680:
Triggering the instruction resulted in a four-cycle process. In the first cycle the lower 6 bits of the instruction, including the 4 bit free field, were put on the H bus while the value of the accumulator was put on the L bus. The device could then read both to decode its instruction. On the second cycle, if the CPU was to send data to the device for output, the 8-bit value was put on the bus. On the third, any data being sent to the CPU was returned on the bus. The fourth indicated the end of the I/O cycle.
547:. On the receipt of an interrupt, the processor completed the current instruction and then pointed to the selected set of these registers, or as they called them, "levels". This allowed the system to track three separate sections of code, corresponding to normal operation and two interrupt levels. External devices could raise an interrupt on two pins,
688:
The main bus was multiplexed, with a total of 16 pins used for both addressing and data. The bus was split into "high" (H) and "low" (L) sides, both 8-bits. During a memory access, the 15-bit address would be placed on the high and low sides, and then the data at that location read or written using
668:
For branches, subroutine calls and jumps, a second format was used where the opcode used the upper 4 bits, and the lower 4 bits along with the 8-bit operand form a 12-bit address. This meant code could only call other code within a 4 kB "block". There were many other instruction formats for special
559:
was enabled and triggered, the processor responded by completing the current instruction, switching to the level 2 registers, and continuing. Normal operation was level 3, which it returned to when a return-from-interrupt instruction was called. This makes interrupt servicing very rapid because the
640:
Indirect addresses used a two-step access pattern. First the processor reads lower 8-bits of the instruction and looks at bit 0 to see which offset to use. It then reads the byte at that location and the following byte, producing a 16-bit value held in a special buffer. It would then read or write
679:
and was handled through special instructions. The upper 4 bits of the opcode held the I/O instruction (input, output, status, etc.), while the lower 4 bits were a "free field". The program could place any value in these 4 bits and use it as an ad-hoc data field to send instructions to the device.
652:
of every address stored in memory was used to specify whether it was a direct or indirect address, this left 15-bits for the actual address, allowing up to 32 kB of memory. Since the address being pointed to by an indirect address might also have its high bit set, indirect addresses can form
627:
Those instructions that used memory (as opposed to registers) used a two-byte format with the opcode in the upper 6 bits of the first byte. The lower 2 bits controlled the type of memory access. The first (bit 1) indicated whether the following 8-bit operand was a direct or indirect address. The
632:
defined by the program counter, or in the zero page. The following operand byte contains an 8 bit address. This means that when using direct addressing, the data has to lie within 256 bytes of the current instruction, or within the first 256 bytes of memory. If access to the greater
563:
The same system could also be used for fast subroutine calls instead of having to store out the register contents. As the processor state was saved separately, only the return address had to be explicitly written out in code. In this case, the first 256 locations in memory, the
587:
pin that was raised by an external device that wanted access to memory. When this signal was received, the processor would continue with the current instruction, including any required reading and writing from memory. When the instruction was complete it would raise the
212:, a German competitor to Olivetti. The F8 had a number of design features that made it very easy to implement, with typical designs requiring only two chips to provide all the needed ROM, RAM, clock and I/O. It also improved on the 5065 in that it was an
515:
In the early 1970s the idea of a microprocessor being used as the basis for a standalone computer was still not common, and designs of the era generally included features intended to make them easy to use in what today would be known as the
223:
line. Mentions of the 5065 disappear by the time their 1975 catalog, which mentions only their version of the F8, the MK3850. Mostek aggressively lowered the price of their F8 over the next year, reaching $ 10 in plastic packaging by 1976.
572:. For this to work, this area had to be implemented in some form of writable memory. The page could hold up to 128 16-bit addresses, with the current value indicated by the "pointer register", what would be known as the
731:. The ROM contained the "Program Aid Routine", a small system development tool and debugger utility. The processor board and PAR ROM was $ 597, the 12k RAM card another $ 597, or both together were $ 995. A
738:
Clock speeds for the 5065 do not appear in any surviving references. Instruction times are listed as 3 to 16 μsec. Although the instruction times are cited as 3 to 16 μsec, a 1 MHz clock can be used.
723:
The system was released with an evaluation system, the two-board GEMS-8, short for
General Evaluation Microprocessor System. This included the clock driver, 512 bytes of ROM, 1 to 12 kB of RAM, and a
197:
under the condition they did not sell into the calculator market. Mostek launched their version in
February 1974. By early 1975 it was in volume production and sold for $ 58 in lots from 100 to 499.
712:, as was common for most processors of the era. The use of the multiplexed bus reduced pin use to the point that five pins were left unconnected. As was the case for most PMOS designs, an external
560:
state information is being stored automatically in a single cycle, whereas many designs require this information to be stored out using user-written code that may take multiple cycles to complete.
150:
was introduced at about the same time, aimed at the same markets. The F8 had a number of advantages over the 5065 due to its more modern design. In June 1975, Mostek licensed the F8 under a
208:
with sample shipments starting the next April and full production later that year. The F8 was almost identical to the 5065 in purpose, originally designed as a calculator CPU for
689:
the L bus only. This meant that memory accesses required two cycles, making it slower than designs with separate (non-multiplexed) address and data busses.
1128:
1061:
135:, and was licensed to Mostek for use in non-calculator roles. It featured three sets of processor registers, allowing it to switch to an
754:
Plastic packaging was suitable for low-speed use where heat was not a concern. For higher speeds a ceramic package was available at $ 20.
592:
pin to indicate it was ready and then went into a paused state. The external device would then perform its DMA operations and then drop
532:. As this is a common operation in these settings, many designs focused on ways to improve interrupt performance or implementation.
157:
Still convinced that they needed a microprocessor, and learning from their experience on the 5065, Motorola began design of their
1046:
190:
216:-based chip, allowing it to be fabricated at a smaller feature size which lowered its cost and allowed it to run much faster.
1149:
608:
There were a total of 51 instructions, and 81 opcodes. The instructions come in many formats, but most of them in two-byte
717:
146:
Despite a relatively low cost (for the era) of $ 58 in quantities of 100, the 5065 appears to have seen little use. The
1076:
793:
536:
201:
60:
154:
arrangement. The 5065 disappeared from Mostek's 1975 catalog, which mentions only their F8, the MK3850.
132:
649:
580:
535:
In the case of the 5065, this was accomplished by providing three separate sets of registers for the
140:
101:
709:
696:
process that was common in the early 1970s, the 5065 required three voltage supply levels, -12V (V
1034:
178:
528:. These systems have to respond quickly to different inputs, which is normally accomplished via
1116:
998:
Personal experience designing and building a MK5065 based system, by a former a Mostek engineer
728:
676:
662:
1026:
617:
732:
540:
517:
219:
In June 1975, Mostek licensed the F8 design from
Fairchild and brought it up on their new
117:
1005:
764:
1104:
1143:
573:
521:
505:
209:
158:
151:
653:
chains. This style of chained access was also seen on minicomputer systems like the
1038:
713:
672:
642:
205:
147:
634:
629:
186:
1018:
693:
628:
second (bit 0) controlled whether the 8-bit value was offset from the current
569:
544:
220:
213:
170:
63:
645:
of the era, as it made certain forms of looping over data easy to implement.
1030:
621:
565:
529:
136:
555:, both of which could be turned on or off in software. So for instance, if
193:
proved unable to produce the design, and they were forced to license it to
716:
was required, in this case the MK5009. There were also plans to release a
763:
The other common solution of the era, not used in the 5065, is dedicated
654:
616:
pairs. A small number of one-byte instructions were used for things like
525:
182:
174:
129:
125:
658:
613:
609:
194:
121:
44:
641:
the data to that 16-bit location. This pattern was commonly seen on
1006:"Development of the MOS Technology 6502: A Historical Perspective"
794:"Motorola's Pioneering 8-bit 6800 : Origins and Architecture"
724:
139:
handler in a single cycle, and a wait-for-data mode that aided
735:
was also available for an unspecified "16-bit minicomputer".
1019:"New Products: Mostek Announces GEMS-8 Microcomputer System"
520:
area, processors that are used to control a device like a
1117:"Introduction to Microcontrollers: Interrupt Processing"
596:
when it was finished. The processor would then drop the
161:
almost immediately after licensing the 5065 to Mostek.
939:
937:
935:
922:
920:
918:
856:
854:
543:
and the internal "main link" register, along with the
124:
in early 1974. The design was originally developed by
905:
903:
901:
899:
897:
895:
893:
817:
815:
813:
811:
809:
807:
597:
593:
589:
584:
556:
552:
548:
93:
88:
80:
72:
58:
53:
37:
29:
24:
624:, which do not need any additional information.
1105:"Introduction to Microcontrollers - Interrupts"
185:. The design effort was led by Rod Orgill and
1129:"Programming a Loop with Indirect Addressing"
637:is needed, indirect addressing must be used.
600:pin, unpause, and pick up where it left off.
583:(DMA) implementations, the system included a
8:
19:
708:) and ground. It was packaged in a 40-pin
189:, producing the 5065. Motorola's existing
1056:. Vol. 1, no. 8. February 1975.
1017:Michalopoulos, Demetrios (October 1975).
665:, but was uncommon for microprocessors.
955:
785:
747:
979:
860:
821:
236:
18:
967:
943:
926:
909:
872:
845:
7:
1096:Digital Electronics And Logic Design
833:
884:
14:
1103:Silva, Mike (18 September 2013).
1:
1047:"Mostek 5065's by the 1000's"
1004:Sachs, Jason (18 June 2022).
1094:Nair, B. Somanathan (2002).
1081:. Vol. 3. Mostek. 1974.
996:Franks, Kirk (16 May 2023),
718:peripheral interface adaptor
604:Instructions and addressing
169:The 5065 began as a custom
1166:
470:
454:
444:
421:
408:
398:
375:
362:
352:
329:
502:
460:
457:
441:
432:
429:
411:
395:
386:
383:
365:
349:
340:
337:
1087:Integrated Circuit Guide
1078:Integrated Circuit Guide
1062:"Mostek Cuts F8 Prices"
1031:10.1109/C-M.1975.218783
202:Fairchild Semiconductor
89:Physical specifications
618:return-from-subroutine
238:Mostek 5065 registers
1150:8-bit microprocessors
133:electronic calculator
1069:Microcomputer Digest
1054:MicroComputer Digest
720:(PIA) in late 1975.
650:most significant bit
581:direct memory access
141:direct memory access
118:8-bit microprocessor
16:8-bit microprocessor
800:. 11 December 2023.
239:
200:In September 1974,
38:Common manufacturer
25:General information
21:
1135:. 29 January 2007.
576:on other designs.
237:
179:desktop calculator
970:, pp. 80–82.
729:computer terminal
707:
703:
699:
663:Data General Nova
513:
512:
110:
109:
1157:
1136:
1124:
1112:
1109:Embedded Related
1099:
1090:
1082:
1072:
1066:
1057:
1051:
1042:
1013:
1010:Embedded Related
1000:
983:
977:
971:
965:
959:
953:
947:
941:
930:
924:
913:
907:
888:
882:
876:
870:
864:
858:
849:
843:
837:
831:
825:
819:
802:
801:
790:
768:
761:
755:
752:
705:
701:
697:
599:
595:
591:
586:
568:, was used as a
558:
554:
550:
507:Pointer Register
240:
22:
1165:
1164:
1160:
1159:
1158:
1156:
1155:
1154:
1140:
1139:
1127:
1115:
1102:
1098:. PHI Learning.
1093:
1089:. Mostek. 1975.
1085:
1075:
1071:. October 1976.
1064:
1060:
1049:
1045:
1016:
1003:
995:
992:
987:
986:
978:
974:
966:
962:
954:
950:
942:
933:
925:
916:
908:
891:
883:
879:
871:
867:
859:
852:
844:
840:
832:
828:
820:
805:
798:The Chip Letter
792:
791:
787:
782:
777:
772:
771:
765:index registers
762:
758:
753:
749:
744:
733:cross assembler
727:for use with a
686:
606:
541:program counter
518:microcontroller
474:
425:
379:
333:
320:
315:
310:
305:
300:
295:
290:
285:
280:
275:
270:
265:
260:
255:
250:
245:
235:
230:
181:being built by
167:
106:
49:
17:
12:
11:
5:
1163:
1161:
1153:
1152:
1142:
1141:
1138:
1137:
1125:
1113:
1100:
1091:
1083:
1073:
1058:
1043:
1014:
1001:
991:
988:
985:
984:
972:
960:
948:
931:
914:
889:
877:
865:
850:
838:
836:, p. 237.
826:
803:
784:
783:
781:
778:
776:
773:
770:
769:
756:
746:
745:
743:
740:
685:
682:
605:
602:
511:
510:
503:
501:
498:
495:
492:
489:
486:
483:
480:
476:
475:
468:
467:
462:
459:
456:
452:
451:
446:
443:
439:
438:
433:
431:
427:
426:
419:
418:
413:
410:
406:
405:
400:
397:
393:
392:
387:
385:
381:
380:
373:
372:
367:
364:
360:
359:
354:
351:
347:
346:
341:
339:
335:
334:
327:
326:
324:(bit position)
321:
318:
316:
313:
311:
308:
306:
303:
301:
298:
296:
293:
291:
288:
286:
283:
281:
278:
276:
273:
271:
268:
266:
263:
261:
258:
256:
253:
251:
248:
246:
243:
234:
231:
229:
226:
173:CPU design by
166:
163:
128:for use in an
120:introduced by
108:
107:
105:
104:
97:
95:
91:
90:
86:
85:
82:
78:
77:
74:
70:
69:
66:
56:
55:
51:
50:
48:
47:
41:
39:
35:
34:
31:
27:
26:
15:
13:
10:
9:
6:
4:
3:
2:
1162:
1151:
1148:
1147:
1145:
1134:
1130:
1126:
1122:
1118:
1114:
1110:
1106:
1101:
1097:
1092:
1088:
1084:
1080:
1079:
1074:
1070:
1063:
1059:
1055:
1048:
1044:
1040:
1036:
1032:
1028:
1024:
1023:IEEE Computer
1020:
1015:
1011:
1007:
1002:
999:
994:
993:
989:
981:
976:
973:
969:
964:
961:
957:
952:
949:
946:, p. 78.
945:
940:
938:
936:
932:
929:, p. 79.
928:
923:
921:
919:
915:
912:, p. 80.
911:
906:
904:
902:
900:
898:
896:
894:
890:
886:
881:
878:
874:
869:
866:
863:, p. 13.
862:
857:
855:
851:
847:
842:
839:
835:
830:
827:
823:
818:
816:
814:
812:
810:
808:
804:
799:
795:
789:
786:
779:
774:
766:
760:
757:
751:
748:
741:
739:
736:
734:
730:
726:
721:
719:
715:
711:
695:
692:Built on the
690:
684:Other details
683:
681:
678:
677:memory mapped
674:
670:
666:
664:
660:
656:
651:
646:
644:
643:minicomputers
638:
636:
631:
625:
623:
619:
615:
611:
603:
601:
582:
577:
575:
574:stack pointer
571:
567:
561:
546:
542:
538:
533:
531:
527:
523:
522:cash register
519:
509:
508:
504:
499:
496:
493:
490:
487:
484:
481:
478:
477:
473:
472:Stack Pointer
469:
466:
463:
453:
450:
447:
440:
437:
434:
428:
424:
420:
417:
414:
407:
404:
401:
394:
391:
388:
382:
378:
374:
371:
368:
361:
358:
355:
348:
345:
342:
336:
332:
328:
325:
322:
317:
312:
307:
302:
297:
292:
287:
282:
277:
272:
267:
262:
257:
252:
247:
242:
241:
232:
227:
225:
222:
217:
215:
211:
210:Olympia-Werke
207:
204:launched the
203:
198:
196:
192:
188:
184:
180:
176:
172:
164:
162:
160:
159:Motorola 6800
155:
153:
152:second source
149:
144:
142:
138:
134:
131:
127:
123:
119:
115:
114:Mostek MK5065
103:
99:
98:
96:
92:
87:
83:
81:Address width
79:
75:
71:
67:
65:
62:
57:
52:
46:
43:
42:
40:
36:
33:February 1974
32:
28:
23:
1132:
1120:
1108:
1095:
1086:
1077:
1068:
1053:
1022:
1009:
997:
990:Bibliography
975:
963:
956:Siemens 2007
951:
880:
868:
841:
829:
824:, p. 2.
797:
788:
759:
750:
737:
722:
691:
687:
673:Input/output
671:
667:
647:
639:
626:
607:
578:
562:
534:
514:
506:
471:
464:
448:
435:
422:
415:
402:
389:
376:
369:
356:
343:
330:
323:
233:Basic design
218:
206:Fairchild F8
199:
168:
156:
148:Fairchild F8
145:
113:
111:
980:Franks 2023
861:Digest 1976
822:Digest 1975
635:main memory
630:memory page
537:accumulator
436:Accumulator
390:Accumulator
344:Accumulator
228:Description
187:Bill Mensch
68:3 μsec
54:Performance
20:Mostek 5065
968:Guide 1974
944:Guide 1974
927:Guide 1974
910:Guide 1974
873:Silva 2013
846:Guide 1975
775:References
714:clock chip
669:purposes.
622:shift-left
570:call stack
545:carry flag
530:interrupts
73:Data width
64:clock rate
834:Nair 2002
780:Citations
704:), -5V (V
566:zero page
137:interrupt
1144:Category
700:), +5V(V
675:was not
655:IBM 1620
526:gas pump
465:Aux/Link
183:Olivetti
175:Motorola
130:Olivetti
126:Motorola
30:Launched
1133:Siemens
1121:Renesas
1039:2862689
885:Renesas
659:HP 2100
614:operand
579:To aid
455:
430:
423:Level 3
409:
384:
377:Level 2
363:
338:
331:Level 1
165:History
116:was an
100:40-pin
94:Package
84:15 bits
1037:
610:opcode
195:Mostek
177:for a
122:Mostek
76:8 bits
45:Mostek
1065:(PDF)
1050:(PDF)
1035:S2CID
742:Notes
557:INT 2
553:INT 2
549:INT 1
59:Max.
725:UART
694:PMOS
661:and
648:The
594:WAIT
585:WAIT
551:and
445:PCL
442:PCH
416:Link
399:PCL
396:PCH
370:Link
353:PCL
350:PCH
221:NMOS
214:NMOS
191:fabs
171:PMOS
112:The
1027:doi
710:DIP
620:or
598:DMA
590:DMA
524:or
102:DIP
61:CPU
1146::
1131:.
1119:.
1107:.
1067:.
1052:.
1033:.
1025:.
1021:.
1008:.
934:^
917:^
892:^
853:^
806:^
796:.
706:DD
702:SS
698:GG
657:,
539:,
500:0
497:0
494:0
491:0
488:0
485:0
482:0
479:0
461:L
458:A
449:PC
412:L
403:PC
366:L
357:PC
143:.
1123:.
1111:.
1041:.
1029::
1012:.
982:.
958:.
887:.
875:.
848:.
767:.
612:-
319:0
314:1
309:2
304:3
299:4
294:5
289:6
284:7
279:8
274:9
269:0
264:1
259:2
254:3
249:4
244:5
Text is available under the Creative Commons Attribution-ShareAlike License. Additional terms may apply.