28:
226:, the result is a wide instruction that operates on one or more fields of the PHV and data to support this instruction. The output PHV is then sent to the next MA stage or to the deparser. The deparser takes in the PHV as well as the original packet and it's metadata (to fill in missing bits that weren't extracted into the PHV) and then outputs the modified packet as chunks. It's typically programmable as with the parser and may reuse some of the configuration files.
218:...) and extracts certain fields from the packet into the Packet Header Vector (PHV). Certain fields in the PHV may be reserved for special uses such as present headers or total packet length. The protocols are typically programmable, and so are the fields to extract. The Match-Action tables are a series of units that read an input PHV, match certain fields in it using a
198:
335:
Using the generic function of the network processor, a software program implements an application that the network processor executes, resulting in the piece of physical equipment performing a task or providing a service. Some of the applications types typically implemented as software running on
326:
network processing and used to be executed by a variety of co-processors, has become an integral part of the network processor architecture, and a substantial part of its silicon area ("real estate") is devoted to the integrated traffic manager. Modern network processors are also equipped with
327:
low-latency high-throughput on-chip interconnection networks optimized for the exchange of small messages among cores (few data words). Such networks can be used as an alternative facility for the efficient inter-core communication aside of the standard use of shared memory.
205:
An RMT pipeline relies on three main stages; the programmable parser, the Match-Action tables and the programmable deparser. The parser reads the packet in chunks and processes these chunks to find out which protocols are used in the packet
181:
Reconfigurable Match-Tables were introduced in 2013 to allow switches to operate at high speeds while maintaining flexibility when it comes to the network protocols running on them, or the processing to does to them.
101:
Network processors have evolved into ICs with specific functions. This evolution has resulted in more complex and more flexible ICs being created. The newer circuits are programmable and thus allow a single
98:(IC) that are optimised to deal with this form of packet data. Network processors have specific features or architectures that are provided to enhance and optimise packet processing within these networks.
361:(QoS) enforcement – identifying different types or classes of packets and providing preferential treatment for some types or classes of packet at the expense of other types or classes of packet.
2724:
1753:
457:
267:
Control processing – the micro operations of processing a packet are controlled at a macro level which involves communication and orchestration with other nodes in a system.
2994:
725:
2668:
1864:
1047:
1566:
564:
Kaufmann, Antoine; Peter, SImon; Sharma, Naveen Kr.; Anderson, Thomas; Krishnamurthy, Arvind (2016-03-25). "High
Performance Packet Processing with FlexNIC".
1723:
1289:
1106:
416:
1069:
1718:
241:
In the generic role as a packet processor, a number of optimised features or functions are typically present in a network processor, which include:
662:
364:
Access
Control functions – determining whether a specific packet or stream of packets should be allowed to traverse the piece of network equipment.
2823:
1790:
27:
1543:
293:
691:
656:
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583:
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233:
allowing servers to send and receive packets at high speeds while maintaining protocol flexibility and without increasing the CPU overhead.
2487:
1611:
874:
718:
248:
Key lookup – the ability to quickly undertake a database lookup using a key (typically an address in a packet) to find a result, typically
456:
Bosshart, Pat; Gibb, Glen; Kim, Hun-Seok; Varghese, George; McKeown, Nick; Izzard, Martin; Mujica, Fernando; Horowitz, Mark (2013-08-01).
2661:
2497:
1638:
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1606:
985:
83:
956:
2863:
2746:
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2183:
1076:
1042:
1037:
921:
566:
Proceedings of the Twenty-First
International Conference on Architectural Support for Programming Languages and Operating Systems
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of data streams – built in hardware-based encryption engines allow individual data flows to be encrypted by the processor.
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2232:
2077:
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1994:
1470:
1431:
1086:
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Data bitfield manipulation – the ability to change certain data fields contained in the packet as it is being processed.
230:
951:
1859:
1556:
1254:
643:. 2014 International Conference on High Performance Computing Simulation (HPCS 2014). Bologna, Italy. pp. 55–64.
154:
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of processors - each stage of the pipeline consisting of a processor performing one of the functions listed above.
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management – as packets are received, processed and scheduled to be sent onwards, they are stored in queues.
245:
Pattern matching – the ability to find specific patterns of bits or bytes within packets in a packet stream.
55:
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95:
40:
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Run-time mechanisms for fine-grained parallelism on network processors: The TILEPro64 experience
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2017:
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165:
75:
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2168:
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2012:
2007:
2002:
1941:
1849:
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1561:
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1348:
1111:
995:
963:
864:
859:
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478:
426:
279:
In order to deal with high data-rates, several architectural paradigms are commonly used:
219:
125:
458:"Forwarding Metamorphosis: Fast Programmable Match-Action Processing in Hardware for SDN"
78:) which is in contrast to older telecommunications networks that carried information as
2936:
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2751:
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352:
207:
129:
54:
programmable devices and would have generic characteristics similar to general purpose
17:
568:. ASPLOS '16. New York, NY, USA: Association for Computing Machinery. pp. 67–81.
2968:
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1381:
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79:
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508:
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106:
IC design to undertake a number of different functions, where the appropriate
2868:
2397:
2394:
2136:
1206:
1184:
574:
495:
Gibb, Glen; Varghese, George; Horowitz, Mark; McKeown, Nick (October 2013).
323:
319:
311:
300:
113:
Network processors are used in the manufacture of many different types of
94:
networks. The processing of these packets has resulted in the creation of
58:
that are commonly used in many different types of equipment and products.
2873:
2811:
2412:
1284:
1231:
703:
411:
107:
51:
2646:
1221:
1179:
249:
541:"P4: Programming Protocol-Independent Packet Processors | acm sigcomm"
2778:
2524:
1236:
1201:
1166:
540:
684:
Network
Systems Design Using Network Processors: Intel 2XXX Version
608:
197:
1694:
1226:
1196:
196:
191:
91:
610:
Network
Processors: Architecture, Programming, and Implementation
347:
discrimination and forwarding, that is, the basic operation of a
318:
Additionally, traffic management, which is a critical element in
2558:
1706:
1626:
1216:
310:
architectures, network processors can be used for higher layer (
215:
2650:
707:
1146:
1136:
190:
was based around these processors and was later purchased by
87:
303:
engines to more efficiently accomplish the tasks at hand.
501:
Architectures for
Networking and Communications Systems
634:
Buono, Daniele; Mencagli, Gabriele (21–25 July 2014).
270:
Quick allocation and re-circulation of packet buffers.
70:, information (voice, video, data) is transferred as
43:
which has a feature set specifically targeted at the
2902:
2849:
2799:
2712:
2684:
2588:
2537:
2473:
2411:
2365:
2317:
2272:
2192:
2119:
2088:
1993:
1914:
1878:
1832:
1732:
1658:
1592:
1542:
1453:
1444:
1417:
1372:
1339:
1311:
1302:
1122:
1025:
1014:
885:
741:
2662:
719:
8:
1724:Computer performance by orders of magnitude
417:List of defunct network processor companies
2669:
2655:
2647:
2189:
1829:
1450:
1308:
1022:
726:
712:
704:
292:with multiple processors, often including
186:is used to program the chips. The company
573:
2995:Application-specific integrated circuits
229:FlexNIC attempts to apply this model to
26:
613:. Systems on Silicon. Morgan Kaufmann.
448:
497:"Design principles for packet parsers"
474:
463:
7:
1695:Floating-point operations per second
490:
488:
668:from the original on 27 March 2019.
25:
2747:Hardware random number generation
84:public switched telephone network
50:Network processors are typically
2621:Semiconductor device fabrication
2596:History of general-purpose CPUs
823:Nondeterministic Turing machine
776:Deterministic finite automaton
1:
1567:Simultaneous and heterogenous
231:Network Interface Controllers
2251:Integrated memory controller
2233:Translation lookaside buffer
1432:Memory dependence prediction
875:Random-access stored program
828:Probabilistic Turing machine
437:Network interface controller
155:Intrusion prevention devices
1707:Synaptic updates per second
649:10.1109/HPCSim.2014.6903669
177:Reconfigurable Match-Tables
150:Intrusion detection devices
68:telecommunications networks
3016:
2111:Heterogeneous architecture
1033:Orthogonal instruction set
803:Alternating Turing machine
791:Quantum cellular automaton
682:Comer, Douglas E. (2005).
145:Session border controllers
2742:Digital signal processing
2601:Microprocessor chronology
2564:Dynamic frequency scaling
1719:Cache performance metrics
509:10.1109/ANCS.2013.6665172
397:Knowledge-based processor
2975:Embedded microprocessors
2694:Universal Turing machine
2616:Hardware security module
1959:Digital signal processor
1936:Graphics processing unit
1748:Graphics processing unit
422:Network Processing Forum
336:network processors are:
201:RMP Pipeline Description
134:Inter-network processors
56:central processing units
2752:Artificial intelligence
2569:Dynamic voltage scaling
2352:Memory address register
2246:Branch target predictor
2210:Address generation unit
1953:Physics processing unit
1742:Central processing unit
1701:Transactions per second
1689:Instructions per second
1612:Array processing (SIMT)
756:Stored-program computer
575:10.1145/2872362.2872367
275:Architectural paradigms
170:secure cryptoprocessors
18:Network Processing Unit
2774:Custom hardware attack
2375:Hardwired control unit
2257:Memory management unit
2222:Memory management unit
1971:Secure cryptoprocessor
1965:Tensor Processing Unit
1947:Vision processing unit
1681:Cycles per instruction
1675:Instructions per cycle
1622:Associative processing
1313:Instruction pipelining
735:Processor technologies
473:Cite journal requires
202:
62:History of development
32:
2990:Hardware acceleration
2704:Distributed computing
2678:Hardware acceleration
2458:Sum-addressed decoder
2204:Arithmetic logic unit
1331:Classic RISC pipeline
1285:Epiphany architecture
1132:Motorola 68000 series
200:
30:
2807:High-level synthesis
2579:Performance per watt
2157:replacement policies
1823:Package on a package
1713:Performance per watt
1617:Pipelined processing
1387:Tomasulo's algorithm
1192:Clipper architecture
1048:Application-specific
761:Finite-state machine
607:Giladi, Ran (2008).
407:Computer engineering
392:Multi-core processor
47:application domain.
2985:Networking hardware
2932:Digital electronics
2884:In-memory computing
2864:Transport triggered
2611:Digital electronics
2264:Instruction decoder
2216:Floating-point unit
1870:Soft microprocessor
1817:System in a package
1392:Reservation station
922:Transport-triggered
306:With the advent of
290:Parallel processing
96:integrated circuits
2942:Hardware emulation
2910:Programmable logic
2699:Parallel computing
2483:Integrated circuit
2327:Processor register
1981:Baseband processor
1326:Operand forwarding
786:Cellular automaton
686:. Addison-Wesley.
503:. pp. 13–24.
359:Quality of service
203:
160:Network monitoring
41:integrated circuit
33:
2980:Network on a chip
2962:
2961:
2839:Network on a chip
2644:
2643:
2533:
2532:
2152:Instruction cache
2142:Scratchpad memory
1989:
1988:
1976:Network processor
1905:Network on a chip
1860:Ultra-low-voltage
1811:Multi-chip module
1654:
1653:
1440:
1439:
1427:Branch prediction
1404:Register renaming
1298:
1297:
1280:VISC architecture
1102:Quantum computing
1097:VISC architecture
979:Secondary storage
895:Microarchitecture
855:Register machines
693:978-0-13-187286-8
658:978-1-4799-5313-4
620:978-0-12-370891-5
585:978-1-4503-4091-5
518:978-1-4799-1641-2
432:Network on a chip
402:Active networking
387:Content processor
237:Generic functions
188:Barefoot Networks
115:network equipment
86:(PSTN) or analog
37:network processor
16:(Redirected from
3007:
3000:System on a chip
2954:Embedded systems
2834:System on a chip
2671:
2664:
2657:
2648:
2606:Processor design
2498:Power management
2380:Instruction unit
2241:Branch predictor
2190:
1888:System on a chip
1830:
1670:Transistor count
1594:Flynn's taxonomy
1451:
1309:
1112:Addressing modes
1023:
969:Memory hierarchy
833:Hypercomputation
751:Abstract machine
728:
721:
714:
705:
698:
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679:
673:
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667:
642:
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537:
531:
530:
492:
483:
482:
476:
471:
469:
461:
453:
166:Network security
126:software routers
76:packet switching
31:Intel FWIXP422BB
21:
3015:
3014:
3010:
3009:
3008:
3006:
3005:
3004:
2965:
2964:
2963:
2958:
2949:Logic synthesis
2898:
2845:
2800:Implementations
2795:
2708:
2680:
2675:
2645:
2640:
2626:Tick–tock model
2584:
2540:
2529:
2469:
2453:Address decoder
2407:
2361:
2357:Program counter
2332:Status register
2313:
2268:
2228:Load–store unit
2195:
2188:
2115:
2084:
1985:
1942:Image processor
1917:
1910:
1880:
1874:
1850:Microcontroller
1840:Embedded system
1828:
1728:
1661:
1650:
1588:
1538:
1436:
1413:
1397:Re-order buffer
1368:
1349:Data dependency
1335:
1294:
1124:
1118:
1017:
1016:Instruction set
1010:
996:Multiprocessing
964:Cache hierarchy
957:Register/memory
881:
781:Queue automaton
737:
732:
702:
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681:
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545:www.sigcomm.org
539:
538:
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472:
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455:
454:
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427:Queueing theory
383:
333:
277:
239:
179:
82:such as in the
64:
23:
22:
15:
12:
11:
5:
3013:
3011:
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2937:Virtualization
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2889:Systolic array
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2769:Machine vision
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2631:Pin grid array
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2465:Barrel shifter
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2448:Binary decoder
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2337:Stack register
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1950:
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1939:
1933:
1931:AI accelerator
1928:
1922:
1920:
1912:
1911:
1909:
1908:
1902:
1897:
1894:Multiprocessor
1891:
1884:
1882:
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1873:
1872:
1867:
1862:
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1847:
1845:Microprocessor
1842:
1836:
1834:
1833:By application
1827:
1826:
1820:
1814:
1808:
1803:
1798:
1793:
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1776:Tile processor
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974:Virtual memory
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798:Turing machine
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475:|journal=
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294:multithreading
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110:is installed.
80:analog signals
63:
60:
24:
14:
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10:
9:
6:
4:
3:
2:
3012:
3001:
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2895:
2892:
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2880:
2879:Heterogeneous
2877:
2875:
2872:
2870:
2867:
2865:
2862:
2860:
2857:
2856:
2854:
2852:
2851:Architectures
2848:
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2426:Demultiplexer
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2347:Memory buffer
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2342:Register file
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2282:Combinational
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2014:
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1382:Scoreboarding
1380:
1379:
1377:
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1371:
1365:
1364:False sharing
1362:
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1163:
1160:
1158:
1157:Stanford MIPS
1155:
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1138:
1135:
1133:
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1129:
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1046:
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1039:
1036:
1034:
1031:
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1024:
1021:
1019:
1018:architectures
1013:
1007:
1004:
1002:
999:
997:
994:
992:
989:
987:
986:Heterogeneous
984:
980:
977:
975:
972:
971:
970:
967:
965:
962:
958:
955:
953:
950:
948:
945:
943:
940:
939:
938:
937:Memory access
935:
933:
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928:
925:
923:
920:
918:
915:
911:
908:
907:
906:
903:
901:
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890:
888:
884:
876:
873:
871:
870:Random-access
868:
866:
863:
861:
858:
857:
856:
853:
851:
850:Stack machine
848:
846:
843:
839:
836:
834:
831:
829:
826:
824:
821:
819:
816:
814:
811:
809:
806:
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799:
796:
792:
789:
787:
784:
782:
779:
777:
774:
772:
769:
767:
766:with datapath
764:
763:
762:
759:
757:
754:
752:
749:
748:
746:
744:
740:
736:
729:
724:
722:
717:
715:
710:
709:
706:
695:
689:
685:
678:
675:
672:
664:
660:
654:
650:
646:
639:
638:
630:
627:
622:
616:
612:
611:
603:
600:
595:
591:
587:
581:
576:
571:
567:
560:
557:
546:
542:
536:
533:
528:
524:
520:
514:
510:
506:
502:
498:
491:
489:
485:
480:
467:
459:
452:
449:
442:
438:
435:
433:
430:
428:
425:
423:
420:
418:
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398:
395:
393:
390:
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385:
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375:
372:
369:
366:
363:
360:
357:
354:
350:
346:
342:
339:
338:
337:
330:
328:
325:
321:
314:) processing.
313:
309:
305:
302:
298:
295:
291:
288:
285:
282:
281:
280:
274:
269:
266:
263:
260:
257:
254:
251:
247:
244:
243:
242:
236:
234:
232:
227:
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209:
199:
195:
193:
189:
185:
176:
171:
167:
164:
161:
158:
156:
153:
151:
148:
146:
143:
141:
138:
135:
131:
127:
123:
120:
119:
118:
116:
111:
109:
105:
99:
97:
93:
89:
85:
81:
77:
74:data (termed
73:
69:
61:
59:
57:
53:
48:
46:
42:
38:
29:
19:
2894:Neuromorphic
2785:
2757:Cryptography
2713:Applications
2636:Chip carrier
2574:Clock gating
2493:Mixed-signal
2390:Write buffer
2367:Control unit
2179:Clock signal
1975:
1918:accelerators
1900:Cypress PSoC
1557:Simultaneous
1374:Out-of-order
1006:Neuromorphic
887:Architecture
845:Belt machine
838:Zeno machine
771:Hierarchical
683:
677:
636:
629:
609:
602:
565:
559:
548:. Retrieved
544:
535:
500:
466:cite journal
451:
334:
331:Applications
317:
299:Specialized
278:
252:information.
240:
228:
204:
180:
112:
100:
65:
49:
36:
34:
2421:Multiplexer
2385:Data buffer
2096:Single-core
2068:bit slicing
1926:Coprocessor
1781:Coprocessor
1662:performance
1584:Cooperative
1574:Speculative
1534:Distributed
1493:Superscalar
1478:Instruction
1446:Parallelism
1419:Speculative
1251:System/3x0
1123:Instruction
900:Von Neumann
813:Post–Turing
374:TCP offload
255:Computation
2969:Categories
2925:chronology
2786:Networking
2541:management
2436:Multiplier
2297:Logic gate
2287:Sequential
2194:Functional
2174:Clock rate
2147:Data cache
2120:Components
2101:Multi-core
2089:Core count
1579:Preemptive
1483:Pipelining
1466:Bit-serial
1409:Wide-issue
1354:Structural
1276:Tilera ISA
1242:MicroBlaze
1212:ETRAX CRIS
1107:Comparison
952:Load–store
932:Endianness
550:2022-03-26
443:References
376:processing
368:Encryption
301:microcoded
224:CAM memory
66:In modern
45:networking
2915:Processor
2869:Multicore
2475:Circuitry
2395:Microcode
2319:Registers
2162:coherence
2137:CPU cache
1995:Word size
1660:Processor
1304:Execution
1207:DEC Alpha
1185:Power ISA
1001:Cognitive
808:Universal
308:multicore
194:in 2019.
140:Firewalls
117:such as:
2874:Manycore
2859:Dataflow
2812:C to HDL
2413:Datapath
2106:Manycore
2078:variable
1916:Hardware
1552:Temporal
1232:OpenRISC
927:Cellular
917:Dataflow
910:modified
663:Archived
527:12282067
412:Internet
381:See also
284:Pipeline
220:crossbar
208:Ethernet
130:switches
108:software
104:hardware
52:software
2903:Related
2730:DirectX
2589:Related
2520:Quantum
2510:Digital
2505:Boolean
2403:Counter
2302:Quantum
2063:512-bit
2058:256-bit
2053:128-bit
1896:(MPSoC)
1881:on chip
1879:Systems
1697:(FLOPS)
1510:Process
1359:Control
1341:Hazards
1227:Itanium
1222:Unicore
1180:PowerPC
905:Harvard
865:Pointer
860:Counter
818:Quantum
671:Alt URL
594:9625891
250:routing
162:systems
122:Routers
2920:design
2779:scrypt
2686:Theory
2525:Switch
2515:Analog
2253:(IMC)
2224:(MMU)
2073:others
2048:64-bit
2043:48-bit
2038:32-bit
2033:24-bit
2028:16-bit
2023:15-bit
2018:12-bit
1855:Mobile
1771:Stream
1766:Barrel
1761:Vector
1750:(GPU)
1709:(SUPS)
1677:(IPC)
1529:Memory
1522:Vector
1505:Thread
1488:Scalar
1290:Others
1237:RISC-V
1202:SuperH
1171:Power
1167:MIPS-X
1142:PDP-11
991:Fabric
743:Models
690:
655:
617:
592:
582:
525:
515:
353:switch
349:router
341:Packet
72:packet
39:is an
2737:Audio
2725:GPGPU
2581:(PPW)
2539:Power
2431:Adder
2307:Array
2274:Logic
2235:(TLB)
2218:(FPU)
2212:(AGU)
2206:(ALU)
2196:units
2132:Cache
2013:8-bit
2008:4-bit
2003:1-bit
1967:(TPU)
1961:(DSP)
1955:(PPU)
1949:(VPU)
1938:(GPU)
1907:(NoC)
1890:(SoC)
1825:(PoP)
1819:(SiP)
1813:(MCM)
1754:GPGPU
1744:(CPU)
1734:Types
1715:(PPW)
1703:(TPS)
1691:(IPS)
1683:(CPI)
1454:Level
1265:S/390
1260:S/370
1255:S/360
1197:SPARC
1175:POWER
1058:TRIPS
1026:Types
666:(PDF)
641:(PDF)
590:S2CID
523:S2CID
345:frame
312:L4-L7
262:Queue
192:Intel
92:Radio
2829:CPLD
2824:ASIC
2819:FPGA
2791:Data
2559:ACPI
2292:Glue
2184:FIFO
2127:Core
1865:ASIP
1806:CPLD
1801:FPOA
1796:FPGA
1791:ASIC
1644:SPMD
1639:MIMD
1634:MISD
1627:SWAR
1607:SIMD
1602:SISD
1517:Data
1500:Task
1471:Word
1217:M32R
1162:MIPS
1125:sets
1092:ZISC
1087:NISC
1082:OISC
1077:MISC
1070:EPIC
1065:VLIW
1053:EDGE
1043:RISC
1038:CISC
947:HUMA
942:NUMA
688:ISBN
653:ISBN
615:ISBN
580:ISBN
513:ISBN
479:help
222:and
216:IPv4
212:VLAN
128:and
2762:TLS
2720:GPU
2554:APM
2549:PMU
2441:CPU
2398:ROM
2169:Bus
1786:PAL
1461:Bit
1247:LMC
1152:ARM
1147:x86
1137:VAX
645:doi
570:doi
505:doi
351:or
343:or
2971::
2488:3D
661:.
651:.
588:.
578:.
543:.
521:.
511:.
499:.
487:^
470::
468:}}
464:{{
324:L3
320:L2
214:,
210:,
184:P4
124:,
88:TV
35:A
2670:e
2663:t
2656:v
727:e
720:t
713:v
696:.
647::
623:.
596:.
572::
553:.
529:.
507::
481:)
477:(
460:.
355:.
322:-
296:.
206:(
172:)
168:(
136:)
132:(
90:/
20:)
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