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Gunning transceiver logic

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and higher voltage levels. AGTL+ stands for either assisted Gunning transceiver logic or advanced Gunning transceiver logic. These are GTL signaling derivatives used by Intel microprocessors.
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JEDEC Standard JESD8-3A, Gunning Transceiver Logic (GTL) Low-Level, High Speed Interface Standard for Digital Integrated Circuits
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use GTL. As of 2008, GTL in these FSBs has a maximum frequency of 1.6 GHz. The front-side bus of the
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is specified to be 100 MHz, although some applications use higher frequencies. GTL is defined by
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standard JESD 8-3 (1993) and was invented by William Gunning while working for
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logic—and symmetrical parallel resistive termination. The maximum signaling
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swing between 0.4 volts and 1.2 volts—much lower than that used in
258: 195:"GTLP vs. GTL: A Performance Comparison from a System Perspective" 127: 123: 266: 329: 115: 270: 26: 229:"GTL/BTL: A Low-Swing Solution for High-Speed Digital Logic" 421: 351: 304: 153:microprocessors uses GTL+ (or GTLP) developed by 157:, an upgraded version of GTL which has defined 282: 96:) is a type of logic signaling used to drive 8: 289: 275: 267: 412:Current mode logic / Source-coupled logic 77:Learn how and when to remove this message 40:This article includes a list of general 170: 7: 46:it lacks sufficient corresponding 25: 31: 376:Direct-coupled transistor logic 210:, December 2000, archived from 1: 406:Transistor–transistor logic 491: 394:Integrated injection logic 178:Shimpi, Anand Lal (2008), 400:Resistor–transistor logic 388:Gunning transceiver logic 324:Depletion-load NMOS logic 181:Intel's Atom Architecture 132:Palo Alto Research Center 90:Gunning transceiver logic 208:Fairchild Semiconductor 155:Fairchild Semiconductor 61:more precise citations. 364:Diode–transistor logic 382:Emitter-coupled logic 336:Pass transistor logic 352:Other technologies 452: 451: 330:Complementary MOS 242:Texas Instruments 143:Intel Pentium Pro 87: 86: 79: 16:(Redirected from 482: 444:Four-phase logic 326:(including HMOS) 291: 284: 277: 268: 262: 256: 245: 237:Application Note 233: 224: 223: 222: 216: 199: 185: 184: 175: 139:front-side buses 82: 75: 71: 68: 62: 57:this article by 48:inline citations 35: 34: 27: 21: 490: 489: 485: 484: 483: 481: 480: 479: 470:JEDEC standards 455: 454: 453: 448: 417: 347: 300: 295: 265: 254: 248: 231: 227: 220: 218: 214: 197: 193: 189: 188: 177: 176: 172: 167: 83: 72: 66: 63: 53:Please help to 52: 36: 32: 23: 22: 15: 12: 11: 5: 488: 486: 478: 477: 475:Logic families 472: 467: 465:Computer buses 457: 456: 450: 449: 447: 446: 441: 436: 431: 425: 423: 419: 418: 416: 415: 409: 403: 397: 391: 385: 379: 373: 370:Open collector 367: 361: 355: 353: 349: 348: 346: 345: 339: 333: 327: 321: 316: 310: 308: 306:MOS technology 302: 301: 298:Logic families 296: 294: 293: 286: 279: 271: 264: 263: 246: 225: 190: 187: 186: 169: 168: 166: 163: 85: 84: 39: 37: 30: 24: 14: 13: 10: 9: 6: 4: 3: 2: 487: 476: 473: 471: 468: 466: 463: 462: 460: 445: 442: 440: 437: 435: 432: 430: 427: 426: 424: 420: 413: 410: 407: 404: 401: 398: 395: 392: 389: 386: 383: 380: 377: 374: 371: 368: 365: 362: 360: 357: 356: 354: 350: 343: 340: 337: 334: 331: 328: 325: 322: 320: 317: 315: 312: 311: 309: 307: 303: 299: 292: 287: 285: 280: 278: 273: 272: 269: 260: 253: 252: 247: 243: 239: 238: 230: 226: 217:on 2013-09-22 213: 209: 205: 204: 196: 192: 191: 183: 182: 174: 171: 164: 162: 160: 156: 152: 148: 144: 140: 135: 133: 129: 125: 121: 117: 113: 109: 105: 102: 99: 95: 91: 81: 78: 70: 60: 56: 50: 49: 43: 38: 29: 28: 19: 439:Domino logic 387: 342:Bipolar–CMOS 250: 235: 219:, retrieved 212:the original 201: 180: 173: 136: 93: 89: 88: 73: 64: 45: 359:Diode logic 151:Pentium III 106:. It has a 59:introducing 459:Categories 319:NMOS logic 314:PMOS logic 261:, May 2007 221:2008-03-18 165:References 159:slew rates 147:Pentium II 137:All Intel 98:electronic 67:March 2014 42:references 414:(CML/SCL) 120:frequency 101:backplane 344:(BiCMOS) 434:Dynamic 203:AN-1070 130:at the 108:voltage 55:improve 429:Static 378:(DCTL) 332:(CMOS) 244:, 1997 44:, but 422:Types 408:(TTL) 402:(RTL) 390:(GTL) 384:(ECL) 366:(DTL) 338:(PTL) 259:JEDEC 255:(PDF) 232:(PDF) 215:(PDF) 198:(PDF) 128:Xerox 124:JEDEC 104:buses 18:AGTL+ 396:(IL) 372:(OC) 149:and 116:CMOS 114:and 112:TTL 94:GTL 461:: 257:, 240:, 234:, 206:, 200:, 145:, 134:. 290:e 283:t 276:v 92:( 80:) 74:( 69:) 65:( 51:. 20:)

Index

AGTL+
references
inline citations
improve
introducing
Learn how and when to remove this message
electronic
backplane
buses
voltage
TTL
CMOS
frequency
JEDEC
Xerox
Palo Alto Research Center
front-side buses
Intel Pentium Pro
Pentium II
Pentium III
Fairchild Semiconductor
slew rates
Intel's Atom Architecture
"GTLP vs. GTL: A Performance Comparison from a System Perspective"
AN-1070
Fairchild Semiconductor
the original
"GTL/BTL: A Low-Swing Solution for High-Speed Digital Logic"
Application Note
Texas Instruments

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