1316:
1304:
resulting in the instructions executing significantly slower than the same behaviour recreated using other instructions. (A software method called "zp7" is, in fact, faster on these machines.) For optimum performance it is recommended that compiler developers choose to use individual instructions in the extensions based on architecture specific performance profiles rather than on extension availability.
847:
does the opposite for the selected bits: contiguous low-order bits are copied to selected bits of the destination; other destination bits are cleared. This can be used to extract any bitfield of the input, and even do a lot of bit-level shuffling that previously would have been expensive. While
1303:
Note that instruction extension support means the processor is capable of executing the supported instructions for software compatibility purposes. The processor might not perform well doing so. For example, Excavator through Zen 2 processors implement PEXT and PDEP instructions using microcode
201:) instruction, but sets the ZF (if the result is zero) and CF (if the source is zero) flags rather than setting the ZF (if the source is zero). Also, it produces a defined result (the source operand size in bits) if the source operand is zero. For a non-zero argument, sum of
937:
TBM consists of instructions complementary to the instruction set started by BMI1; their complementary nature means they do not necessarily need to be used directly but can be generated by an optimizing compiler when supported. AMD introduced TBM together with BMI1 in its
838:
instructions are new generalized bit-level compress and expand instructions. They take two inputs; one is a source, and the other is a selector. The selector is a bitmap selecting the bits that are to be packed or unpacked.
111:) instruction set, then later added support for Intel's new BMI2 instructions. AMD today advertises the availability of these features via Intel's BMI1 and BMI2 cpuflags and instructs programmers to target them accordingly.
928:
AMD processors before Zen 3 that implement PDEP and PEXT do so in microcode, with a latency of 18 cycles rather than (Zen 3) 3 cycles. As a result it is often faster to use other instructions on these processors.
1685:
652:) instruction, but sets the ZF (if the result is zero) and CF (if the source is zero) flags rather than setting the ZF (if the source is zero). For a non-zero argument, the result of
683:
Intel introduced BMI2 together with BMI1 in its line of
Haswell processors. Only AMD has produced processors supporting BMI1 without BMI2; BMI2 is supported by AMDs
2600:
1590:
2439:
2403:
2293:
75:
microarchitecture with BMI1 matching features offered by AMD's ABM instruction set and BMI2 extending them. Another two sets were published by AMD: ABM (
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1825:
1619:
1689:
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2000:
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1561:
2148:
1957:
1868:
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copies selected bits from the source to contiguous low-order bits of the destination; higher-order destination bits are cleared.
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2624:
1494:
1390:
863:
The instructions are available in 32-bit and 64-bit versions. An example using arbitrary source and selector in 32-bit mode is:
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92:
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1888:
1802:"Saving Private Ryzen: PEXT/PDEP 32/64b replacement functions for #AMD CPUs (BR/#Zen/Zen+/#Zen2) based on @zwegner's zp7"
942:
line of processors; later AMD Jaguar and Zen-based processors do not support TBM. No Intel processors (at least through
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2531:
2398:
1993:
41:
2486:
1321:
1205:
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257:
72:
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249:
1845:
71:
There are two sets published by Intel: BMI (now referred to as BMI1) and BMI2; they were both introduced with the
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1713:"A New Basis for Shifters in General-Purpose Processors for Existing and Advanced Bit Manipulations"
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as part of BMI1, both Intel and AMD advertise the presence of these two instructions individually.
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65:
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1973:
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instructions (like the rest of the BMI instruction sets) operate on general-purpose registers.
107:
AMD was the first to introduce the instructions that now form Intel's BMI1 as part of its ABM (
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2408:
1953:
1366:
1173:
49:
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57:
1591:"How to detect New Instruction support in the 4th generation Intel® Core™ processor family"
1484:"AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and System Instructions"
2609:
2516:
2337:
1417:"AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions"
17:
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2143:
1946:
186:
169:
45:
1483:
1416:
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2362:
2158:
2138:
2133:
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1183:
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processors and newer (ABM, BMI1, BMI2 and TBM supported; microcoded PEXT and PDEP)
1297:
processors and newer (ABM, BMI1 and BMI2 supported; full hardware implementation)
2908:
2372:
1315:
729:
Unsigned multiply without affecting flags, and arbitrary destination registers
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209:
results is argument bit width minus 1 (for example, if 32-bit argument is
2322:
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2168:
2163:
142:
combined with BMI1 and BMI2 completes the expanded ABM instruction set).
1869:"AMD Zen 3 Ryzen Deep Dive Review: 5950X, 5900X, 5800X and 5600X Tested"
1642:
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56:. The purpose of these instruction sets is to improve the speed of
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processors (ABM, BMI1 and BMI2 supported; microcoded PEXT and PDEP)
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2713:
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95:-based processors as an extension to BMI1, but dropped again in
84:
80:
61:
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1982:
2734:
2009:
1536:
1490:
38:
1686:"AMD Excavator Core May Bring Dramatic Performance Increases"
1778:"Software Optimization Guide for AMD Family 19h Processors"
1889:"Dolphin Progress Report: December 2019 and January 2020"
1680:
1678:
1445:"Intel Advanced Vector Extensions Programming Reference"
1385:
1383:
714:
Zero high bits starting with specified bit position ;
1846:"BIOS and Kernel Developer's Guide for AMD Family 14h"
1722:. IEEE Transactions on Computers. pp. 1035–1048
1369:(also used for advanced bit manipulation techniques)
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2619:
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2017:
848:what these instructions do is similar to bit level
130:flag of the same name, and Intel and AMD use AMD's
1411:
1409:
980:(src >> start) & ((1 << len) - 1)
314:(src >> start) & ((1 << len) - 1)
1555:
1553:
671:is such that if BMI1 is not supported, then the
232:The instructions below are those enabled by the
1562:"New "Bulldozer" and "Piledriver" instructions"
1391:"New "Bulldozer" and "Piledriver" Instructions"
789:Shift arithmetic right without affecting flags
248:CPUID feature flag. BMI1 is available in AMD's
220:is such that if ABM is not supported, then the
2857:(ABM: 2007, BMI1: 2012, BMI2: 2013, TBM: 2012)
1688:. X-bit labs. October 18, 2013. Archived from
2594:
2287:
1994:
1741:"Zen 3 - Microarchitectures - AMD - WikiChip"
1711:Yedidya Hilewitz; Ruby B. Lee (August 2009).
1584:
1582:
1520:
1518:
1516:
1514:
1246:processors and newer (ABM and BMI1 supported)
1240:processors and newer (ABM and BMI1 supported)
774:Rotate right logical without affecting flags
648:is almost identical to the Bit Scan Forward (
60:. All the instructions in these sets are non-
8:
1478:
1476:
1474:
1472:
804:Shift logical right without affecting flags
819:Shift logical left without affecting flags
2601:
2587:
2579:
2440:Advanced Programmable Interrupt Controller
2404:Intel Communication Streaming Architecture
2294:
2280:
2272:
2057:
2001:
1987:
1979:
1643:"sandpile.org -- x86 architecture -- bits"
1637:
1635:
1439:
1437:
1435:
27:X86 instruction set architecture extension
2482:High-bandwidth Digital Content Protection
679:BMI2 (Bit Manipulation Instruction Set 2)
236:bit in CPUID. Intel officially considers
228:BMI1 (Bit Manipulation Instruction Set 1)
1269:processors (ABM, BMI1 and TBM supported)
1263:processors (ABM, BMI1 and TBM supported)
1036:Isolate lowest clear bit and complement
948:
865:
689:
262:
144:
2917:(2008); ARMv8 also has AES instructions
1379:
390:Count the number of trailing zero bits
2527:Platform Environment Control Interface
1116:Isolate lowest set bit and complement
256:and newer processors, and in Intel's
213:, LZCNT gives 12, and BSR gives 19).
7:
1526:"Family 16h AMD A-Series Data Sheet"
197:is related to the Bit Scan Reverse (
64:and operate only on general-purpose
976:Bit field extract (with immediate)
2512:Host Embedded Controller Interface
310:Bit field extract (with register)
31:Bit manipulation instructions sets
25:
675:instruction is executed instead.
224:instruction is executed instead.
3017:Suspended extensions' dates are
1915:Wegner, Zach (4 November 2020).
1314:
1212:) (ABM, BMI1 and BMI2 supported)
1136:Inverse mask from trailing ones
826:Parallel bit deposit and extract
330:Extract lowest set isolated bit
83:implemented by Intel as part of
1663:"Abseil - C++ Common Libraries"
1500:from the original on 2021-04-08
933:TBM (Trailing Bit Manipulation)
240:as part of BMI, but advertises
103:ABM (Advanced Bit Manipulation)
91:, an extension introduced with
350:Get mask up to lowest set bit
1:
1939:Warren Jr., Henry S. (2013).
1567:. Advanced Micro Devices, Inc
1251:"Heavy Equipment" processors
1197:processors (POPCNT supported)
2470:Active Management Technology
2399:MultiProcessor Specification
79:, which is also a subset of
42:instruction set architecture
1322:Computer programming portal
1228:"Cat" low-power processors
1204:processors and newer (like
1182:processors and newer (like
1056:Mask from lowest clear bit
996:Fill from lowest clear bit
3060:
1826:"tbmintrin.h from GCC 4.8"
1620:"bmiintrin.h from GCC 4.8"
1331:Advanced Vector Extensions
1257:processors (ABM supported)
1234:processors (ABM supported)
1225:processors (ABM supported)
3015:
1156:Mask from trailing zeros
1096:Fill from lowest set bit
1016:Isolate lowest clear bit
109:Advanced Bit Manipulation
89:Trailing Bit Manipulation
77:Advanced Bit Manipulation
18:Advanced Bit Manipulation
2814:(FMA4: 2011, FMA3: 2012)
2507:Serial Digital Video Out
2497:Rapid Storage Technology
961:Equivalent C expression
687:architecture and newer.
393:
275:Equivalent C expression
37:) are extensions to the
2872:Compressed instructions
2552:Ultra Path Interconnect
2537:Platform Controller Hub
2465:Intel Management Engine
1951:Pearson Education, Inc.
765:VEX.LZ.F2.0F3A F0 /r ib
2568:Silicon Photonics Link
2532:QuickPath Interconnect
1974:Intel Intrinsics Guide
1560:Hollingsworth, Brent.
759:Parallel bits extract
744:Parallel bits deposit
260:and newer processors.
118:as part of SSE4.2 and
114:While Intel considers
2542:System Management Bus
2487:High Definition Audio
2394:Common Building Block
2124:High Bandwidth Memory
1782:AMD Developer Central
1342:CLMUL instruction set
1076:Set lowest clear bit
370:Reset lowest set bit
2962:Transactional memory
1755:"Instruction tables"
1190:) (POPCNT supported)
810:VEX.LZ.66.0F38 F7 /r
795:VEX.LZ.F2.0F38 F7 /r
780:VEX.LZ.F3.0F38 F7 /r
750:VEX.LZ.F3.0F38 F5 /r
735:VEX.LZ.F2.0F38 F5 /r
720:VEX.LZ.F2.0F38 F6 /r
99:-based processors).
87:and BMI1), and TBM (
1720:palms.princeton.edu
1692:on October 23, 2013
1362:XOP instruction set
1352:FMA instruction set
1337:AES instruction set
852:SIMD instructions,
187:Leading zeros count
1671:. 4 November 2021.
1589:Locktyukhin, Max.
967:XOP.LZ.0A 10 /r id
667:, the encoding of
244:support using the
3026:
3025:
2576:
2575:
2450:Intel Turbo Boost
2409:Intel Inboard 386
2269:
2268:
2107:
2106:
1959:978-0-321-84268-8
1897:. 7 February 2020
1489:. Revision 3.32.
1367:Intel BCD opcodes
1267:Steamroller-based
1165:
1164:
1140:~x | (x + 1)
1120:~x | (x - 1)
1020:x | ~(x + 1)
926:
925:
823:
822:
705:VEX.LZ.0F38 F5 /r
643:
642:
361:VEX.LZ.0F38 F3 /1
341:VEX.LZ.0F38 F3 /2
321:VEX.LZ.0F38 F3 /3
301:VEX.LZ.0F38 F7 /r
281:VEX.LZ.0F38 F2 /r
192:
191:
134:flag to indicate
16:(Redirected from
3051:
3044:AMD technologies
3039:X86 instructions
2847:Bit manipulation
2603:
2596:
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2492:Hub Architecture
2460:Intel Secure Key
2296:
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2058:
2003:
1996:
1989:
1980:
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1942:Hacker's Delight
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1894:Dolphin Emulator
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1387:
1324:
1319:
1318:
1261:Piledriver-based
1161:
1160:~x & (x - 1)
1153:
1148:
1141:
1133:
1128:
1121:
1113:
1108:
1101:
1100:x | (x - 1)
1093:
1088:
1081:
1080:x | (x + 1)
1073:
1068:
1061:
1053:
1048:
1041:
1040:~x & (x + 1)
1033:
1028:
1021:
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290:Logical and not
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216:The encoding of
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170:Population count
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125:
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58:bit manipulation
21:
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2610:Instruction set
2607:
2577:
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2517:Hyper-threading
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2265:
2175:
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2035:Radeon Software
2013:
2007:
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1933:Further reading
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1273:Excavator-based
1255:Bulldozer-based
1170:
1168:Supporting CPUs
1159:
1151:
1147:XOP.LZ.09 01 /4
1146:
1139:
1131:
1127:XOP.LZ.09 01 /7
1126:
1119:
1111:
1107:XOP.LZ.09 01 /6
1106:
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1087:XOP.LZ.09 01 /2
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1067:XOP.LZ.09 01 /3
1066:
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1047:XOP.LZ.09 02 /1
1046:
1039:
1031:
1027:XOP.LZ.09 01 /5
1026:
1019:
1011:
1007:XOP.LZ.09 02 /6
1006:
1000:x & (x + 1)
999:
991:
987:XOP.LZ.09 01 /1
986:
979:
971:
966:
946:) support TBM.
935:
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374:x & (x - 1)
373:
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46:microprocessors
28:
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22:
15:
12:
11:
5:
3057:
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3019:struck through
3016:
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2986:Virtualization
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1968:External links
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1947:Addison Wesley
1945:(2 ed.).
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1539:. October 2013
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1493:. March 2021.
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2899:Security and
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1917:"zwegner/zp7"
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1596:
1595:www.intel.com
1592:
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1199:
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1038:
1035:
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1024:
1018:
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1005:
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998:
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985:
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975:
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965:
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947:
945:
941:
932:
930:
919:
914:
909:
904:
903:
897:
892:
887:
882:
881:
877:
874:
872:Selector mask
871:
868:
867:
864:
861:
851:
825:
818:
813:
808:
807:
803:
798:
793:
792:
788:
783:
778:
777:
773:
768:
763:
762:
758:
753:
748:
747:
743:
738:
733:
732:
728:
723:
718:
717:
713:
708:
703:
702:
698:
695:
692:
691:
688:
686:
678:
676:
661:
392:
389:
384:
379:
378:
372:
369:
364:
359:
358:
352:
349:
344:
339:
338:
332:
329:
324:
319:
318:
312:
309:
304:
299:
298:
292:
289:
284:
279:
278:
274:
271:
268:
265:
264:
261:
259:
255:
251:
227:
225:
214:
188:
185:
180:
175:
174:
171:
168:
163:
158:
157:
153:
150:
147:
146:
143:
129:
112:
110:
102:
100:
98:
94:
90:
86:
82:
78:
74:
69:
67:
63:
59:
55:
51:
47:
43:
40:
36:
32:
19:
3018:
2901:cryptography
2788:
2475:AMT versions
2387:Discontinued
2180:Instructions
2119:Cool'n'Quiet
1940:
1920:
1910:
1899:. Retrieved
1892:
1883:
1872:. Retrieved
1863:
1852:. Retrieved
1840:
1829:. Retrieved
1820:
1809:. Retrieved
1805:
1796:
1785:. Retrieved
1781:
1772:
1761:. Retrieved
1749:
1735:
1724:. Retrieved
1719:
1706:
1696:November 24,
1694:. Retrieved
1690:the original
1666:
1657:
1646:. Retrieved
1623:. Retrieved
1614:
1602:. Retrieved
1594:
1569:. Retrieved
1541:. Retrieved
1532:
1502:. Retrieved
1460:. Retrieved
1451:
1423:. Retrieved
1397:. Retrieved
1302:
1238:Jaguar-based
1232:Bobcat-based
1184:Sandy Bridge
958:Description
955:Instruction
936:
927:
878:Destination
862:
829:
699:Description
696:Instruction
682:
662:
644:
272:Description
269:Instruction
231:
215:
193:
154:Description
151:Instruction
113:
108:
106:
88:
76:
70:
34:
30:
29:
2885:MIPS16e ASE
2547:Thunderbolt
1604:11 December
1571:11 December
1458:. June 2011
1289:Zen 2-based
1060:x ^ (x + 1)
869:Instruction
381:F3 0F BC /r
354:x ^ (x - 1)
177:F3 0F BD /r
160:F3 0F B8 /r
3033:Categories
2613:extensions
2414:Intel Play
2353:Skulltrail
2323:Centrino 2
2305:technology
2207:CVT16/F16C
2154:AMD Wraith
2144:Turbo Core
2112:Technology
2045:Xilinx ISE
2012:technology
1901:2020-02-07
1874:2021-12-26
1854:2014-01-03
1831:2014-03-17
1811:2022-02-21
1787:2022-07-22
1763:2023-09-09
1726:2014-02-10
1648:2014-03-17
1625:2014-03-17
1543:2014-01-02
1504:2021-04-08
1462:2014-01-03
1425:2022-07-20
1399:2014-01-03
1375:References
1285:Zen+-based
1244:Puma-based
1195:Silvermont
1188:Ivy Bridge
944:Alder Lake
940:Piledriver
921:0x12005670
916:0x00012567
911:0xff00fff0
899:0x00012567
894:0x12345678
889:0xff00fff0
660:is equal.
618:0x55555555
573:0x33333333
528:0x0F0F0F0F
483:0x00FF00FF
438:0x0000FFFF
334:x & -x
294:~x & y
254:Piledriver
211:0x000f0000
93:Piledriver
2702:Power ISA
2683:MIPS SIMD
2522:Omni-Path
2502:SpeedStep
2348:Ultrabook
2311:Platforms
2139:PowerTune
2134:PowerPlay
2129:PowerNow!
2054:Platforms
1452:intel.com
1357:Intel ADX
1281:Zen-based
1223:K10-based
1210:Broadwell
952:Encoding
693:Encoding
685:Excavator
266:Encoding
148:Encoding
66:registers
3008:(AMD-Vi)
2561:Upcoming
2318:Centrino
2169:Ryzen AI
2082:Obsolete
2018:Software
1495:Archived
1308:See also
663:As with
35:BMI sets
2909:PadLock
2824:AVX-512
2690:PA-RISC
2673:MIPS-3D
2433:Current
2363:Galileo
2073:GPUOpen
2061:Current
1806:Twitter
1533:amd.com
1206:Skylake
1202:Haswell
1180:Nehalem
1092:BLSFILL
992:BLCFILL
258:Haswell
73:Haswell
3002:(2006)
2996:(2005)
2972:(2013)
2953:(2021)
2947:(2015)
2941:(2015)
2935:(2013)
2929:(2012)
2927:RDRAND
2923:(2010)
2915:AES-NI
2911:(2003)
2863:(2014)
2838:(2023)
2832:(2022)
2826:(2015)
2820:(2013)
2808:(2009)
2802:(2009)
2796:(2008)
2789:(2007)
2782:(2006)
2776:(2006)
2770:(2004)
2764:(2001)
2758:(1999)
2752:(1998)
2750:3DNow!
2746:(1996)
2368:Edison
2338:Tablet
2192:3DNow!
2187:X86-64
2159:Virtex
2094:Dragon
2089:Spider
2040:Vivado
2030:AMDGPU
1956:
1922:GitHub
1668:GitHub
1287:, and
1200:Intel
1193:Intel
1178:Intel
1132:T1MSKC
1052:BLCMSK
875:Source
346:BLSMSK
250:Jaguar
165:POPCNT
124:POPCNT
116:POPCNT
85:SSE4.2
3000:AMD-V
2921:CLMUL
2880:Thumb
2836:AVX10
2774:SSSE3
2714:SPARC
2634:Alpha
2424:MMC-2
2419:MMC-1
2373:Curie
2303:Intel
2099:Horus
2025:AGESA
1849:(PDF)
1758:(PDF)
1716:(PDF)
1599:Intel
1565:(PDF)
1529:(PDF)
1498:(PDF)
1487:(PDF)
1456:Intel
1448:(PDF)
1420:(PDF)
1394:(PDF)
1333:(AVX)
1295:Zen 3
1174:Intel
1152:TZMSK
1112:BLSIC
1032:BLCIC
972:BEXTR
669:TZCNT
665:LZCNT
654:TZCNT
646:TZCNT
615:&
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386:TZCNT
306:BEXTR
242:LZCNT
238:LZCNT
218:LZCNT
203:LZCNT
195:LZCNT
182:LZCNT
140:LZCNT
136:LZCNT
128:CPUID
120:LZCNT
81:SSE4a
50:Intel
48:from
3006:VT-d
2994:VT-x
2818:AVX2
2800:F16C
2786:SSE5
2780:SSE4
2768:SSE3
2762:SSE2
2731:SIMD
2668:MDMX
2663:MIPS
2651:NEON
2625:RISC
2621:SIMD
2455:vPro
2445:CNVi
2343:CULV
2328:Viiv
2251:SSE5
2239:BMI1
2222:FMA3
2217:FMA4
2164:XDNA
2149:ASTC
2068:ROCm
1954:ISBN
1698:2013
1606:2014
1573:2014
1347:F16C
1072:BLCS
1012:BLCI
906:PDEP
884:PEXT
858:PEXT
856:and
854:PDEP
845:PDEP
841:PEXT
836:PEXT
834:and
832:PDEP
830:The
815:SHLX
800:SHRX
785:SARX
770:RORX
755:PEXT
740:PDEP
725:MULX
710:BZHI
656:and
366:BLSR
326:BLSI
286:ANDN
205:and
62:SIMD
52:and
44:for
2976:ASF
2970:TSX
2951:TDX
2945:SGX
2939:MPX
2933:SHA
2890:RVC
2861:ADX
2855:BMI
2830:AMX
2812:FMA
2806:XOP
2794:AVX
2756:SSE
2744:MMX
2735:x86
2719:VIS
2707:VMX
2695:MAX
2678:MXU
2656:SVE
2646:ARM
2639:MVI
2378:Evo
2358:NUC
2333:MID
2261:AES
2256:ASF
2244:TBM
2234:ABM
2229:BMI
2212:FMA
2202:XOP
2197:AVX
2010:AMD
1537:AMD
1491:AMD
1218:AMD
673:BSF
658:BSF
650:BSF
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552:(((
507:(((
462:(((
417:(((
246:ABM
234:BMI
222:BSR
207:BSR
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