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The following 68 pages are in this category, out of 68 total.
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General-purpose computing on graphics processing units
191:Application-specific instruction set processor
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16:This category contains articles related to
163:Pages in category "Instruction processing"
298:Explicitly parallel instruction computing
168:This list may not reflect recent changes
423:Multithreading (computer architecture)
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235:Burroughs B6x00-7x00 instruction set
147:Very long instruction word computing
489:Predication (computer architecture)
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413:Minimal instruction set computer
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351:Instruction-level parallelism
560:Instruction set architecture
435:No instruction set computing
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575:Speculative multithreading
452:Orthogonal instruction set
587:Tomasulo's algorithm
213:Branch (computer science)
383:Memory-level parallelism
418:Model-specific register
366:Interlock (engineering)
230:Branch target predictor
181:Address generation unit
469:Instruction pipelining
457:Out-of-order execution
361:Instructions per cycle
270:Decoupled architecture
257:Cycles per instruction
671:Computer architecture
570:Speculative execution
479:Classic RISC pipeline
276:Degree of parallelism
252:Cycle time (software)
114:Speculative execution
501:Prefetch input queue
495:Instruction prefetch
474:Pipeline (computing)
219:Branch misprediction
533:Reservation station
293:Execute instruction
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101:(1 C, 43 P)
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665:Categories
638:Wide-issue
281:Delay slot
118:(1 C, 4 P)
21:processing
408:Millicode
398:Microcode
543:Runahead
609:Unicore
151:(39 P)
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53:GPGPU
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