1366:, was an important characteristic of any instruction set. It remained important on the initially-tiny memories of minicomputers and then microprocessors. Density remains important today, for smartphone applications, applications downloaded into browsers over slow Internet connections, and in ROMs for embedded applications. A more general advantage of increased density is improved effectiveness of caches and instruction prefetch.
1392:, were first widely implemented during a period of rapidly growing memory subsystems. They sacrifice code density to simplify implementation circuitry, and try to increase performance via higher clock frequencies and more registers. A single RISC instruction typically performs only a single operation, such as an "add" of registers or a "load" from a memory location into a register. A RISC instruction set normally has a fixed
252:(ABI) for a particular ISA, machine code will run on future implementations of that ISA and operating system. However, if an ISA supports running multiple operating systems, it does not guarantee that machine code for one operating system will run on another operating system, unless the first operating system supports running machine code built for the other operating system.
1666:. Naturally, due to the interpretation overhead, this is slower than directly running programs on the emulated hardware, unless the hardware running the emulator is an order of magnitude faster. Today, it is common practice for vendors of new ISAs or microarchitectures to make software emulators available to software developers before the hardware implementation is ready.
809:
875:
part of the program, and not transfer control if the condition is false, so that execution continues sequentially. Some instruction sets also have conditional moves, so that the move will be executed, and the data stored in the target location, if the condition is true, and not executed, and the target location not modified, if the condition is false. Similarly, IBM
2325:
1485:
could be eliminated. The result was the RISC (Reduced
Instruction Set Computer), an architecture that uses a smaller set of instructions. A simpler instruction set may offer the potential for higher speeds, reduced processor size, and reduced power consumption. However, a more complex set may optimize common operations, improve memory and
1484:
The design of instruction sets is a complex issue. There were two stages in history for the microprocessor. The first was the CISC (Complex
Instruction Set Computer), which had many different instructions. In the 1970s, however, places like IBM did research and found that many instructions in the set
1245:
or in an implicit register. If some of the operands are given implicitly, fewer operands need be specified in the instruction. When a "destination operand" explicitly specifies the destination, an additional operand must be supplied. Consequently, the number of operands encoded in an instruction may
874:
Conditional instructions often have a predicate field—a few bits that encode the specific condition to cause an operation to be performed rather than not performed. For example, a conditional branch instruction will transfer control if the condition is true, so that execution proceeds to a different
319:
Prior to NPL , the company's computer designers had been free to honor cost objectives not only by selecting technologies but also by fashioning functional and architectural refinements. The SPREAD compatibility objective, in contrast, postulated a single architecture for a series of five processors
863:" instruction sets in which arithmetic and logical operations lack any operand specifier fields; only instructions that push operands onto the evaluation stack or that pop operands from the stack into variables have operand specifiers. The instruction set carries out most ALU actions with postfix (
237:, physical size, and monetary cost (among other things), but that are capable of running the same machine code, so that a lower-performance, lower-cost machine can be replaced with a higher-cost, higher-performance machine without having to replace software. It also enables the evolution of the
1281:
enjoy low register pressure. CISC ISAs like x86-64 offer low register pressure despite having smaller register sets. This is due to the many addressing modes and optimizations (such as sub-register addressing, memory operands in ALU instructions, absolute addressing, PC-relative addressing, and
1381:
such as direct, indirect, indexed, etc.). Certain architectures may allow two or three operands (including the result) directly in memory or may be able to perform functions such as automatic pointer increment, etc. Software-implemented instruction sets may have even more complex and powerful
772:
Complex instructions are more common in CISC instruction sets than in RISC instruction sets, but RISC instruction sets may include them as well. RISC instruction sets generally do not include ALU operations with memory operands, or instructions to move large blocks of memory, but most RISC
812:
One instruction may have several fields, which identify the logical operation, and may also include source and destination addresses and constant values. This is the MIPS "Add
Immediate" instruction, which allows selection of source and destination registers and inclusion of a small
1352:
Fixed-length instructions are less complicated to handle than variable-length instructions for several reasons (not having to check whether an instruction straddles a cache line or virtual memory page boundary, for instance), and are therefore somewhat easier to optimize for speed.
380:(RISC) simplifies the processor by efficiently implementing only the instructions that are frequently used in programs, while the less common operations are implemented as subroutines, having their resulting additional processor execution time offset by infrequent use.
1396:, whereas a typical CISC instruction set has instructions of widely varying length. However, as RISC computers normally require more and often longer instructions to implement a given task, they inherently make less optimal use of bus bandwidth and cache memories.
1361:
In early 1960s computers, main memory was expensive and very limited, even on mainframes. Minimizing the size of a program to make sure it would fit in the limited memory was often central. Thus the size of the instructions needed to perform a particular task, the
1261:
measures the availability of free registers at any point in time during the program execution. Register pressure is high when a large number of the available registers are in use; thus, the higher the register pressure, the more often the register contents must be
320:
spanning a wide range of cost and performance. None of the five engineering design teams could count on being able to bring about adjustments in architectural specifications as a way of easing difficulties in achieving cost and performance objectives.
510:; however, the term is misleading). They are used to store the contents of a register, the contents of another memory location or the result of a computation, or to retrieve stored data to perform a computation on it later. They are often called
684:
by instructions that take multiple steps, control multiple functional units, or otherwise appear on a larger scale than the bulk of simple instructions implemented by the given processor. Some examples of "complex" instructions include:
1688:
The demands of high-speed digital signal processing have pushed in the opposite direction—forcing instructions to be implemented in a particular way. For example, to perform digital filters fast enough, the MAC instruction in a typical
1310:
have minimum instruction sizes between 8 and 64 bits. The longest possible instruction on x86 is 15 bytes (120 bits). Within an instruction set, different instructions may have different lengths. In some architectures, notably most
1407:
typically exhibit very high density owing to a technique called code compression. This technique packs two 16-bit instructions into one 32-bit word, which is then unpacked at the decode stage and executed as two instructions.
781:
instructions that perform the same arithmetic operation on multiple pieces of data at the same time. SIMD instructions have the ability of manipulating large vectors and matrices in minimal time. SIMD instructions allow easy
1587:, and all implementations of that instruction set are able to run the same executables. The various ways of implementing an instruction set give different tradeoffs between cost, performance, power consumption, size, etc.
1418:, where there are few separate instructions (8–32), so that multiple instructions can be fit into a single machine word. These types of cores often take little silicon to implement, so they can be easily realized in an
871:, not on data registers or arbitrary main memory cells. This can be very convenient for compiling high-level languages, because most arithmetic expressions can be easily translated into postfix notation.
1205:
Due to the large number of bits needed to encode the three registers of a 3-operand instruction, RISC architectures that have 16-bit instructions are invariably 2-operand designs, such as the Atmel AVR,
348:, implement this by translating the bytecode for commonly used code paths into native machine code. In addition, these virtual machines execute less frequently used code paths by interpretation (see:
255:
An ISA can be extended by adding instructions or other capabilities, or adding support for larger addresses and data values; an implementation of the extended ISA will still be able to execute
1349:
variable encoding, that is two fixed, usually 32-bit and 16-bit encodings, where instructions cannot be mixed freely but must be switched between on a branch (or exception boundary in ARMv8).
680:
Processors may include "complex" instructions in their instruction set. A single "complex" instruction does something that may take many instructions on other computers. Such instructions are
955:. For stack machines, the terms "0-operand" and "zero-address" apply to arithmetic instructions, but not to all instructions, as 1-operand push and pop instructions are used to access memory.
3395:
1594:
of a processor, engineers use blocks of "hard-wired" electronic circuitry (often designed separately) such as adders, multiplexers, counters, registers, ALUs, etc. Some kind of
1426:
form. The code density of MISC is similar to the code density of RISC; the increased instruction density is offset by requiring more of the primitive instructions to do a task.
282:
techniques used, in a particular processor, to implement the instruction set. Processors with different microarchitectures can share a common instruction set. For example, the
1669:
Often the details of the implementation have a strong influence on the particular instructions selected for the instruction set. For example, many implementations of the
1377:). However, more typical, or frequent, "CISC" instructions merely combine a basic ALU operation, such as "add", with the access of one or more operands in memory (using
241:
of the implementations of that ISA, so that a newer, higher-performance implementation of an ISA can run software that runs on previous generations of implementations.
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1598:
is then often used to describe the decoding and sequencing of each instruction of an ISA using this physical microarchitecture. There are two basic ways to build a
3506:
2689:
1528:
3208:
3365:
2931:
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1713:
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of algorithms commonly involved in sound, image, and video processing. Various SIMD implementations have been brought to market under trade names such as
1843:
1369:
Computers with high code density often have complex instructions for procedure entry, parameterized returns, loops, etc. (therefore retroactively named
259:
for versions of the ISA without those extensions. Machine code using those extensions will only run on implementations that support those extensions.
2711:
1042:
396:
3360:
3432:
1197:
more operands—some CISC machines permit a variety of addressing modes that allow more than 3 operands (registers or memory accesses), such as the
1250:). Operands are either encoded in the "opcode" representation of the instruction, or else are given as values or addresses following the opcode.
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3185:
2329:
140:
2085:
1946:
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3253:
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More complex operations are built up by combining these simple instructions, which are executed sequentially, or as otherwise directed by
4139:
3280:
1583:
A given instruction set can be implemented in a variety of ways. All ways of implementing a particular instruction set provide the same
1452:
has the option -Os to optimize for small machine code size, and -O3 to optimize for execution speed at the cost of larger machine code.
2407:
3447:
3275:
3248:
2627:
2301:
1826:
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Some computer designs "hardwire" the complete instruction set decoding and sequencing (just like the rest of the microarchitecture).
774:
737:
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1938:
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running on implementations of that ISA in a fashion that does not depend on the characteristics of that implementation, providing
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Some microcoded CPU designs with a writable control store use it to allow the instruction set to be changed (for example, the
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2417:
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used in immunity-aware programming is much easier to implement if the "unprogrammed" state of the memory is interpreted as a
972:: most instructions specify a single right operand (that is, constant, a register, or a memory location), with the implicit
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has a conditional store instruction. A few instruction sets include a predicate field in every instruction; this is called
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3119:
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into memory. Increasing the number of registers in an architecture decreases register pressure but increases the cost.
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have options that control whether to optimize code generation for execution speed or for code density. For instance
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data from a memory location or a register to a memory location or a register (a machine instruction is often called
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suffer from extremely high register pressure because they have small register sets, general-purpose RISC ISAs like
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384:
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or program that executes instructions described by that ISA, such as a central processing unit (CPU), is called an
133:
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4205:
4195:
2583:
1733:
1190:
Unlike 2-operand or 1-operand, this leaves all three values a, b, and c in registers available for further reuse.
860:
708:
630:
97:
1873:
Schlansker, Michael S.; Rau, B. Ramakrishna (February 2000). "EPIC: Explicitly
Parallel Instruction Computing".
233:
between implementations. This enables multiple implementations of an ISA that differ in characteristics such as
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3427:
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3170:
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1690:
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full systems simulator providing ability to create/model/emulate any instruction set using C and standard APIs
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1161:
RISC — arithmetic instructions use registers only, so explicit 2-operand load/store instructions are needed:
745:, a single instruction performing an operation on many homogeneous values in parallel, possibly in dedicated
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3993:
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174:
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3015:
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376:(CISC) has many specialized instructions, some of which may only be rarely used in practical programs. A
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differ from the mathematically necessary number of arguments for a logical or arithmetic operation (the
787:
765:
126:
31:
2029:
1549:
algorithms are much easier to implement if the instruction set includes support for something such as "
1237:
Each instruction specifies some number of operands (registers, memory locations, or immediate values)
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4156:
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3301:
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2402:
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337:
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An ISA may be classified in a number of different ways. A common classification is by architectural
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1501:
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The binary compatibility that they provide makes ISAs one of the most fundamental abstractions in
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The instructions constituting a program are rarely specified using their internal, numeric form (
1303:
880:
845:
architectures, multiple simultaneous opcodes and operands are specified in a single instruction.
830:
759:
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another block of code, while saving the location of the next instruction as a point to return to.
638:
497:
455:
207:
109:
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that can fetch an instruction and two data words simultaneously, and it requires a single-cycle
1241:. Some instructions give one or both operands implicitly, such as by being stored on top of the
4077:
4044:
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3793:
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1978:
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1701:
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1223:
1214:. RISC architectures that have 32-bit instructions are usually 3-operand designs, such as the
778:
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581:
275:
238:
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the values of two registers, placing the result in a register, possibly setting one or more
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245:
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154:
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325:
211:
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102:
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The size or length of an instruction varies widely, from as little as four bits in some
929:: All arithmetic operations take place using the top one or two positions on the stack:
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3000:
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2255:
1815:
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876:
511:
215:
183:
64:
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to implement this description (although many designs use middle ways or compromises):
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3005:
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1903:
1550:
1415:
1307:
926:
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1057:; This requires a load/store pair for any memory movement regardless of whether the
27:
Set of abstract symbols that describe a computer program's operations to a processor
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4215:
4031:
4008:
3820:
3541:
2479:
1599:
1527:
Fast virtual machines are much easier to implement if an instruction set meets the
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752:
701:
608:
two values in registers (for example, to see if one is less, or if they are equal).
473:
427:
419:(OISC). These are theoretically important types, but have not been commercialized.
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191:
69:
40:
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only allow a single memory load or memory store per instruction, leading to a
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1423:
690:
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312:
92:
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2826:
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2102:
1610:
1535:
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Some instruction set designers reserve one or more opcodes for some kind of
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1227:
1211:
1207:
842:
720:
353:
341:
333:
263:
195:
17:
2104:
Harnessing ISA Diversity: Design of a
Heterogeneous-ISA Chip Multiprocessor
668:
Load/store data to and from a coprocessor or exchanging with CPU registers.
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4054:
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2873:
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1728:
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1634:
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1441:
1334:
681:
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329:
170:
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808:
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2821:
1138:
CISC — Or, on machines limited to two memory operands per instruction,
826:
795:
411:
Architectures with even less complexity have been studied, such as the
76:
910:
are (direct or calculated) addresses referring to memory cells, while
891:
Instruction sets may be categorized by the maximum number of operands
4166:
2878:
2843:
2808:
1888:
1748:
833:, memory locations, or literal data. The operand specifiers may have
818:
791:
728:
442:
293:
178:
59:
2228:
1792:
1084:
RISC — Requiring explicit memory loads, the instructions would be:
438:. On the processing architecture, a given instruction may specify:
307:, distinct from the design of a specific machine, was developed by
3336:
2868:
2838:
2006:
2004:
1960:
1958:
1404:
1338:
1247:
1231:
1219:
1003:
2-operand — many CISC and RISC machines fall under this category:
848:
Some exotic instruction sets do not have an opcode field, such as
807:
689:
transferring multiple registers to or from memory (especially the
634:
to another location in the program and execute instructions there.
283:
2258:(July–August 1985). "Standard Microprocessor Programming Cards".
1677:(RISC). For another example, some early ways of implementing the
4200:
3348:
3268:
2858:
1330:
724:
484:
Examples of operations common to many instruction sets include:
357:
2349:
2119:"Intel® 64 and IA-32 Architectures Software Developer's Manual"
2107:. 41st Annual International Symposium on Computer Architecture.
1933:
Gilreath, William F.; Laplante, Phillip A. (December 6, 2012).
2788:
2778:
1618:
1433:
as a mechanism for improving code density. The mathematics of
1198:
1842:
Crystal Chen; Greg Novick; Kirk
Shimano (December 16, 2006).
1061:
result is an augmentation stored to a different place, as in
768:
operations with an operand from memory rather than a register
1813:
Pugh, Emerson W.; Johnson, Lyle R.; Palmer, John H. (1991).
1032:. This effectively 'stores' the result without an explicit
976:
as the left operand (and the destination if there is one):
2229:"Great Microprocessors of the Past and Present (V 13.4.0)"
400:(EPIC) architectures. These architectures seek to exploit
817:
On traditional architectures, an instruction includes an
596:
of corresponding bits in a pair of registers, taking the
2336:
Programming
Textfiles: Bowen's Instruction Summary Cards
837:
determining their meaning or may be in fixed fields. In
274:
An instruction set architecture is distinguished from a
445:(the instruction to be performed) e.g. add, copy, test
300:, but they have radically different internal designs.
2144:. IEEE International Conference on Computer Design.
575:
in some ISAs, saving operand fetch in trivial cases.
404:
with less hardware than RISC and CISC by making the
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4179:
4115:
4053:
4007:
3959:
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2656:
2527:
2383:
1440:In practice, code density is also dependent on the
1321:, typically corresponding with that architecture's
1282:register-to-register spills) that CISC ISAs offer.
2341:Mark Smotherman's Historical Computer Designs Page
1814:
408:responsible for instruction issue and scheduling.
2196:
2070:A Practical Introduction to Computer Architecture
2028:Cocke, John; Markstein, Victoria (January 1990).
2010:
1995:
1964:
1464:); they may be specified by programmers using an
821:that specifies the operation to perform, such as
642:to another location if a certain condition holds.
1904:"On the Classification of Computer Architecture"
1935:Computer Architecture: A Minimalist Perspective
1908:International Journal of Science and Technology
1613:routines or tables (or both) to do this, using
1120:CISC — It becomes either a single instruction:
317:
2289:Computer Architecture: A Quantitative Approach
1785:"GLOSSARY: Instruction Set Architecture (ISA)"
1529:Popek and Goldberg virtualization requirements
867:) operations that work only on the expression
387:(VLIW) architectures, and the closely related
2361:
1437:describes the challenges and limits of this.
134:
8:
2140:Weaver, Vincent M.; McKee, Sally A. (2009).
1902:Shaout, Adnan; Eldos, Taisir (Summer 2003).
1512:uses the eight codes C7,CF,D7,DF,E7,EF,F7,FF
1325:. In other architectures, instructions have
3366:Computer performance by orders of magnitude
2142:Code density concerns for new architectures
1714:Comparison of instruction set architectures
296:implement nearly identical versions of the
3831:
3471:
3092:
2950:
2664:
2368:
2354:
2346:
1117:3-operand, allowing better reuse of data:
177:in a computer or a family of computers. A
141:
127:
36:
2149:
2101:Venkat, Ashish; Tullsen, Dean M. (2014).
2030:"The evolution of RISC technology at IBM"
1468:or, more commonly, may be generated from
1201:"POLY" polynomial evaluation instruction.
968:, include early computers and many small
841:(VLIW) architectures, which include many
619:for arithmetic on floating-point numbers.
397:explicitly parallel instruction computing
356:implemented the x86 instruction set atop
190:In general, an ISA defines the supported
2023:
2021:
2019:
1269:While embedded instruction sets such as
30:For broader coverage of this topic, see
2037:IBM Journal of Research and Development
1776:
1393:
914:and so on refer to machine registers.)
84:
46:
39:
2068:Page, Daniel (2009). "11. Compilers".
1983:Introduction to Computer Science CS 0
1545:On systems with multiple processors,
1489:efficiency, or simplify programming.
222:model of implementations of the ISA.
7:
3337:Floating-point operations per second
1979:"Instruction Set Architecture (ISA)"
1329:, typically integral multiples of a
696:moving large blocks of memory (e.g.
248:maintains a standard and compatible
206:, fundamental features (such as the
202:, the hardware support for managing
2209:Ganssle, Jack (February 26, 2001).
488:Data handling and memory operations
1844:"RISC Architecture: RISC vs. CISC"
823:add contents of memory to register
311:at IBM during the design phase of
25:
1520:use codes in the range A000..AFFF
1412:Minimal instruction set computers
1386:Reduced instruction-set computers
1371:Complex Instruction Set Computers
1313:reduced instruction set computers
1294:to many hundreds of bits in some
850:transport triggered architectures
225:An ISA specifies the behavior of
4263:Semiconductor device fabrication
2323:
2260:Microprocessors and Microsystems
1575:Semiconductor device fabrication
1470:high-level programming languages
1399:Certain embedded RISC ISAs like
413:minimal instruction set computer
378:reduced instruction set computer
374:complex instruction set computer
4238:History of general-purpose CPUs
2465:Nondeterministic Turing machine
1939:Springer Science+Business Media
1817:IBM's 360 and Early 370 Systems
1318:instructions are a fixed length
1065:, or the same memory location:
671:Perform coprocessor operations.
529:Arithmetic and logic operations
2418:Deterministic finite automaton
1653:field-programmable gate arrays
1565:Instruction set implementation
1414:(MISC) are commonly a form of
898:(In the examples that follow,
829:specifiers, which may specify
1:
4309:Instruction set architectures
3209:Simultaneous and heterogenous
2330:Instruction set architectures
2197:Hennessy & Patterson 2003
2011:Hennessy & Patterson 2003
1996:Hennessy & Patterson 2003
1965:Hennessy & Patterson 2003
1429:There has been research into
1043:limited to one memory operand
402:instruction-level parallelism
3893:Integrated memory controller
3875:Translation lookaside buffer
3074:Memory dependence prediction
2517:Random-access stored program
2470:Probabilistic Turing machine
2272:10.1016/0141-9331(85)90116-4
1744:No instruction set computing
1547:non-blocking synchronization
1298:systems. Processors used in
417:one-instruction set computer
360:processors in this fashion.
250:application binary interface
159:instruction set architecture
3349:Synaptic updates per second
1555:load-link/store-conditional
895:specified in instructions.
524:data from hardware devices.
169:that generally defines how
4330:
3753:Heterogeneous architecture
2675:Orthogonal instruction set
2445:Alternating Turing machine
2433:Quantum cellular automaton
2294:Morgan Kaufmann Publishers
1765:Register transfer language
1719:Compressed instruction set
1596:register transfer language
1568:
1041:CISC — Often machines are
839:very long instruction word
764:instructions that perform
614:Floating-point instruction
602:of each bit in a register.
500:to a fixed constant value.
430:is built up from discrete
385:very long instruction word
29:
4243:Microprocessor chronology
4206:Dynamic frequency scaling
3361:Cache performance metrics
2160:10.1109/ICCD.2009.5413117
2072:. Springer. p. 464.
1734:Instruction set simulator
1693:(DSP) must use a kind of
773:instruction sets include
709:floating-point arithmetic
4258:Hardware security module
3601:Digital signal processor
3578:Graphics processing unit
3390:Graphics processing unit
1691:digital signal processor
1649:reconfigurable computing
852:(TTA), only operand(s).
717:transcendental functions
707:complicated integer and
663:Coprocessor instructions
350:Just-in-time compilation
4299:Central processing unit
4211:Dynamic voltage scaling
3994:Memory address register
3888:Branch target predictor
3852:Address generation unit
3595:Physics processing unit
3384:Central processing unit
3343:Transactions per second
3331:Instructions per second
3254:Array processing (SIMT)
2398:Stored-program computer
1675:load–store architecture
1210:, and some versions of
865:reverse Polish notation
624:Control flow operations
460:literal/constant values
346:Common Language Runtime
4304:Instruction processing
4017:Hardwired control unit
3899:Memory management unit
3864:Memory management unit
3613:Secure cryptoprocessor
3607:Tensor Processing Unit
3589:Vision processing unit
3323:Cycles per instruction
3317:Instructions per cycle
3264:Associative processing
2955:Instruction pipelining
2377:Processor technologies
1623:writable control store
1557:" (LL/SC), or "atomic
1431:executable compression
1171:add reg1+reg2->reg3
814:
448:any explicit operands:
364:Classification of ISAs
322:
278:, which is the set of
4100:Sum-addressed decoder
3846:Arithmetic logic unit
2973:Classic RISC pipeline
2927:Epiphany architecture
2774:Motorola 68000 series
2211:"Proactive Debugging"
1724:Computer architecture
1609:Other designs employ
1435:Kolmogorov complexity
923:zero-address machines
811:
755:instruction or other
751:performing an atomic
466:used to access memory
390:long instruction word
332:as their ISA such as
32:Computer architecture
4221:Performance per watt
3799:replacement policies
3465:Package on a package
3355:Performance per watt
3259:Pipelined processing
3029:Tomasulo's algorithm
2834:Clipper architecture
2690:Application-specific
2403:Finite-state machine
2332:at Wikimedia Commons
1854:on February 21, 2015
1695:Harvard architecture
1679:instruction pipeline
1671:instruction pipeline
1446:optimizing compilers
1337:. Some, such as the
966:accumulator machines
962:one-address machines
804:Instruction encoding
676:Complex instructions
650:to another location.
639:Conditionally branch
383:Other types include
338:Java virtual machine
231:binary compatibility
4253:Digital electronics
3906:Instruction decoder
3858:Floating-point unit
3512:Soft microprocessor
3459:System in a package
3034:Reservation station
2564:Transport-triggered
2284:Patterson, David A.
2121:. Intel Corporation
2078:2009pica.book.....P
2049:10.1147/rd.341.0004
1699:multiply–accumulate
1658:An ISA can also be
1590:When designing the
1502:MOS Technology 6502
584:, e.g., taking the
298:x86 instruction set
115:Execute instruction
4125:Integrated circuit
3969:Processor register
3623:Baseband processor
2968:Operand forwarding
2428:Cellular automaton
2292:(Third ed.).
2256:Bowen, Jonathan P.
1662:in software by an
1647:CPUs designed for
1637:processor and the
1498:software interrupt
1394:instruction length
1300:personal computers
1286:Instruction length
1077:three instructions
996:three instructions
887:Number of operands
881:branch predication
825:—and zero or more
815:
760:atomic instruction
582:bitwise operations
303:The concept of an
239:microarchitectures
208:memory consistency
110:Repeat instruction
4286:
4285:
4175:
4174:
3794:Instruction cache
3784:Scratchpad memory
3631:
3630:
3618:Network processor
3547:Network on a chip
3502:Ultra-low-voltage
3453:Multi-chip module
3296:
3295:
3082:
3081:
3069:Branch prediction
3046:Register renaming
2940:
2939:
2922:VISC architecture
2744:Quantum computing
2739:VISC architecture
2621:Secondary storage
2537:Microarchitecture
2497:Register machines
2328:Media related to
2280:Hennessy, John L.
2087:978-1-84882-255-9
1948:978-1-4615-0237-1
1592:microarchitecture
1585:programming model
1466:assembly language
1259:Register pressure
1254:Register pressure
1185:four instructions
1108:four instructions
1045:per instruction:
953:four instructions
757:read-modify-write
647:Indirectly branch
480:Instruction types
276:microarchitecture
151:
150:
16:(Redirected from
4321:
4248:Processor design
4140:Power management
4022:Instruction unit
3883:Branch predictor
3832:
3530:System on a chip
3472:
3312:Transistor count
3236:Flynn's taxonomy
3093:
2951:
2754:Addressing modes
2665:
2611:Memory hierarchy
2475:Hypercomputation
2393:Abstract machine
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1889:10.1109/2.820037
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1850:. Archived from
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1833:
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1820:
1810:
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1801:
1800:
1791:. Archived from
1781:
1755:Processor design
1579:Silicon compiler
1571:Processor design
1559:compare-and-swap
1379:addressing modes
1320:
1319:
1292:microcontrollers
1182:
1176:
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1154:two instructions
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1030:two instructions
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970:microcontrollers
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835:addressing modes
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616:
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573:
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464:addressing modes
428:Machine language
393:
326:virtual machines
280:processor design
246:operating system
212:addressing modes
155:computer science
143:
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129:
47:General concepts
37:
21:
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4314:Microprocessors
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4226:
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4095:Address decoder
4049:
4003:
3999:Program counter
3974:Status register
3955:
3910:
3870:Load–store unit
3837:
3830:
3757:
3726:
3627:
3584:Image processor
3559:
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3522:
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3492:Microcontroller
3482:Embedded system
3470:
3370:
3303:
3292:
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3180:
3078:
3055:
3039:Re-order buffer
3010:
2991:Data dependency
2977:
2936:
2766:
2760:
2659:
2658:Instruction set
2652:
2638:Multiprocessing
2606:Cache hierarchy
2599:Register/memory
2523:
2423:Queue automaton
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2249:Further reading
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2180:
2178:cs.stanford.edu
2174:"RISC vs. CISC"
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2151:10.1.1.398.1967
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1739:Micro-operation
1710:
1581:
1569:Main articles:
1567:
1523:
1515:
1507:
1500:. For example,
1482:
1458:
1359:
1343:Thumb-extension
1327:variable length
1317:
1316:
1288:
1256:
1234:architectures.
1180:
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1131:one instruction
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1103:
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784:parallelization
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555:status register
551:condition codes
531:
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103:Indirect branch
55:Instruction set
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4273:Pin grid array
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4107:Barrel shifter
4104:
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4102:
4097:
4090:Binary decoder
4087:
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4019:
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3991:
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3979:Stack register
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3573:AI accelerator
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3536:Multiprocessor
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3487:Microprocessor
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1977:Durand, Paul.
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1456:Representation
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1308:supercomputers
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877:z/Architecture
857:stack machines
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10:
9:
6:
4:
3:
2:
4326:
4315:
4312:
4310:
4307:
4305:
4302:
4300:
4297:
4296:
4294:
4279:
4276:
4274:
4271:
4269:
4266:
4264:
4261:
4259:
4256:
4254:
4251:
4249:
4246:
4244:
4241:
4239:
4236:
4235:
4233:
4229:
4222:
4219:
4217:
4214:
4212:
4209:
4207:
4204:
4202:
4199:
4197:
4194:
4192:
4189:
4188:
4186:
4184:
4178:
4168:
4165:
4163:
4160:
4158:
4155:
4153:
4150:
4148:
4145:
4141:
4138:
4136:
4133:
4131:
4128:
4127:
4126:
4123:
4122:
4120:
4118:
4114:
4108:
4105:
4101:
4098:
4096:
4093:
4092:
4091:
4088:
4084:
4081:
4080:
4079:
4076:
4074:
4071:
4069:
4068:Demultiplexer
4066:
4064:
4061:
4060:
4058:
4056:
4052:
4046:
4043:
4041:
4038:
4035:
4033:
4030:
4028:
4025:
4023:
4020:
4018:
4015:
4014:
4012:
4010:
4006:
4000:
3997:
3995:
3992:
3990:
3989:Memory buffer
3987:
3985:
3984:Register file
3982:
3980:
3977:
3975:
3972:
3970:
3967:
3966:
3964:
3962:
3958:
3950:
3947:
3945:
3942:
3941:
3940:
3937:
3935:
3932:
3930:
3927:
3925:
3924:Combinational
3922:
3921:
3919:
3917:
3913:
3907:
3904:
3900:
3897:
3896:
3894:
3891:
3889:
3886:
3884:
3881:
3876:
3873:
3871:
3868:
3867:
3865:
3862:
3859:
3856:
3853:
3850:
3847:
3844:
3843:
3841:
3839:
3833:
3827:
3824:
3822:
3819:
3817:
3814:
3812:
3809:
3805:
3802:
3800:
3797:
3795:
3792:
3790:
3787:
3785:
3782:
3780:
3777:
3776:
3775:
3772:
3770:
3767:
3766:
3764:
3760:
3754:
3751:
3749:
3746:
3744:
3741:
3739:
3736:
3735:
3733:
3729:
3721:
3718:
3717:
3716:
3713:
3711:
3708:
3706:
3703:
3701:
3698:
3696:
3693:
3691:
3688:
3686:
3683:
3681:
3678:
3676:
3673:
3671:
3668:
3666:
3663:
3661:
3658:
3656:
3653:
3651:
3648:
3646:
3643:
3642:
3640:
3638:
3634:
3624:
3621:
3619:
3616:
3614:
3611:
3608:
3605:
3602:
3599:
3596:
3593:
3590:
3587:
3585:
3582:
3579:
3576:
3574:
3571:
3569:
3566:
3565:
3563:
3561:
3555:
3548:
3545:
3543:
3540:
3537:
3534:
3531:
3528:
3527:
3525:
3519:
3513:
3510:
3508:
3505:
3503:
3500:
3498:
3495:
3493:
3490:
3488:
3485:
3483:
3480:
3479:
3477:
3473:
3466:
3463:
3460:
3457:
3454:
3451:
3449:
3446:
3444:
3441:
3439:
3436:
3434:
3431:
3429:
3426:
3424:
3421:
3419:
3416:
3414:
3411:
3409:
3406:
3404:
3401:
3397:
3394:
3393:
3391:
3388:
3385:
3382:
3381:
3379:
3377:
3373:
3367:
3364:
3362:
3359:
3356:
3353:
3350:
3347:
3344:
3341:
3338:
3335:
3332:
3329:
3324:
3321:
3320:
3318:
3315:
3313:
3310:
3309:
3307:
3305:
3299:
3287:
3284:
3283:
3282:
3279:
3277:
3274:
3270:
3267:
3265:
3262:
3260:
3257:
3255:
3252:
3251:
3250:
3247:
3245:
3242:
3241:
3239:
3237:
3233:
3227:
3224:
3222:
3219:
3217:
3214:
3210:
3207:
3205:
3202:
3201:
3200:
3197:
3195:
3192:
3191:
3189:
3187:
3183:
3177:
3174:
3172:
3169:
3165:
3162:
3161:
3160:
3157:
3153:
3150:
3148:
3145:
3144:
3143:
3140:
3136:
3133:
3131:
3128:
3127:
3126:
3123:
3121:
3118:
3114:
3111:
3109:
3106:
3105:
3104:
3101:
3100:
3098:
3094:
3091:
3089:
3085:
3075:
3072:
3070:
3067:
3066:
3064:
3062:
3058:
3052:
3049:
3047:
3044:
3040:
3037:
3035:
3032:
3031:
3030:
3027:
3025:
3024:Scoreboarding
3022:
3021:
3019:
3017:
3013:
3007:
3006:False sharing
3004:
3002:
2999:
2997:
2994:
2992:
2989:
2988:
2986:
2984:
2980:
2974:
2971:
2969:
2966:
2964:
2961:
2960:
2958:
2956:
2952:
2949:
2947:
2943:
2933:
2930:
2928:
2925:
2923:
2920:
2917:
2913:
2910:
2908:
2905:
2903:
2900:
2898:
2895:
2894:
2892:
2890:
2887:
2885:
2882:
2880:
2877:
2875:
2872:
2870:
2867:
2865:
2862:
2860:
2857:
2855:
2852:
2850:
2847:
2845:
2842:
2840:
2837:
2835:
2832:
2828:
2825:
2823:
2820:
2818:
2815:
2814:
2812:
2810:
2807:
2805:
2802:
2800:
2799:Stanford MIPS
2797:
2795:
2792:
2790:
2787:
2785:
2782:
2780:
2777:
2775:
2772:
2771:
2769:
2763:
2755:
2752:
2751:
2750:
2747:
2745:
2742:
2740:
2737:
2735:
2732:
2730:
2727:
2725:
2722:
2720:
2717:
2713:
2710:
2709:
2708:
2705:
2701:
2698:
2697:
2696:
2693:
2691:
2688:
2686:
2683:
2681:
2678:
2676:
2673:
2672:
2670:
2666:
2663:
2661:
2660:architectures
2655:
2649:
2646:
2644:
2641:
2639:
2636:
2634:
2631:
2629:
2628:Heterogeneous
2626:
2622:
2619:
2617:
2614:
2613:
2612:
2609:
2607:
2604:
2600:
2597:
2595:
2592:
2590:
2587:
2585:
2582:
2581:
2580:
2579:Memory access
2577:
2575:
2572:
2570:
2567:
2565:
2562:
2560:
2557:
2553:
2550:
2549:
2548:
2545:
2543:
2540:
2538:
2535:
2534:
2532:
2530:
2526:
2518:
2515:
2513:
2512:Random-access
2510:
2508:
2505:
2503:
2500:
2499:
2498:
2495:
2493:
2492:Stack machine
2490:
2488:
2485:
2481:
2478:
2476:
2473:
2471:
2468:
2466:
2463:
2461:
2458:
2456:
2453:
2451:
2448:
2446:
2443:
2442:
2441:
2438:
2434:
2431:
2429:
2426:
2424:
2421:
2419:
2416:
2414:
2411:
2409:
2408:with datapath
2406:
2405:
2404:
2401:
2399:
2396:
2394:
2391:
2390:
2388:
2386:
2382:
2378:
2371:
2366:
2364:
2359:
2357:
2352:
2351:
2348:
2342:
2339:
2337:
2334:
2331:
2326:
2322:
2321:
2317:
2305:
2303:1-55860-724-2
2299:
2295:
2291:
2290:
2285:
2281:
2277:
2273:
2269:
2265:
2261:
2257:
2253:
2252:
2248:
2234:
2230:
2224:
2221:
2216:
2212:
2205:
2202:
2198:
2193:
2190:
2179:
2175:
2169:
2166:
2161:
2157:
2152:
2147:
2143:
2136:
2133:
2120:
2114:
2111:
2106:
2105:
2097:
2094:
2089:
2083:
2079:
2075:
2071:
2064:
2061:
2050:
2046:
2042:
2038:
2031:
2024:
2022:
2020:
2016:
2013:, p. 93.
2012:
2007:
2005:
2001:
1998:, p. 92.
1997:
1992:
1989:
1984:
1980:
1973:
1970:
1966:
1961:
1959:
1955:
1950:
1944:
1940:
1936:
1929:
1926:
1913:
1909:
1905:
1898:
1895:
1890:
1886:
1882:
1878:
1877:
1869:
1866:
1853:
1849:
1845:
1838:
1835:
1830:
1828:0-262-16123-0
1824:
1821:. MIT Press.
1819:
1818:
1809:
1806:
1795:on 2023-11-11
1794:
1790:
1786:
1780:
1777:
1771:
1766:
1763:
1761:
1758:
1756:
1753:
1750:
1747:
1745:
1742:
1740:
1737:
1735:
1732:
1730:
1727:
1725:
1722:
1720:
1717:
1715:
1712:
1711:
1707:
1705:
1703:
1700:
1696:
1692:
1686:
1684:
1680:
1676:
1672:
1667:
1665:
1661:
1656:
1654:
1650:
1645:
1643:
1640:
1636:
1628:
1624:
1620:
1616:
1612:
1608:
1605:
1604:
1603:
1601:
1597:
1593:
1588:
1586:
1580:
1576:
1572:
1564:
1562:
1560:
1556:
1552:
1551:fetch-and-add
1548:
1543:
1541:
1537:
1532:
1530:
1525:
1519:
1511:
1503:
1499:
1495:
1490:
1488:
1479:
1477:
1475:
1471:
1467:
1463:
1455:
1453:
1451:
1447:
1443:
1438:
1436:
1432:
1427:
1425:
1421:
1417:
1416:stack machine
1413:
1409:
1406:
1402:
1397:
1395:
1391:
1387:
1383:
1380:
1376:
1372:
1367:
1365:
1356:
1354:
1350:
1348:
1344:
1340:
1336:
1332:
1328:
1324:
1314:
1309:
1305:
1301:
1297:
1293:
1285:
1283:
1280:
1276:
1272:
1267:
1265:
1260:
1253:
1251:
1249:
1244:
1240:
1235:
1233:
1229:
1225:
1221:
1217:
1213:
1209:
1200:
1196:
1189:
1186:
1179:
1178:
1160:
1155:
1148:
1147:
1137:
1132:
1125:
1124:
1119:
1118:
1116:
1109:
1102:
1101:
1094:add reg1,reg2
1083:
1078:
1071:
1070:
1044:
1040:
1035:
1031:
1024:
1023:
1021:
1013:
1005:
1004:
1002:
997:
990:
989:
975:
971:
967:
964:), so called
963:
959:
954:
947:
946:
928:
925:), so called
924:
920:
919:
915:
913:
909:
905:
901:
896:
894:
886:
884:
882:
878:
872:
870:
866:
862:
858:
853:
851:
846:
844:
840:
836:
832:
828:
824:
820:
810:
803:
801:
799:
797:
793:
789:
785:
780:
776:
767:
763:
761:
758:
754:
750:
748:
744:
739:
733:
730:
726:
722:
718:
714:
710:
706:
703:
699:
695:
692:
688:
687:
686:
683:
675:
670:
667:
666:
662:
657:
656:
652:
649:
648:
644:
641:
640:
636:
633:
632:
628:
627:
623:
618:
610:
607:
604:
601:
600:
595:
594:
589:
588:
583:
579:
574:
566:
559:
558:
556:
552:
548:
544:
540:
536:
533:
532:
528:
523:
519:
516:
513:
509:
505:
502:
499:
495:
492:
491:
487:
485:
479:
477:
475:
465:
462:
459:
457:
454:
453:
452:
451:
447:
444:
441:
440:
439:
437:
433:
429:
422:
420:
418:
414:
409:
407:
403:
399:
398:
391:
386:
381:
379:
375:
371:
363:
361:
359:
355:
351:
347:
343:
339:
335:
331:
328:that support
327:
321:
316:
314:
310:
306:
301:
299:
295:
292:
288:
285:
281:
277:
269:
267:
265:
260:
258:
253:
251:
247:
242:
240:
236:
232:
228:
223:
221:
217:
213:
209:
205:
201:
197:
193:
188:
187:of that ISA.
186:
185:
180:
176:
173:controls the
172:
168:
164:
160:
156:
144:
139:
137:
132:
130:
125:
124:
122:
121:
116:
113:
111:
108:
104:
101:
100:
99:
96:
94:
91:
90:
89:
88:
83:
78:
75:
71:
68:
66:
63:
62:
61:
58:
56:
53:
52:
51:
50:
45:
42:
38:
33:
19:
4278:Chip carrier
4216:Clock gating
4135:Mixed-signal
4032:Write buffer
4009:Control unit
3821:Clock signal
3560:accelerators
3542:Cypress PSoC
3199:Simultaneous
3016:Out-of-order
2657:
2648:Neuromorphic
2529:Architecture
2487:Belt machine
2480:Zeno machine
2413:Hierarchical
2307:. Retrieved
2288:
2263:
2259:
2236:. Retrieved
2233:cpushack.net
2232:
2223:
2215:embedded.com
2214:
2204:
2192:
2181:. Retrieved
2177:
2168:
2141:
2135:
2123:. Retrieved
2113:
2103:
2096:
2069:
2063:
2052:. Retrieved
2040:
2036:
1991:
1982:
1972:
1934:
1928:
1916:. Retrieved
1911:
1907:
1897:
1883:(2): 37–45.
1880:
1874:
1868:
1858:February 21,
1856:. Retrieved
1852:the original
1847:
1837:
1816:
1808:
1797:. Retrieved
1793:the original
1788:
1779:
1687:
1668:
1657:
1646:
1632:
1617:or writable
1600:control unit
1589:
1582:
1544:
1533:
1526:
1491:
1483:
1462:machine code
1459:
1439:
1428:
1410:
1398:
1385:
1384:
1370:
1368:
1364:code density
1363:
1360:
1357:Code density
1351:
1346:
1342:
1289:
1268:
1258:
1257:
1238:
1236:
1204:
1184:
1175:store reg3,c
1153:
1144:add reg1,b,c
1130:
1107:
1098:store reg2,c
1076:
1055:store reg1,c
1036:instruction.
1033:
1029:
1019:
1011:
995:
961:
952:
922:
911:
907:
903:
899:
897:
892:
890:
873:
854:
847:
822:
816:
800:
771:
753:test-and-set
734:
702:DMA transfer
679:
653:
645:
637:
629:
611:
605:
597:
591:
585:
568:
560:
546:
542:
538:
534:
521:
517:
507:
503:
493:
483:
474:control flow
471:
436:instructions
435:
431:
426:
423:Instructions
410:
395:
389:
382:
369:
367:
323:
318:
305:architecture
304:
302:
273:
261:
257:machine code
254:
243:
227:machine code
224:
220:input/output
192:instructions
189:
182:
162:
158:
152:
85:Instructions
70:Opcode table
54:
41:Machine code
18:Code density
4063:Multiplexer
4027:Data buffer
3738:Single-core
3710:bit slicing
3568:Coprocessor
3423:Coprocessor
3304:performance
3226:Cooperative
3216:Speculative
3176:Distributed
3135:Superscalar
3120:Instruction
3088:Parallelism
3061:Speculative
2893:System/3x0
2765:Instruction
2542:Von Neumann
2455:Post–Turing
2043:(1): 4–11.
1664:interpreter
1494:system call
1167:load b,reg2
1163:load a,reg1
1140:move a,reg1
1090:load b,reg2
1086:load a,reg1
1047:load a,reg1
974:accumulator
960:1-operand (
921:0-operand (
740:instruction
713:square root
698:string copy
593:disjunction
587:conjunction
514:operations.
415:(MISC) and
309:Fred Brooks
235:performance
218:), and the
204:main memory
4293:Categories
4183:management
4078:Multiplier
3939:Logic gate
3929:Sequential
3836:Functional
3816:Clock rate
3789:Data cache
3762:Components
3743:Multi-core
3731:Core count
3221:Preemptive
3125:Pipelining
3108:Bit-serial
3051:Wide-issue
2996:Structural
2918:Tilera ISA
2884:MicroBlaze
2854:ETRAX CRIS
2749:Comparison
2594:Load–store
2574:Endianness
2309:2023-03-04
2238:2014-07-25
2183:2021-12-18
2054:2022-10-05
1799:2024-02-03
1772:References
1760:Simulation
1702:multiplier
1683:delay slot
1629:, or both.
1424:multi-core
1304:mainframes
1239:explicitly
1051:add b,reg1
893:explicitly
432:statements
370:complexity
313:System/360
196:data types
4117:Circuitry
4037:Microcode
3961:Registers
3804:coherence
3779:CPU cache
3637:Word size
3302:Processor
2946:Execution
2849:DEC Alpha
2827:Power ISA
2643:Cognitive
2450:Universal
2146:CiteSeerX
2125:5 October
1681:led to a
1655:(FPGAs).
1611:microcode
1536:NOP slide
1510:Zilog Z80
1474:compilers
1323:word size
1228:Power ISA
1212:ARM Thumb
1208:TI MSP430
1122:add a,b,c
861:0-operand
843:microcode
831:registers
813:constant.
721:logarithm
693:) at once
571:decrement
563:increment
456:registers
354:Transmeta
342:Microsoft
334:Smalltalk
264:computing
200:registers
4055:Datapath
3748:Manycore
3720:variable
3558:Hardware
3194:Temporal
2874:OpenRISC
2569:Cellular
2559:Dataflow
2552:modified
2286:(2003).
1918:March 2,
1876:Computer
1729:Emulator
1708:See also
1660:emulated
1651:may use
1635:Rekursiv
1442:compiler
1422:or in a
1335:halfword
1315:(RISC),
917:C = A+B
719:such as
682:typified
599:negation
580:Perform
543:multiply
539:subtract
498:register
406:compiler
330:bytecode
289:and the
270:Overview
171:software
165:) is an
4231:Related
4162:Quantum
4152:Digital
4147:Boolean
4045:Counter
3944:Quantum
3705:512-bit
3700:256-bit
3695:128-bit
3538:(MPSoC)
3523:on chip
3521:Systems
3339:(FLOPS)
3152:Process
3001:Control
2983:Hazards
2869:Itanium
2864:Unicore
2822:PowerPC
2547:Harvard
2507:Pointer
2502:Counter
2460:Quantum
2074:Bibcode
1789:arm.com
1504:uses 00
1444:. Most
1264:spilled
1181:C = A+B
1150:C = A+B
1127:C = A+B
1104:C = A+B
1073:C = A+B
1067:A = A+B
1063:C = A+B
1026:C = A+B
1014:; then
1006:CISC —
992:C = A+B
986:store c
949:C = A+B
827:operand
796:AltiVec
731:, etc.)
606:Compare
287:Pentium
77:Operand
4167:Switch
4157:Analog
3895:(IMC)
3866:(MMU)
3715:others
3690:64-bit
3685:48-bit
3680:32-bit
3675:24-bit
3670:16-bit
3665:15-bit
3660:12-bit
3497:Mobile
3413:Stream
3408:Barrel
3403:Vector
3392:(GPU)
3351:(SUPS)
3319:(IPC)
3171:Memory
3164:Vector
3147:Thread
3130:Scalar
2932:Others
2879:RISC-V
2844:SuperH
2813:Power
2809:MIPS-X
2784:PDP-11
2633:Fabric
2385:Models
2300:
2148:
2084:
1945:
1825:
1749:OVPsim
1577:, and
1516:while
1480:Design
1306:, and
1230:, and
1183:needs
1152:needs
1129:needs
1106:needs
1075:needs
1028:needs
1008:move A
994:needs
978:load a
951:needs
935:push b
931:push a
906:, and
859:have "
819:opcode
794:, and
792:3DNow!
779:vector
729:cosine
711:(e.g.
631:Branch
547:divide
443:opcode
340:, and
336:, the
294:Athlon
244:If an
179:device
98:Branch
60:Opcode
4223:(PPW)
4181:Power
4073:Adder
3949:Array
3916:Logic
3877:(TLB)
3860:(FPU)
3854:(AGU)
3848:(ALU)
3838:units
3774:Cache
3655:8-bit
3650:4-bit
3645:1-bit
3609:(TPU)
3603:(DSP)
3597:(PPU)
3591:(VPU)
3580:(GPU)
3549:(NoC)
3532:(SoC)
3467:(PoP)
3461:(SiP)
3455:(MCM)
3396:GPGPU
3386:(CPU)
3376:Types
3357:(PPW)
3345:(TPS)
3333:(IPS)
3325:(CPI)
3096:Level
2907:S/390
2902:S/370
2897:S/360
2839:SPARC
2817:POWER
2700:TRIPS
2668:Types
2033:(PDF)
1767:(RTL)
1639:Imsys
1487:cache
1405:AVR32
1401:Thumb
1347:mixed
1345:have
1341:with
1333:or a
1279:Alpha
1271:Thumb
1248:arity
1243:stack
1232:SPARC
1220:AVR32
1034:store
1016:add B
982:add b
943:pop c
869:stack
855:Most
715:, or
691:stack
553:in a
545:, or
522:write
392:(LIW)
324:Some
284:Intel
157:, an
4201:ACPI
3934:Glue
3826:FIFO
3769:Core
3507:ASIP
3448:CPLD
3443:FPOA
3438:FPGA
3433:ASIC
3286:SPMD
3281:MIMD
3276:MISD
3269:SWAR
3249:SIMD
3244:SISD
3159:Data
3142:Task
3113:Word
2859:M32R
2804:MIPS
2767:sets
2734:ZISC
2729:NISC
2724:OISC
2719:MISC
2712:EPIC
2707:VLIW
2695:EDGE
2685:RISC
2680:CISC
2589:HUMA
2584:NUMA
2298:ISBN
2127:2022
2082:ISBN
1943:ISBN
1920:2023
1860:2015
1823:ISBN
1642:Cjip
1627:PLAs
1619:RAMs
1615:ROMs
1553:", "
1534:The
1420:FPGA
1403:and
1390:RISC
1375:CISC
1331:byte
1296:VLIW
1277:and
1275:MIPS
1224:MIPS
912:reg1
775:SIMD
738:SIMD
725:sine
655:Call
590:and
520:and
518:Read
508:move
504:Copy
394:and
372:. A
358:VLIW
4196:APM
4191:PMU
4083:CPU
4040:ROM
3811:Bus
3428:PAL
3103:Bit
2889:LMC
2794:ARM
2789:x86
2779:VAX
2268:doi
2156:doi
2045:doi
1914:: 3
1885:doi
1644:).
1625:),
1561:".
1540:NOP
1524:.
1496:or
1472:by
1450:GCC
1339:ARM
1216:ARM
1199:VAX
1059:add
1018:to
1010:to
939:add
788:MMX
777:or
766:ALU
700:or
535:Add
494:Set
434:or
352:).
344:'s
291:AMD
175:CPU
163:ISA
153:In
93:NOP
4295::
4130:3D
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945:.
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