2453:. The input stage (the two latches on the left) processes the clock and data signals to ensure correct input signals for the output stage (the single latch on the right). If the clock is low, both the output signals of the input stage are high regardless of the data input; the output latch is unaffected and it stores the previous state. When the clock signal changes from low to high, only one of the output voltages (depending on the data signal) goes low and sets/resets the output latch: if D = 0, the lower output becomes low; if D = 1, the upper output becomes low. If the clock signal continues staying high, the outputs keep their states regardless of the data input and force the output latch to stay in the corresponding state as the input logical zero (of the output stage) remains active while the clock is high. Hence the role of the output latch is to store the data only while the clock is low.
1529:
the feedback loop. When input S = 1, then the OR gate outputs 1, regardless of the other input from the feedback loop ("set mode"). When input R = 1 then the AND gate outputs 0, regardless of the other input from the feedback loop ("reset mode"). And since the AND gate takes the output of the OR gate as input, R has priority over S. Latches drawn as cross-coupled gates may look less intuitive, as the behavior of one gate appears to be intertwined with the other gate. The standard NOR or NAND latches could also be re-drawn with the feedback loop, but in their case the feedback loop does not show the same signal value throughout the whole feedback loop. However, the SR AND-OR latch has the drawback that it would need an extra inverter, if an inverted Q output is needed.
2106:
2518:
high. As the clock signal goes high (0 to 1) the inverted "enable" of the first latch goes low (1 to 0) and the value seen at the input to the master latch is "locked". Nearly simultaneously, the twice inverted "enable" of the second or "slave" D latch transitions from low to high (0 to 1) with the clock signal. This allows the signal captured at the rising edge of the clock by the now "locked" master latch to pass through the "slave" latch. When the clock signal returns to low (1 to 0), the output of the "slave" latch is "locked", and the value seen at the last rising edge of the clock is held while the "master" latch begins to accept new values in preparation for the next rising clock edge.
3432:
data are close together in time, the flip-flop is forced to decide which event happened first. However fast the device is made, there is always the possibility that the input events will be so close together that it cannot detect which one happened first. It is therefore logically impossible to build a perfectly metastable-proof flip-flop. Flip-flops are sometimes characterized for a maximum settling time (the maximum time they will remain metastable under specified conditions). In this case, dual-ranked flip-flops that are clocked slower than the maximum allowed metastability time will provide proper conditioning for asynchronous (e.g., external) signals.
3428:
level, depending on the required reliability of the circuit. One technique for suppressing metastability is to connect two or more flip-flops in a chain, so that the output of each one feeds the data input of the next, and all devices share a common clock. With this method, the probability of a metastable event can be reduced to a negligible value, but never to zero. The probability of metastability gets closer and closer to zero as the number of flip-flops connected in series is increased. The number of flip-flops being cascaded is referred to as the "ranking"; "dual-ranked" flip flops (two flip-flops in series) is a common situation.
2434:
2620:
1035:
2486:
170:
2635:. This means that the digital output is stored on parasitic device capacitance while the device is not transitioning. This design facilities resetting by simply discharging one or more internal nodes. A common dynamic flip-flop variety is the true single-phase clock (TSPC) type which performs the flip-flop operation with little power and at high speeds. However, dynamic flip-flops will typically not work at static or low clock speeds: given enough time, leakage paths may discharge the parasitic capacitance enough to cause the flip-flop to enter invalid states.
38:
2066:
1696:
2422:
2152:
3038:
2607:
3054:
combination J = K = 1 is a command to toggle the flip-flop, i.e., change its output to the logical complement of its current value. Setting J = K = 0 maintains the current state. To synthesize a D flip-flop, simply set K equal to the complement of J (input J will act as input D). Similarly, to synthesize a T flip-flop, set K equal to J. The JK flip-flop is therefore a universal flip-flop, because it can be configured to work as an SR flip-flop, a D flip-flop, or a T flip-flop.
2587:
2050:
2400:, which are an essential part of many electronic devices. The advantage of the D flip-flop over the D-type "transparent latch" is that the signal on the D input pin is captured the moment the flip-flop is clocked, and subsequent changes on the D input will be ignored until the next clock event. An exception is that some flip-flops have a "reset" signal input, which will reset Q (to zero), and may be either asynchronous or synchronous with the clock.
1851:
2035:
2498:
2386:
3312:
2599:
3400:, which can happen when two inputs, such as data and clock or clock and reset, are changing at about the same time. When the order is not clear, within appropriate timing constraints, the result is that the output may behave unpredictably, taking many times longer than normal to settle to one state or the other, or even oscillating several times before settling. Theoretically, the time to settle down is not bounded. In a
1316:
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2644:
2193:
250:
233:
Eldred Nelson, who is responsible for coining the term while working at Hughes
Aircraft. Flip-flops in use at Hughes at the time were all of the type that came to be known as J-K. In designing a logical system, Nelson assigned letters to flip-flop inputs as follows: #1: A & B, #2: C & D, #3: E & F, #4: G & H, #5: J & K. Nelson used the notations "
720:
2130:
driving the latch because many common computational circuits have an OR layer followed by an AND layer as their last two levels. Merging the latch function can implement the latch with no additional gate delays. The merge is commonly exploited in the design of pipelined computers, and, in fact, was originally developed by John G. Earle to be used in the
3424:) respectively. These times are specified in the data sheet for the device, and are typically between a few nanoseconds and a few hundred picoseconds for modern devices. Depending upon the flip-flop's internal organization, it is possible to build a device with a zero (or even negative) setup or hold time requirement but not both simultaneously.
734:
4522:
2078:
3374:
transition that happens to fall between the recovery/removal time, eventually the flip-flop will transition to the appropriate state, but a very short glitch may or may not appear on the output, dependent on the synchronous input signal. This second situation may or may not have significance to a circuit design.
2164:
3053:
The JK flip-flop, augments the behavior of the SR flip-flop (J: Set, K: Reset) by interpreting the J = K = 1 condition as a "flip" or toggle command. Specifically, the combination J = 1, K = 0 is a command to set the flip-flop; the combination J = 0, K = 1 is a command to reset the flip-flop; and the
3427:
Unfortunately, it is not always possible to meet the setup and hold criteria, because the flip-flop may be connected to a real-time signal that could change at any time, outside the control of the designer. In this case, the best the designer can do is to reduce the probability of error to a certain
2283:
Most D-type flip-flops in ICs have the capability to be forced to the set or reset state (which ignores the D and clock inputs), much like an SR flip-flop. Usually, the illegal S = R = 1 condition is resolved in D-type flip-flops. Setting S = R = 0 makes the flip-flop behave as described above. Here
1528:
The SR AND-OR latch is easier to understand, because both gates can be explained in isolation, again with the control view of AND and OR from above. When neither S or R is set, then both the OR gate and the AND gate are in "hold mode", i.e., they let the input through, their output is the input from
793:
To derive the behavior of the SR NOR latch, consider S and R as control inputs and remember that, from the equations above, set and reset NOR with control 1 will fix their outputs to 0, while set and reset NOR with control 0 will act as a NOT gate. With this it is now possible to derive the behavior
381:
It is convenient to think of NAND, NOR, AND and OR as controlled operations, where one input is chosen as the control input set and the other bit as the input to be processed depending on the state of the control. Then, all of these gates have one control value that ignores the input (x) and outputs
3404:
system, this metastability can cause corruption of data or a program crash if the state is not stable before another circuit uses its value; in particular, if two different logical paths use the output of a flip-flop, one path can interpret it as a 0 and the other as a 1 when it has not resolved to
2200:
The D flip-flop is widely used, and known as a "data" flip-flop. The D flip-flop captures the value of the D-input at a definite portion of the clock cycle (such as the rising edge of the clock). That captured value becomes the Q output. At other times, the output Q does not change. The D flip-flop
1341:
The circuit uses the same feedback as SR NOR, just replacing NOR gates with NAND gates, to "remember" and retain its logical state even after the controlling input signals have changed. Again, recall that a 1-controlled NAND always outputs 0, while a 0-controlled NAND acts as a NOT gate. When the S
3431:
So-called metastable-hardened flip-flops are available, which work by reducing the setup and hold times as much as possible, but even these cannot eliminate the problem entirely. This is because metastability is more than simply a matter of circuit design. When the transitions in the clock and the
3319:
The input must be held steady in a period around the rising edge of the clock known as the aperture. Imagine taking a picture of a frog on a lily-pad. Suppose the frog then jumps into the water. If you take a picture of the frog as it jumps into the water, you will get a blurry picture of the frog
2517:
For a positive-edge triggered master–slave D flip-flop, when the clock signal is low (logical 0) the "enable" seen by the first or "master" D latch (the inverted clock signal) is high (logical 1). This allows the "master" latch to store the input value when the clock signal transitions from low to
1453:
From a teaching point of view, SR latches drawn as a pair of cross-coupled components (transistors, gates, tubes, etc.) are often hard to understand for beginners. A didactically easier explanation is to draw the latch as a single feedback loop instead of the cross-coupling. The following is an SR
785:
inputs as explained above. Notice that at this point, because everything is symmetric, it does not matter to which inputs the outputs are connected. We now break the symmetry by choosing which of the remaining control inputs will be our set and reset and we can call "set NOR" the NOR gate with the
291:
Since the elementary amplifying stages are inverting, two stages can be connected in succession (as a cascade) to form the needed non-inverting amplifier. In this configuration, each amplifier may be considered as an active inverting feedback network for the other inverting amplifier. Thus the two
283:
Clocked flip-flops are specially designed for synchronous systems; such devices ignore their inputs except at the transition of a dedicated clock signal (known as clocking, pulsing, or strobing). Clocking causes the flip-flop either to change or to retain its output signal based upon the values of
3549:
Alternatively, the two inputs may be called set 1 and set 0, which may clear confusion for some: the term set alone may be misunderstood as setting the bit to the input provided to set. This naming also makes it intuitive in the explanation below that trying to set 0 and 1 at the same time should
3381:
Differentiation between Setup/Hold and
Recovery/Removal times is often necessary when verifying the timing of larger circuits because asynchronous signals may be found to be less critical than synchronous signals. The differentiation offers circuit designers the ability to define the verification
3373:
Short impulses applied to asynchronous inputs (set, reset) should not be applied completely within the recovery-removal period, or else it becomes entirely indeterminable whether the flip-flop will transition to the appropriate state. In another case, where an asynchronous signal simply makes one
232:
under Eldred Nelson, who had coined the term JK for a flip-flop which changed states when both inputs were on (a logical "one"). The other names were coined by
Phister. They differ slightly from some of the definitions given below. Lindley explains that he heard the story of the JK flip-flop from
3526:) representation. The construction is similar to a conventional cross-coupled flip-flop; each output, when high, inhibits all the other outputs. Alternatively, more or less conventional flip-flops can be used, one per output, with additional circuitry to make sure only one at a time can be true.
1532:
Note that the SR AND-OR latch can be transformed into the SR NOR latch using logic transformations: inverting the output of the OR gate and also the 2nd input of the AND gate and connecting the inverted Q output between these two added inverters; with the AND gate with both inputs inverted being
1524:
Note that the SR AND-OR latch has the benefit that S = 1, R = 1 is well defined. In above version of the SR AND-OR latch it gives priority to the R signal over the S signal. If priority of S over R is needed, this can be achieved by connecting output Q to the output of the OR gate instead of the
2594:
Flip-Flops that read in a new value on the rising and the falling edge of the clock are called dual-edge-triggered flip-flops. Such a flip-flop may be built using two single-edge-triggered D-type flip-flops and a multiplexer, or by using two single-edge triggered D-type flip-flops and three XOR
2513:
input to one of them. It is called master–slave because the master latch controls the slave latch's output value Q and forces the slave latch to hold its value whenever the slave latch is enabled, as the slave latch always copies its new value from the master latch and changes its value only in
2129:
Designers looked for alternatives. A successful alternative is the Earle latch. It requires only a single data input, and its output takes a constant two gate delays. In addition, the two gate levels of the Earle latch can, in some cases, be merged with the last two gate levels of the circuits
2627:
An efficient functional alternative to a D flip-flop can be made with dynamic circuits (where information is stored in a capacitance) as long as it is clocked often enough; while not a true flip-flop, it is still called a flip-flop for its functional role. While the master–slave D element is
2125:
The classic gated latch designs have some undesirable characteristics. They require double-rail logic or an inverter. The input-to-output propagation may take up to three gate delays. The input-to-output propagation is not constant – some outputs take two gate delays while others take three.
388:
2476:
NAND latches are used in the positive-edge-triggered D flip-flop. The role of these latches is to "lock" the active output producing low voltage (a logical zero); thus the positive-edge-triggered D flip-flop can also be thought of as a gated D latch with latched input gates.
3949:
3320:
jumping into the water—it's not clear which state the frog was in. But if you take a picture while the frog sits steadily on the pad (or is steadily in the water), you will get a clear picture. In the same way, the input to a flip-flop must be held steady during the
2077:
786:
set control and "reset NOR" the NOR with the reset control; in the figures the set NOR is the bottom one and the reset NOR is the top one. The output of the reset NOR will be our stored bit Q, while we will see that the output of the set NOR stores its complement
1446:
3020:
When T is held high, the toggle flip-flop divides the clock frequency by two; that is, if clock frequency is 4 MHz, the output frequency obtained from the flip-flop will be 2 MHz. This "divide by" feature has application in various types of digital
120:, the output and next state depend not only on its current input, but also on its current state (and hence, previous inputs). It can also be used for counting of pulses, and for synchronizing variably-timed input signals to some reference timing signal.
3517:
In a conventional flip-flop, exactly one of the two complementary outputs is high. This can be generalized to a memory element with N outputs, exactly one of which is high (alternatively, where exactly one of N is low). The output is therefore always a
2163:
746:
2105:
1867:
This latch exploits the fact that, in the two active input combinations (01 and 10) of a gated SR latch, R is the complement of S. The input NAND stage converts the two D input states (0 and 1) to these two input combinations for the next
3377:
Set and Reset (and other) signals may be either synchronous or asynchronous and therefore may be characterized with either Setup/Hold or
Recovery/Removal times, and synchronicity is very dependent on the design of the flip-flop.
3695:
2728:
2628:
triggered on the edge of a clock, its components are each triggered by clock levels. The "edge-triggered D flip-flop", as it is called even though it is not a true flip-flop, does not have the master–slave properties.
2651:
If the T input is high, the T flip-flop changes state ("toggles") whenever the clock input is strobed. If the T input is low, the flip-flop holds the previous value. This behavior is described by the characteristic
1638:
its output (oscillate between 0 and 1) when passed the input combination of 11. Unlike the JK flip-flop, the 11 input combination for the JK latch is not very useful because there is no clock that directs toggling.
798:
While the R and S are both zero, both R NOR and S NOR simply impose the feedback being the complement of the output, this is satisfied as long as the outputs are the complement of each other. Thus the outputs Q and
3533:. In this case the memory element retains exactly one of the logic states until the control inputs induce a change. In addition, a multiple-valued clock can also be used, leading to new possible clock transitions.
715:{\displaystyle {\begin{aligned}NAND(x,0)&=1&NAND(x,1)&={\bar {x}}\\NOR(x,0)&={\bar {x}}&NOR(x,1)&=0\\AND(x,0)&=0&AND(x,1)&={x}\\OR(x,0)&=x&OR(x,1)&=1\\\end{aligned}}}
1342:
and R inputs are both high, feedback maintains the Q outputs to the previous state. When either is zero, they fix their output bits to 0 while to other adapts to the complement. S=R=0 produces the invalid state.
3117:
3505:
Flip-flops can be generalized in at least two ways: by making them 1-of-N instead of 1-of-2, and by adapting them to logic with more than two states. In the special cases of 1-of-3 encoding, or multi-valued
1153:
1338:
for Set and Reset respectively. Because the NAND inputs must normally be logic 1 to avoid affecting the latching action, the inputs are considered to be inverted in this circuit (or active low).
393:
1213:
1273:
293:
3408:
The metastability in flip-flops can be avoided by ensuring that the data and control inputs are held valid and constant for specified periods before and after the clock pulse, called the
2151:
3360:
the clock event, so that the data is reliably sampled by the clock. The recovery time for the asynchronous set or reset input is thereby similar to the setup time for the data input.
3370:
the clock event, so that the data is reliably sampled by the clock. The removal time for the asynchronous set or reset input is thereby similar to the hold time for the data input.
2403:
The above circuit shifts the contents of the register to the right, one bit position on each active transition of the clock. The input X is shifted into the leftmost bit position.
3475:) of the following flip-flop, so data present at the input of the succeeding flip-flop is properly "shifted in" following the active edge of the clock. This relationship between t
3483:
is normally guaranteed if the flip-flops are physically identical. Furthermore, for correct operation, it is easy to verify that the clock period has to be greater than the sum t
146:
When a level-triggered latch is enabled it becomes transparent, but an edge-triggered flip-flop's output only changes on a clock edge (either positive going or negative going).
2883:
2831:
1912:
comes from the fact that, when the enable input is on, the signal propagates directly through the circuit, from the input D to the output Q. Gated D-latches are also
770:
The SR NOR latch consists of two parallel NOR gates where the output of each NOR is also fanned out into one input of the other NOR, as shown in the figure. We call
5093:
1302:
364:
Its two inputs S and R can set the internal state to 1 using the combination S=1 and R=0, and can reset the internal state to 0 using the combination S=0 and R=1.
4658:
2904:
2855:
2803:
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347:
4459:
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4269:
4928:
2065:
4830:
154:
4517:, Lapidus, Peter D., "Flip flop supporting glitchless operation on a one-hot bus and method", published 2005-12-13, assigned to
4244:
2662:
106:(binary digit) of data; one of its two states represents a "one" and the other represents a "zero". Such data storage can be used for storage of
4933:
1425:
320:(see History section above). The behavior of a particular type can be described by the characteristic equation that derives the "next" output (
4435:
4356:
4172:
4042:
3974:
3881:
3854:
3786:
3631:
2049:
123:
The term flip-flop has historically referred generically to both level-triggered (asynchronous, transparent, or opaque) and edge-triggered (
4765:
3025:. A T flip-flop can also be built using a JK flip-flop (J & K pins are connected together and act as T) or a D flip-flop (T input XOR Q
2632:
3063:
1663:
latches follow each other, if they are all transparent at the same time, signals will propagate through them all. However, following a
292:
stages are connected in a non-inverting loop although the circuit diagram is usually drawn as a symmetric cross-coupled pair (both the
4878:
4777:
4812:
4651:
4328:
4070:
4015:
3925:
3674:
1449:
An SR AND-OR latch. Light green means logical '1' and dark green means logical '0'. The latch is currently in hold mode (no change).
3754:
Report of the Eighty-seventh
Meeting of the British Association for the Advancement of Science: Bournemouth: 1919, September 9–13
1651:
That is, input signal changes cause immediate changes in output. Additional logic can be added to a transparent latch to make it
4489:
2619:
5103:
4824:
4760:
1034:
3693:, Eccles, William Henry & Jordan, Frank Wilfred, "Improvements in ionic relays", published 1920-08-05
1095:
1760:
true), the signals can pass through the input gates to the encapsulated latch; all signal combinations except for (0, 0) =
4950:
4818:
3603:
3452:), which is the time a flip-flop takes to change its output after the clock edge. The time for a high-to-low transition (t
2485:
1064:
169:
4612:
4088:
Proceedings of the
November 30--December 1, 1965, fall joint computer conference, Part I on XX - AFIPS '65 (Fall, part I)
5098:
4644:
3397:
3391:
810:=0, while the reset NOR will adapt and set Q=1. Once S is set back to zero the values are maintained as explained above.
5067:
4962:
4518:
3583:
2433:
1158:
1024:
794:
of the SR latch as simple conditions (instead of, for example, assigning values to each line see how they propagate):
254:
1919:
Transparent latches are typically used as I/O ports or in asynchronous systems, or in synchronous two-phase systems (
3941:
1466:
gate. Note that the inverter is not needed for the latch functionality, but rather to make both inputs High-active.
4982:
4940:
2460:
as both the circuits convert the two D input states (0 and 1) to two input combinations (01 and 10) for the output
1927:), where two latches operating on different clock phases prevent data transparency as in a master–slave flip-flop.
1227:
182:
173:
Schematics from the Eccles and Jordan trigger relay patent filed 1918, one drawn as a cascade of amplifiers with a
37:
31:
4883:
4868:
4794:
4754:
3568:
1545:
The JK latch is much less frequently used than the JK flip-flop. The JK latch follows the following state table:
217:
1027:
state and may eventually lock at either 1 or 0 depending on the propagation time relations between the gates (a
5118:
5108:
4895:
4800:
4788:
108:
4273:
3731:
3607:
4945:
4723:
3440:
Another important timing value for a flip-flop is the clock-to-output delay (common symbol in data sheets: t
2131:
269:
229:
201:
and such circuits and their transistorized versions were common in computers even after the introduction of
143:
for level-triggered ones. The terms "edge-triggered", and "level-triggered" may be used to avoid ambiguity.
4536:
Irving, Thurman A.; Shiva, Sajjan G.; Nagle, H. Troy (March 1976). "Flip-Flops for
Multiple-Valued Logic".
4449:
3989:
2464:
latch by inverting the data input signal (both the circuits split the single D signal in two complementary
725:
Essentially, they can all be used as switches that either set a specific value or let an input value pass.
260:
Transparent or asynchronous latches can be built around a single pair of cross-coupled inverting elements:
5039:
4836:
4293:
4200:
3133:
2753:
1671:
latch (or vice-versa) causes the state and output to only change on clock edges, forming what is called a
832:
78:
5051:
5005:
4873:
4771:
4708:
2112:
1459:
273:
3713:
820:
If R=S=1, the NORs will fix both outputs to 0, which is not a valid state storing complementary values.
4514:
4248:
3944:, Nelson, Eldred C., "High-speed printing system", published 1958-09-02, assigned to
3749:
2606:
5113:
4977:
4972:
4955:
4675:
3690:
3606:'s Logic Handfbook Flip Chip™ Modules 1969 edition calls transparent RS latches as "R/S Flip Flops" (
3350:
is the sum of setup and hold time. The data input should be held steady throughout this time period.
2861:
2809:
117:
5024:
4967:
4806:
4728:
4703:
4667:
4205:
3945:
1880:. This configuration prevents application of the restricted input combination. It is also known as
1534:
94:
2157:
Earle latch uses complementary enable inputs: enable active low (E_L) and enable active high (E_H)
1695:
5044:
4910:
4748:
4713:
4588:
4553:
4401:
4226:
4113:
4101:
3826:
3530:
2501:
An implementation of a master–slave D flip-flop that is triggered on the rising edge of the clock
1938:
lock input is 0, the D input has no effect on the output. When E/C is high, the output equals D.
1920:
265:
202:
150:
86:
74:
2586:
3778:
3037:
5000:
4431:
4393:
4352:
4324:
4218:
4168:
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4038:
4011:
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3921:
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3850:
3782:
3670:
3627:
3445:
3022:
2206:
198:
174:
4003:
2521:
Removing the leftmost inverter in the circuit creates a D-type flip-flop that strobes on the
4733:
4580:
4545:
4471:
4385:
4210:
4091:
3818:
3500:
3138:
2758:
2631:
Edge-triggered D flip-flops are often implemented in integrated high-speed operations using
2421:
837:
113:
90:
1876:
signal produces the inactive "11" combination. Thus a gated D-latch may be considered as a
1850:
1042:
To overcome the restricted combination, one can add gates to the inputs that would convert
357:
When using static gates as building blocks, the most fundamental latch is the asynchronous
4923:
4918:
4900:
4863:
4858:
4783:
4743:
4616:
4571:
Wu, Haomin; Zhuang Nan (July 1991). "Research into ternary edge-triggered JKL flip-flop".
4125:
3578:
3573:
2497:
2397:
2385:
2202:
2034:
1924:
1424:
1278:
382:
a constant value, while the other control value lets the input pass (maybe complemented):
4629:
2472:
signals). The difference is that NAND logical gates are used in the gated D latch, while
4008:
Mathematical
Systems Theory I: Modelling, State Space Analysis, Stability and Robustness
3311:
1330:
The circuit shown below is a basic NAND latch. The inputs are also generally designated
17:
4853:
4622:
4373:
4191:
Kunkel, Steven R.; Smith, James E. (May 1986). "Optimal
Pipelining in Supercomputers".
3899:
3771:
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2889:
2840:
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2767:
2390:
1028:
813:
Similarly, if R=1 while S=0, then the reset NOR fixes Q=0 while the set NOR with adapt
332:
4451:
The design and application of a "flip-flap-flop" using tunnel diodes (Master's thesis)
2598:
2141:, which is commonly used because it demands less logic. However, it is susceptible to
2137:
The Earle latch is hazard free. If the middle NAND gate is omitted, then one gets the
85:
applied to one or more control inputs and will output its state (often along with its
5087:
5034:
5017:
5012:
4493:
3802:
3646:
3507:
3366:
is the minimum amount of time the asynchronous set or reset input should be inactive
3356:
is the minimum amount of time the asynchronous set or reset input should be inactive
2506:
2276:
766:
Transitioning from the restricted combination (D) to (A) leads to an unstable state.
210:
4592:
4557:
4405:
4105:
3830:
1315:
4230:
1799:
1749:(with non-inverting enable) can be made by adding a second level of AND gates to a
1683:
1445:
220:, the flip-flop types detailed below (SR, D, T, JK) were first discussed in a 1954
186:
128:
2083:
An animated gated D latch. Black and white mean logical '1' and '0', respectively.
4425:
4162:
4032:
3964:
3915:
3871:
3844:
3621:
2610:
A dual-edge triggered D flip-flop implemented using XOR gates, and no multiplexer
1000:
because, as both NOR gates then output zeros, it breaks the logical equation Q =
284:
the input signals at the transition. Some flip-flops change output on the rising
4304:
3045:
2739:
2169:
An animated Earle latch. Black and white mean logical '1' and '0', respectively.
285:
261:
194:
158:
124:
62:
4086:
Cotten, L. W. (1965). "Circuit implementation of high-speed pipeline systems".
2643:
2192:
224:
course on computer design by
Montgomery Phister, and then appeared in his book
209:
are also common now. Early latches were known variously as trigger circuits or
5072:
4738:
4683:
4609:
1324:
375:
277:
206:
132:
4397:
4323:. Upper Saddle River, NJ, USA: Pearson Education International. p. 283.
4222:
3529:
Another generalization of the conventional flip-flop is a memory element for
749:
An animated SR latch. Black and white mean logical '1' and '0', respectively.
5029:
4698:
4549:
4419:
4389:
4096:
3822:
1704:
745:
372:
97:
systems used in computers, communications, and many other types of systems.
2723:{\displaystyle Q_{\text{next}}=T\oplus Q=T{\overline {Q}}+{\overline {T}}Q}
249:
100:
Flip-flops and latches are used as data storage elements to store a single
3608:
http://www.bitsavers.org/pdf/dec/handbooks/Digital_Logic_Handbook_1969.pdf
181:
The first electronic latch was invented in 1918 by the British physicists
4693:
4688:
4630:"Reverse-engineering a 1960s hybrid flip flop module with X-ray CT scans"
4475:
4446:
actually appeared much earlier in the computing literature, for example,
4376:(April 1973). "Anomalous Behavior of Synchronizer and Arbiter Circuits".
3401:
2731:
2653:
2623:
A CMOS IC implementation of a dynamic edge-triggered flip-flop with reset
1700:
1455:
772:
738:
368:
4214:
3651:"...Sometimes the terms flip-flop and latch are used interchangeably..."
2514:
response to a change in the value of the master latch and clock signal.
4584:
3519:
2115:, similar to the ones in the CD4042 or the CD74HC75 integrated circuits
1463:
781:
these output-to-input connections. The remaining inputs we will use as
4636:
3456:) is sometimes different from the time for a low-to-high transition (t
1659:
when another input (an "enable" input) is not asserted. When several
737:
An animation of a SR latch, constructed from a pair of cross-coupled
82:
3344:
the clock event, so that the data is reliably sampled by the clock.
3334:
the clock event, so that the data is reliably sampled by the clock.
3750:"A trigger relay utilising three electrode thermionic vacuum tubes"
3732:"A trigger relay utilizing three-electrode thermionic vacuum tubes"
3714:"A trigger relay utilizing three-electrode thermionic vacuum tubes"
3340:
is the minimum amount of time the data input should be held steady
3330:
is the minimum amount of time the data input should be held steady
2489:
A master–slave D flip-flop. It responds on the falling edge of the
733:
3876:(revised ed.). Research & Education Assoc. p. 1223.
3806:
3310:
3044:
3036:
2642:
2618:
2605:
2597:
2585:
2496:
2484:
2384:
2284:
is the truth table for the other possible S and R configurations:
2191:
1682:
1444:
1314:
1033:
744:
732:
248:
168:
36:
3112:{\displaystyle Q_{\text{next}}=J{\overline {Q}}+{\overline {K}}Q}
77:
that have two stable states that can store state information – a
3849:(4th ed.). Delmar Thomson (Cengage) Learning. p. 299.
221:
4640:
2145:. Intentionally skewing the clock signal can avoid the hazard.
1872:
latch by inverting the data input signal. The low state of the
1783:
and remains in the state it was left the last time E was high.
3463:
When cascading flip-flops which share the same clock (as in a
3405:
stable state, putting the machine into an inconsistent state.
102:
2396:
These flip-flops are very useful, as they form the basis for
367:
The SR latch can be constructed from a pair of cross-coupled
329:) in terms of the input signal(s) and/or the current output,
4164:
The Microarchitecture of Pipelined and Superscalar Computers
3769:
Pugh, Emerson W.; Johnson, Lyle R.; Palmer, John H. (1991).
93:. Flip-flops and latches are fundamental building blocks of
3897:
Lindley, P.L. (August 1968). "letter dated June 13, 1968".
3315:
Flip-flop setup, hold and clock-to-output timing parameters
3041:
A circuit symbol for a positive-edge-triggered JK flip-flop
149:
Different types of flip-flops and latches are available as
1007:. The combination is also inappropriate in circuits where
4139:
Earle, John G. (March 1965). "Latched Carry-Save Adder".
1916:
with respect to the level of the clock or enable signal.
1715:
can be made by adding a second level of NAND gates to an
1078:
Alternatively, the restricted combination can be made to
304:
Flip-flops and latches can be divided into common types:
3963:
Langholz, Gideon; Kandel, Abraham; Mott, Joe L. (1998).
3471:
of a preceding flip-flop is longer than the hold time (t
2505:
A master–slave D flip-flop is created by connecting two
2439:
A positive-edge-triggered D flip-flop with set and reset
1046:
to one of the non-restricted combinations. That can be:
817:=1. Again the state is maintained if R is set back to 0.
153:, usually with multiple elements per chip. For example,
3665:
Roth, Charles H. Jr. (1995). "Latches and Flip-Flops".
1691:
Latch (Clocked SR flip-flop). Note the inverted inputs.
1148:{\displaystyle Q_{\text{next}}={\bar {R}}Q+{\bar {R}}S}
803:
are maintained in a constant state, whether Q=0 or Q=1.
741:. Red and black mean logical '1' and '0', respectively.
296:
are initially introduced in the Eccles–Jordan patent).
4349:
Digital Design and Computer Architecture - ARM Edition
3660:
3658:
2590:
An implementation of a dual-edge-triggered D flip-flop
1719:. The extra NAND gates further invert the inputs so a
4002:
Hinrichsen, Diederich; Pritchard, Anthony J. (2006).
3382:
conditions for these types of signals independently.
3066:
2892:
2864:
2843:
2812:
2791:
2770:
2665:
2525:
of a clock signal. This has a truth table like this:
1281:
1230:
1161:
1098:
391:
335:
177:
path, and the other as a symmetric cross-coupled pair
3057:
The characteristic equation of the JK flip-flop is:
2414:
A few different types of edge triggered D flip‑flops
2288:
378:. The stored bit is present on the output marked Q.
139:
exclusively for edge-triggered storage elements and
5060:
4993:
4909:
4846:
4674:
4321:
Logic and Computer Design Fundamentals, 3rd Edition
2602:
Circuit symbol of a dual-edge-triggered D flip-flop
2446:This circuit consists of two stages implemented by
1634:Hence, the JK latch is an SR latch that is made to
3770:
3111:
2898:
2877:
2849:
2825:
2797:
2776:
2722:
1806:(to the level of the clock signal), as opposed to
1699:A gated SR latch circuit diagram constructed from
1296:
1267:
1207:
1147:
714:
341:
216:According to P. L. Lindley, an engineer at the US
1089:The characteristic equation for the SR latch is:
131:) circuits that store a single bit of data using
3712:Eccles, W.H.; Jordan, F.W. (19 September 1919).
1218:where A + B means (A or B), AB means (A and B)
1208:{\displaystyle Q_{\text{next}}={\bar {R}}(Q+S).}
241:-input" in a patent application filed in 1953.
4652:
3990:"Summary of the Types of Flip-flop Behaviour"
2407:Classical positive-edge-triggered D flip-flop
2391:serial-in, parallel-out (SIPO) shift register
2280:condition, meaning the signal is irrelevant)
1268:{\displaystyle Q_{\text{next}}=S+{\bar {R}}Q}
81:. The circuit can be made to change state by
8:
3730:Eccles, W.H.; Jordan, F.W. (December 1919).
806:If S=1 while R=0, then the set NOR will fix
4314:
4312:
4294:A Survey of Digital Computer Memory Systems
3396:Flip-flops are subject to a problem called
197:). The design was used in the 1943 British
4659:
4645:
4637:
4430:. Princeton University Press. p. 57.
4319:Mano, M. Morris; Kime, Charles R. (2004).
3510:, such an element may be referred to as a
1930:The truth table below shows that when the
1643:Gated latches and conditional transparency
988:, that is, either 0 or 1 is a valid value.
288:of the clock, others on the falling edge.
280:have all been used in practical circuits.
205:, though latches and flip-flops made from
4342:
4340:
4204:
4186:
4184:
4156:
4154:
4095:
4004:"Example 1.5.6 (R–S latch and J–K latch)"
3096:
3083:
3071:
3065:
2891:
2869:
2863:
2842:
2817:
2811:
2790:
2769:
2707:
2694:
2670:
2664:
1280:
1251:
1250:
1235:
1229:
1176:
1175:
1166:
1160:
1131:
1130:
1113:
1112:
1103:
1097:
635:
517:
516:
470:
469:
392:
390:
334:
89:too). It is the basic storage element in
27:Electronic circuit with two stable states
4056:
4054:
4034:Digital design and computer organization
3873:The Electronics problem solver, Volume 1
3623:Digital electronics and design with VHDL
3126:
2746:
2615:Edge-triggered dynamic D storage element
2529:
2216:
2071:A gated D latch based on an SR NOR latch
2033:
1944:
1849:
1816:
1694:
1549:
1470:
1423:
1348:
825:
157:is a quadruple transparent latch in the
4831:Application-specific integrated circuit
4063:The Architecture of Pipelined Computers
4037:. Vol. 1. CRC Press. p. 274.
3595:
3550:make the SR latch behave unpredictably.
3542:
3467:), it is important to ensure that the t
2647:A circuit symbol for a T-type flip-flop
2481:Master–slave edge-triggered D flip-flop
2147:
2045:
5094:Computer-related introductions in 1918
4619:, shows interactive flipflop circuits.
4193:ACM SIGARCH Computer Architecture News
4121:
4111:
3649:(EE 42/100 Lecture 24 from Berkeley)
3122:and the corresponding truth table is:
2456:The circuit is closely related to the
1764:then immediately reproduce on the (Q,
1533:equivalent to a NOR gate according to
1071:Hold state (0, 0) – referred to as an
992:The R = S = 1 combination is called a
193:and consisted of two active elements (
2427:A positive-edge-triggered D flip-flop
1323:latch constructed from cross-coupled
253:A transparent latch circuit based on
112:, and such a circuit is described as
7:
4766:Three-dimensional integrated circuit
226:Logical Design of Digital Computers.
3966:Foundations of Digital Logic Design
3917:Logical Design of Digital Computers
3870:Fogiel, Max; Gu, You-Liang (1998).
3748:Eccles, W.H.; Jordan, F.W. (1919).
228:Lindley was at the time working at
4778:Erasable programmable logic device
3811:Annals of the History of Computing
2457:
2447:
2201:can be viewed as a memory cell, a
2142:
135:. Modern authors reserve the term
25:
4813:Complex programmable logic device
4141:IBM Technical Disclosure Bulletin
3969:. World Scientific. p. 344.
1056:Q = 0 (0, 1) – referred to as an
1050:Q = 1 (1, 0) – referred to as an
4351:. Morgan Kaufmann, Waltham, MA.
3626:. Morgan Kaufmann. p. 329.
2432:
2420:
2162:
2150:
2104:
2076:
2064:
2048:
1023:). The output could remain in a
4825:Field-programmable object array
4761:Mixed-signal integrated circuit
4065:. McGraw-Hill. pp. 25–27.
3773:IBM's 360 and early 370 systems
2878:{\displaystyle Q_{\text{next}}}
2826:{\displaystyle Q_{\text{next}}}
2582:Dual-edge-triggered D flip-flop
1842:The same as non-gated SR latch
116:in electronics. When used in a
4573:Journal of Electronics (China)
4538:IEEE Transactions on Computers
4378:IEEE Transactions on Computers
1878:one-input synchronous SR latch
1256:
1199:
1187:
1181:
1136:
1118:
1082:the output. The result is the
695:
683:
662:
650:
625:
613:
589:
577:
551:
539:
522:
506:
494:
475:
459:
447:
420:
408:
353:Asynchronous set-reset latches
199:Colossus codebreaking computer
189:. It was initially called the
1:
4951:Hardware description language
4819:Field-programmable gate array
4628:Shirriff, Ken (August 2022).
4454:. University of North Dakota.
4347:Harris, S; Harris, D (2016).
3992:. Retrieved on 16 April 2018.
3604:Digital Equipment Corporation
2509:in series, and inverting the
1790:input signal may be called a
1083:
1065:programmable logic controller
1063:This is done in nearly every
191:Eccles–Jordan trigger circuit
4427:Number: from Ahmes to Cantor
4167:. Springer. pp. 40–42.
4010:. Springer. pp. 63–64.
3914:Phister, Montgomery (1958).
3667:Fundamentals of Logic Design
3392:Metastability in electronics
3101:
3088:
2712:
2699:
2055:A gated D latch based on an
1768:) output, i.e. the latch is
255:bipolar junction transistors
4963:Formal equivalence checking
4519:Advanced Micro Devices Inc.
4270:"Edge-Triggered Flip-flops"
3846:Introduction to electronics
3620:Pedroni, Volnei A. (2008).
3584:Static random-access memory
3049:JK flip-flop timing diagram
1854:Symbol for a gated SR latch
1647:Latches are designed to be
5135:
4983:Hierarchical state machine
4941:Transaction-level modeling
4490:"Ternary "flip-flap-flop""
4458:Alexander, W. (Feb 1964).
4448:Bowdon, Edward K. (1960).
4031:Farhat, Hassan A. (2004).
3498:
3389:
2738:and can be described in a
2038:Symbol for a gated D latch
1946:Gated D latch truth table
1802:, the latch is said to be
1494:No change; random initial
1472:SR AND-OR latch operation
1416:No change; random initial
29:
4884:Digital signal processing
4869:Logic in computer science
4795:Programmable logic device
4755:Hybrid integrated circuit
4424:Midhat J. Gazalé (2000).
3569:Pulse transition detector
3137:
3132:
2757:
2752:
2294:
2291:
1956:
1818:Gated SR latch operation
1038:How an SR NOR latch works
836:
831:
762:S = 1, R = 1: Not allowed
218:Jet Propulsion Laboratory
4896:Switching circuit theory
4801:Programmable Array Logic
4789:Programmable logic array
4161:Omondi, Amos R. (1999).
4061:Kogge, Peter M. (1981).
3807:"The Design of Colossus"
2493:input (usually a clock).
1966:
1961:
1958:
1953:
1950:
1900:signal (sometimes named
1822:
1742:with inverted enable).
1525:output of the AND gate.
1015:(i.e. a transition from
270:field-effect transistors
18:Edge-triggered flip-flop
4946:Register-transfer level
4550:10.1109/TC.1976.5009250
4390:10.1109/T-C.1973.223730
4097:10.1145/1463891.1463945
3843:Gates, Earl D. (2000).
3823:10.1109/MAHC.1983.10079
3128:JK flip-flop operation
2132:IBM System/360 Model 91
1834:No action (hold state)
1810:like flip-flops below.
1734:would transform into a
1221:Another expression is:
5104:Electronic engineering
4837:Tensor Processing Unit
4460:"The ternary computer"
3920:. Wiley. p. 128.
3647:Latches and Flip Flops
3316:
3113:
3050:
3042:
2948:Hold state (no clock)
2922:Hold state (no clock)
2900:
2879:
2851:
2827:
2799:
2778:
2748:T flip-flop operation
2724:
2648:
2624:
2611:
2603:
2591:
2502:
2494:
2393:
2197:
2039:
1855:
1708:
1692:
1673:master–slave flip-flop
1450:
1433:
1327:
1298:
1269:
1209:
1149:
1039:
994:restricted combination
767:
742:
716:
343:
257:
178:
79:bistable multivibrator
58:
5052:Electronic literature
5006:Hardware acceleration
4874:Computer architecture
4772:Emitter-coupled logic
4709:Printed circuit board
4464:Electronics and Power
3777:. MIT Press. p.
3669:(4th ed.). PWS.
3314:
3302:Timing considerations
3114:
3048:
3040:
3029:drives the D input).
2901:
2880:
2852:
2828:
2800:
2779:
2725:
2646:
2622:
2609:
2601:
2589:
2500:
2488:
2388:
2195:
2176:D = 0, E_H = 1: reset
2113:pass transistor logic
2037:
1853:
1698:
1686:
1551:JK latch truth table
1448:
1427:
1318:
1299:
1270:
1210:
1150:
1037:
748:
736:
717:
344:
252:
172:
40:
4978:Finite-state machine
4956:High-level synthesis
4891:Circuit minimization
4476:10.1049/ep.1964.0037
4418:Often attributed to
4199:(2). ACM: 404–411 .
4090:. pp. 489–504.
3134:Characteristic table
3064:
2890:
2862:
2841:
2810:
2789:
2768:
2754:Characteristic table
2663:
2179:D = 1, E_H = 0: hold
1779:false) the latch is
1703:gates (on left) and
1454:latch built with an
1297:{\displaystyle SR=0}
1279:
1228:
1159:
1096:
833:Characteristic table
389:
359:Set-Reset (SR) latch
333:
118:finite-state machine
30:For other uses, see
5099:Digital electronics
5025:Digital photography
4807:Generic Array Logic
4729:Combinational logic
4704:Printed electronics
4668:Digital electronics
4372:Chaney, Thomas J.;
4305:SN7474 TI datasheet
4215:10.1145/17356.17403
3946:Hughes Aircraft Co.
3129:
2749:
2173:D = 1, E_H = 1: set
2139:polarity hold latch
2111:A gated D latch in
2096:D = 0, E = 1: reset
1947:
1921:synchronous systems
1819:
1552:
1473:
1354:
1058:R (dominated)-latch
1052:S (dominated)-latch
828:
827:SR latch operation
759:S = 0, R = 1: Reset
266:bipolar transistors
203:integrated circuits
151:integrated circuits
95:digital electronics
4973:Asynchronous logic
4749:Integrated circuit
4714:Electronic circuit
4615:2015-04-08 at the
4610:FlipFlop Hierarchy
4585:10.1007/BF02778378
4374:Molnar, Charles E.
3803:Flowers, Thomas H.
3531:multi-valued logic
3324:of the flip-flop.
3317:
3127:
3109:
3051:
3043:
2896:
2875:
2847:
2823:
2795:
2774:
2747:
2720:
2649:
2625:
2612:
2604:
2592:
2503:
2495:
2394:
2198:
2196:D flip-flop symbol
2134:for that purpose.
2093:D = 0, E = 0: hold
2090:D = 1, E = 0: hold
2040:
1945:
1856:
1817:
1709:
1693:
1550:
1471:
1451:
1434:
1349:
1328:
1294:
1265:
1205:
1145:
1040:
1011:inputs may go low
826:
768:
756:S = 0, R = 0: Hold
743:
712:
710:
339:
258:
179:
87:logical complement
59:
5081:
5080:
5030:Digital telephone
5001:Computer hardware
4968:Synchronous logic
4623:The J-K Flip-Flop
4470:(2). IET: 36–39.
4437:978-0-691-00515-7
4358:978-0-12-800056-4
4245:"The D Flip-Flop"
4174:978-0-7923-8463-2
4044:978-0-8493-1191-8
3976:978-981-02-3110-1
3883:978-0-87891-543-9
3856:978-0-7668-1698-5
3788:978-0-262-16123-7
3756:. pp. 271–2.
3633:978-0-12-374270-4
3446:propagation delay
3436:Propagation delay
3307:Timing parameters
3297:
3296:
3104:
3091:
3074:
3016:
3015:
2899:{\displaystyle T}
2872:
2850:{\displaystyle Q}
2820:
2798:{\displaystyle Q}
2777:{\displaystyle T}
2715:
2702:
2673:
2577:
2576:
2381:
2380:
2266:
2265:
2087:D = 1, E = 1: set
2044:
2043:
2030:
2029:
1882:transparent latch
1860:
1859:
1846:
1845:
1745:Alternatively, a
1717:inverted SR latch
1630:
1629:
1520:
1519:
1438:
1437:
1420:
1419:
1383:= 1; not allowed
1259:
1238:
1184:
1169:
1139:
1121:
1106:
979:
978:
753:S = 1, R = 0: Set
525:
478:
342:{\displaystyle Q}
175:positive feedback
16:(Redirected from
5126:
4734:Sequential logic
4661:
4654:
4647:
4638:
4633:
4597:
4596:
4568:
4562:
4561:
4533:
4527:
4526:
4525:
4521:
4511:
4505:
4504:
4502:
4501:
4492:. Archived from
4486:
4480:
4479:
4455:
4441:
4416:
4410:
4409:
4369:
4363:
4362:
4344:
4335:
4334:
4316:
4307:
4302:
4296:
4291:
4285:
4284:
4282:
4281:
4272:. Archived from
4266:
4260:
4259:
4257:
4256:
4247:. Archived from
4241:
4235:
4234:
4208:
4188:
4179:
4178:
4158:
4149:
4148:
4136:
4130:
4129:
4123:
4119:
4117:
4109:
4099:
4083:
4077:
4076:
4058:
4049:
4048:
4028:
4022:
4021:
3999:
3993:
3987:
3981:
3980:
3960:
3954:
3953:
3952:
3948:
3938:
3932:
3931:
3911:
3905:
3904:
3894:
3888:
3887:
3867:
3861:
3860:
3840:
3834:
3833:
3799:
3793:
3792:
3776:
3766:
3760:
3757:
3743:
3736:The Radio Review
3725:
3706:
3700:
3699:
3698:
3694:
3687:
3681:
3680:
3662:
3653:
3644:
3638:
3637:
3617:
3611:
3600:
3551:
3547:
3501:Multi-level cell
3278:
3139:Excitation table
3130:
3118:
3116:
3115:
3110:
3105:
3097:
3092:
3084:
3076:
3075:
3072:
2905:
2903:
2902:
2897:
2884:
2882:
2881:
2876:
2874:
2873:
2870:
2856:
2854:
2853:
2848:
2832:
2830:
2829:
2824:
2822:
2821:
2818:
2804:
2802:
2801:
2796:
2783:
2781:
2780:
2775:
2759:Excitation table
2750:
2729:
2727:
2726:
2721:
2716:
2708:
2703:
2695:
2675:
2674:
2671:
2530:
2475:
2471:
2467:
2463:
2450:
2436:
2424:
2317:
2289:
2217:
2166:
2154:
2108:
2080:
2068:
2058:
2052:
1986:
1964:
1948:
1941:
1940:
1871:
1820:
1813:
1812:
1767:
1739:
1723:
1707:gates (on right)
1690:
1665:transparent-high
1623:
1553:
1535:De Morgan's laws
1474:
1431:
1382:
1365:
1360:
1355:
1353:latch operation
1352:
1345:
1344:
1337:
1333:
1322:
1310:
1303:
1301:
1300:
1295:
1274:
1272:
1271:
1266:
1261:
1260:
1252:
1240:
1239:
1236:
1214:
1212:
1211:
1206:
1186:
1185:
1177:
1171:
1170:
1167:
1154:
1152:
1151:
1146:
1141:
1140:
1132:
1123:
1122:
1114:
1108:
1107:
1104:
1045:
1006:
838:Excitation table
829:
816:
809:
802:
789:
721:
719:
718:
713:
711:
639:
527:
526:
518:
480:
479:
471:
348:
346:
345:
340:
328:
316:("toggle"), and
276:, and inverting
114:sequential logic
91:sequential logic
56:
48:
21:
5134:
5133:
5129:
5128:
5127:
5125:
5124:
5123:
5119:Computer memory
5109:Digital systems
5084:
5083:
5082:
5077:
5056:
4989:
4924:Place and route
4919:Logic synthesis
4905:
4901:Gate equivalent
4864:Logic synthesis
4859:Boolean algebra
4842:
4784:Macrocell array
4744:Boolean circuit
4670:
4665:
4627:
4617:Wayback Machine
4606:
4601:
4600:
4570:
4569:
4565:
4535:
4534:
4530:
4523:
4513:
4512:
4508:
4499:
4497:
4488:
4487:
4483:
4457:
4447:
4438:
4423:
4417:
4413:
4371:
4370:
4366:
4359:
4346:
4345:
4338:
4331:
4318:
4317:
4310:
4303:
4299:
4292:
4288:
4279:
4277:
4268:
4267:
4263:
4254:
4252:
4243:
4242:
4238:
4190:
4189:
4182:
4175:
4160:
4159:
4152:
4138:
4137:
4133:
4120:
4110:
4085:
4084:
4080:
4073:
4060:
4059:
4052:
4045:
4030:
4029:
4025:
4018:
4001:
4000:
3996:
3988:
3984:
3977:
3962:
3961:
3957:
3950:
3940:
3939:
3935:
3928:
3913:
3912:
3908:
3896:
3895:
3891:
3884:
3869:
3868:
3864:
3857:
3842:
3841:
3837:
3801:
3800:
3796:
3789:
3768:
3767:
3763:
3747:
3729:
3728:Reprinted in:
3718:The Electrician
3711:
3707:
3703:
3696:
3689:
3688:
3684:
3677:
3664:
3663:
3656:
3645:
3641:
3634:
3619:
3618:
3614:
3601:
3597:
3592:
3579:Schmitt trigger
3574:Sample and hold
3560:
3555:
3554:
3548:
3544:
3539:
3503:
3497:
3495:Generalizations
3490:
3486:
3482:
3478:
3474:
3470:
3459:
3455:
3451:
3443:
3438:
3423:
3415:
3394:
3388:
3309:
3304:
3276:
3166:
3157:
3067:
3062:
3061:
3035:
3028:
2888:
2887:
2865:
2860:
2859:
2839:
2838:
2813:
2808:
2807:
2787:
2786:
2766:
2765:
2730:(expanding the
2666:
2661:
2660:
2641:
2617:
2584:
2545:
2507:gated D latches
2483:
2473:
2469:
2465:
2461:
2448:
2444:
2443:
2442:
2441:
2440:
2437:
2429:
2428:
2425:
2416:
2415:
2409:
2398:shift registers
2315:
2229:
2203:zero-order hold
2190:
2183:
2182:
2167:
2158:
2155:
2123:
2116:
2109:
2100:
2099:
2081:
2072:
2069:
2060:
2056:
2053:
1989:
1984:
1981:
1962:
1925:two-phase clock
1914:level-sensitive
1869:
1865:
1804:level-sensitive
1781:closed (opaque)
1765:
1737:
1721:
1688:
1681:
1669:transparent-low
1653:non-transparent
1645:
1621:
1565:
1543:
1443:
1441:SR AND-OR latch
1429:
1380:
1363:
1358:
1350:
1335:
1331:
1320:
1313:
1308:
1277:
1276:
1231:
1226:
1225:
1162:
1157:
1156:
1099:
1094:
1093:
1044:(S, R) = (1, 1)
1043:
1004:
998:forbidden state
865:
853:
814:
807:
800:
787:
765:
731:
709:
708:
698:
675:
665:
641:
640:
628:
602:
592:
565:
564:
554:
528:
509:
482:
481:
462:
433:
423:
387:
386:
355:
331:
330:
327:
324:
321:
308:("set-reset"),
302:
247:
230:Hughes Aircraft
167:
54:
46:
35:
28:
23:
22:
15:
12:
11:
5:
5132:
5130:
5122:
5121:
5116:
5111:
5106:
5101:
5096:
5086:
5085:
5079:
5078:
5076:
5075:
5070:
5064:
5062:
5058:
5057:
5055:
5054:
5049:
5048:
5047:
5042:
5040:cinematography
5032:
5027:
5022:
5021:
5020:
5010:
5009:
5008:
4997:
4995:
4991:
4990:
4988:
4987:
4986:
4985:
4975:
4970:
4965:
4960:
4959:
4958:
4953:
4943:
4938:
4937:
4936:
4931:
4921:
4915:
4913:
4907:
4906:
4904:
4903:
4898:
4893:
4888:
4887:
4886:
4879:Digital signal
4876:
4871:
4866:
4861:
4856:
4854:Digital signal
4850:
4848:
4844:
4843:
4841:
4840:
4834:
4828:
4822:
4816:
4810:
4804:
4798:
4792:
4786:
4781:
4775:
4769:
4763:
4758:
4752:
4746:
4741:
4736:
4731:
4726:
4721:
4716:
4711:
4706:
4701:
4696:
4691:
4686:
4680:
4678:
4672:
4671:
4666:
4664:
4663:
4656:
4649:
4641:
4635:
4634:
4625:
4620:
4605:
4604:External links
4602:
4599:
4598:
4579:(3): 268–275.
4563:
4544:(3): 237–246.
4528:
4506:
4481:
4444:flip-flap-flop
4436:
4411:
4384:(4): 421–422.
4364:
4357:
4336:
4329:
4308:
4297:
4286:
4261:
4236:
4206:10.1.1.99.2773
4180:
4173:
4150:
4147:(10): 909–910.
4131:
4122:|journal=
4078:
4071:
4050:
4043:
4023:
4016:
3994:
3982:
3975:
3955:
3933:
3926:
3906:
3889:
3882:
3862:
3855:
3835:
3794:
3787:
3761:
3759:
3758:
3744:
3726:
3701:
3682:
3675:
3654:
3639:
3632:
3612:
3594:
3593:
3591:
3588:
3587:
3586:
3581:
3576:
3571:
3566:
3564:Latching relay
3559:
3556:
3553:
3552:
3541:
3540:
3538:
3535:
3522:(respectively
3512:flip-flap-flop
3496:
3493:
3488:
3487: + t
3484:
3480:
3476:
3472:
3468:
3465:shift register
3457:
3453:
3449:
3441:
3437:
3434:
3421:
3413:
3390:Main article:
3387:
3384:
3308:
3305:
3303:
3300:
3299:
3298:
3295:
3294:
3291:
3288:
3285:
3282:
3279:
3274:
3271:
3268:
3264:
3263:
3260:
3257:
3254:
3251:
3248:
3245:
3242:
3239:
3235:
3234:
3231:
3228:
3225:
3222:
3219:
3216:
3213:
3210:
3206:
3205:
3202:
3199:
3196:
3193:
3190:
3187:
3184:
3181:
3177:
3176:
3173:
3170:
3167:
3164:
3161:
3158:
3155:
3152:
3149:
3146:
3142:
3141:
3136:
3120:
3119:
3108:
3103:
3100:
3095:
3090:
3087:
3082:
3079:
3070:
3034:
3031:
3026:
3018:
3017:
3014:
3013:
3010:
3007:
3004:
3001:
2998:
2995:
2992:
2988:
2987:
2984:
2981:
2978:
2975:
2972:
2969:
2966:
2962:
2961:
2958:
2955:
2952:
2949:
2946:
2943:
2940:
2936:
2935:
2932:
2929:
2926:
2923:
2920:
2917:
2914:
2910:
2909:
2906:
2895:
2885:
2868:
2857:
2846:
2836:
2833:
2816:
2805:
2794:
2784:
2773:
2762:
2761:
2756:
2736:
2735:
2719:
2714:
2711:
2706:
2701:
2698:
2693:
2690:
2687:
2684:
2681:
2678:
2669:
2640:
2637:
2616:
2613:
2583:
2580:
2579:
2578:
2575:
2574:
2571:
2568:
2565:
2561:
2560:
2557:
2554:
2551:
2547:
2546:
2543:
2540:
2537:
2534:
2482:
2479:
2438:
2431:
2430:
2426:
2419:
2418:
2417:
2413:
2412:
2411:
2410:
2408:
2405:
2383:
2382:
2379:
2378:
2375:
2372:
2369:
2366:
2363:
2359:
2358:
2355:
2352:
2349:
2346:
2343:
2339:
2338:
2335:
2332:
2329:
2326:
2323:
2319:
2318:
2313:
2310:
2307:
2304:
2301:
2297:
2296:
2293:
2268:
2267:
2264:
2263:
2260:
2257:
2253:
2252:
2249:
2246:
2242:
2241:
2238:
2235:
2231:
2230:
2227:
2224:
2221:
2189:
2186:
2185:
2184:
2181:
2180:
2177:
2174:
2170:
2168:
2161:
2159:
2156:
2149:
2122:
2119:
2118:
2117:
2110:
2103:
2101:
2098:
2097:
2094:
2091:
2088:
2084:
2082:
2075:
2073:
2070:
2063:
2061:
2054:
2047:
2042:
2041:
2031:
2028:
2027:
2024:
2021:
2018:
2015:
2011:
2010:
2007:
2004:
2001:
1998:
1994:
1993:
1990:
1987:
1982:
1979:
1976:
1973:
1969:
1968:
1965:
1960:
1957:
1955:
1952:
1864:
1861:
1858:
1857:
1847:
1844:
1843:
1840:
1836:
1835:
1832:
1828:
1827:
1824:
1808:edge-sensitive
1747:gated SR latch
1728:gated SR latch
1713:gated SR latch
1680:
1679:Gated SR latch
1677:
1644:
1641:
1632:
1631:
1628:
1627:
1624:
1619:
1616:
1612:
1611:
1608:
1605:
1602:
1598:
1597:
1594:
1591:
1588:
1584:
1583:
1580:
1577:
1574:
1570:
1569:
1566:
1563:
1560:
1557:
1542:
1539:
1522:
1521:
1518:
1517:
1514:
1511:
1507:
1506:
1503:
1500:
1496:
1495:
1492:
1489:
1485:
1484:
1481:
1478:
1458:gate with one
1442:
1439:
1436:
1435:
1428:Symbol for an
1421:
1418:
1417:
1414:
1411:
1407:
1406:
1403:
1400:
1396:
1395:
1392:
1389:
1385:
1384:
1377:
1374:
1370:
1369:
1366:
1361:
1312:
1306:
1305:
1304:
1293:
1290:
1287:
1284:
1264:
1258:
1255:
1249:
1246:
1243:
1234:
1216:
1215:
1204:
1201:
1198:
1195:
1192:
1189:
1183:
1180:
1174:
1165:
1144:
1138:
1135:
1129:
1126:
1120:
1117:
1111:
1102:
1076:
1075:
1061:
1060:
1054:
1029:race condition
1013:simultaneously
984:Note: X means
981:
980:
977:
976:
973:
970:
967:
964:
961:
958:
955:
951:
950:
947:
944:
941:
938:
935:
932:
929:
925:
924:
921:
918:
915:
912:
909:
906:
903:
899:
898:
895:
892:
889:
886:
883:
880:
877:
873:
872:
869:
866:
863:
860:
857:
854:
851:
848:
845:
841:
840:
835:
822:
821:
818:
811:
804:
764:
763:
760:
757:
754:
750:
730:
727:
723:
722:
707:
704:
701:
699:
697:
694:
691:
688:
685:
682:
679:
676:
674:
671:
668:
666:
664:
661:
658:
655:
652:
649:
646:
643:
642:
638:
634:
631:
629:
627:
624:
621:
618:
615:
612:
609:
606:
603:
601:
598:
595:
593:
591:
588:
585:
582:
579:
576:
573:
570:
567:
566:
563:
560:
557:
555:
553:
550:
547:
544:
541:
538:
535:
532:
529:
524:
521:
515:
512:
510:
508:
505:
502:
499:
496:
493:
490:
487:
484:
483:
477:
474:
468:
465:
463:
461:
458:
455:
452:
449:
446:
443:
440:
437:
434:
432:
429:
426:
424:
422:
419:
416:
413:
410:
407:
404:
401:
398:
395:
394:
354:
351:
338:
325:
322:
301:
298:
246:
245:Implementation
243:
211:multivibrators
183:William Eccles
166:
163:
26:
24:
14:
13:
10:
9:
6:
4:
3:
2:
5131:
5120:
5117:
5115:
5112:
5110:
5107:
5105:
5102:
5100:
5097:
5095:
5092:
5091:
5089:
5074:
5071:
5069:
5068:Metastability
5066:
5065:
5063:
5061:Design issues
5059:
5053:
5050:
5046:
5043:
5041:
5038:
5037:
5036:
5035:Digital video
5033:
5031:
5028:
5026:
5023:
5019:
5016:
5015:
5014:
5013:Digital audio
5011:
5007:
5004:
5003:
5002:
4999:
4998:
4996:
4992:
4984:
4981:
4980:
4979:
4976:
4974:
4971:
4969:
4966:
4964:
4961:
4957:
4954:
4952:
4949:
4948:
4947:
4944:
4942:
4939:
4935:
4932:
4930:
4927:
4926:
4925:
4922:
4920:
4917:
4916:
4914:
4912:
4908:
4902:
4899:
4897:
4894:
4892:
4889:
4885:
4882:
4881:
4880:
4877:
4875:
4872:
4870:
4867:
4865:
4862:
4860:
4857:
4855:
4852:
4851:
4849:
4845:
4838:
4835:
4832:
4829:
4826:
4823:
4820:
4817:
4814:
4811:
4808:
4805:
4802:
4799:
4796:
4793:
4790:
4787:
4785:
4782:
4779:
4776:
4773:
4770:
4767:
4764:
4762:
4759:
4756:
4753:
4750:
4747:
4745:
4742:
4740:
4737:
4735:
4732:
4730:
4727:
4725:
4722:
4720:
4717:
4715:
4712:
4710:
4707:
4705:
4702:
4700:
4697:
4695:
4692:
4690:
4687:
4685:
4682:
4681:
4679:
4677:
4673:
4669:
4662:
4657:
4655:
4650:
4648:
4643:
4642:
4639:
4631:
4626:
4624:
4621:
4618:
4614:
4611:
4608:
4607:
4603:
4594:
4590:
4586:
4582:
4578:
4574:
4567:
4564:
4559:
4555:
4551:
4547:
4543:
4539:
4532:
4529:
4520:
4516:
4510:
4507:
4496:on 2009-01-05
4495:
4491:
4485:
4482:
4477:
4473:
4469:
4465:
4461:
4453:
4452:
4445:
4439:
4433:
4429:
4428:
4421:
4415:
4412:
4407:
4403:
4399:
4395:
4391:
4387:
4383:
4379:
4375:
4368:
4365:
4360:
4354:
4350:
4343:
4341:
4337:
4332:
4330:0-13-191165-1
4326:
4322:
4315:
4313:
4309:
4306:
4301:
4298:
4295:
4290:
4287:
4276:on 2013-09-08
4275:
4271:
4265:
4262:
4251:on 2014-02-23
4250:
4246:
4240:
4237:
4232:
4228:
4224:
4220:
4216:
4212:
4207:
4202:
4198:
4194:
4187:
4185:
4181:
4176:
4170:
4166:
4165:
4157:
4155:
4151:
4146:
4142:
4135:
4132:
4127:
4115:
4107:
4103:
4098:
4093:
4089:
4082:
4079:
4074:
4072:0-07-035237-2
4068:
4064:
4057:
4055:
4051:
4046:
4040:
4036:
4035:
4027:
4024:
4019:
4017:9783540264101
4013:
4009:
4005:
3998:
3995:
3991:
3986:
3983:
3978:
3972:
3968:
3967:
3959:
3956:
3947:
3943:
3937:
3934:
3929:
3927:9780608102658
3923:
3919:
3918:
3910:
3907:
3902:
3901:
3893:
3890:
3885:
3879:
3875:
3874:
3866:
3863:
3858:
3852:
3848:
3847:
3839:
3836:
3832:
3828:
3824:
3820:
3816:
3812:
3808:
3804:
3798:
3795:
3790:
3784:
3780:
3775:
3774:
3765:
3762:
3755:
3751:
3746:Summary in:
3745:
3741:
3737:
3733:
3727:
3723:
3719:
3715:
3710:
3709:
3705:
3702:
3692:
3686:
3683:
3678:
3676:9780534954727
3672:
3668:
3661:
3659:
3655:
3652:
3648:
3643:
3640:
3635:
3629:
3625:
3624:
3616:
3613:
3609:
3605:
3602:For example,
3599:
3596:
3589:
3585:
3582:
3580:
3577:
3575:
3572:
3570:
3567:
3565:
3562:
3561:
3557:
3546:
3543:
3536:
3534:
3532:
3527:
3525:
3521:
3515:
3513:
3509:
3508:ternary logic
3502:
3494:
3492:
3466:
3461:
3447:
3435:
3433:
3429:
3425:
3419:
3411:
3406:
3403:
3399:
3398:metastability
3393:
3386:Metastability
3385:
3383:
3379:
3375:
3371:
3369:
3365:
3361:
3359:
3355:
3354:Recovery time
3351:
3349:
3345:
3343:
3339:
3335:
3333:
3329:
3325:
3323:
3313:
3306:
3301:
3292:
3289:
3286:
3283:
3280:
3275:
3272:
3269:
3266:
3265:
3261:
3258:
3255:
3252:
3249:
3246:
3243:
3240:
3237:
3236:
3232:
3229:
3226:
3223:
3220:
3217:
3214:
3211:
3208:
3207:
3203:
3200:
3197:
3194:
3191:
3188:
3185:
3182:
3179:
3178:
3174:
3171:
3168:
3162:
3159:
3153:
3150:
3147:
3144:
3143:
3140:
3135:
3131:
3125:
3124:
3123:
3106:
3098:
3093:
3085:
3080:
3077:
3068:
3060:
3059:
3058:
3055:
3047:
3039:
3032:
3030:
3024:
3011:
3008:
3005:
3002:
2999:
2996:
2993:
2990:
2989:
2985:
2982:
2979:
2976:
2973:
2970:
2967:
2964:
2963:
2959:
2956:
2953:
2950:
2947:
2944:
2941:
2938:
2937:
2933:
2930:
2927:
2924:
2921:
2918:
2915:
2912:
2911:
2907:
2893:
2886:
2866:
2858:
2844:
2837:
2834:
2814:
2806:
2792:
2785:
2771:
2764:
2763:
2760:
2755:
2751:
2745:
2744:
2743:
2741:
2733:
2717:
2709:
2704:
2696:
2691:
2688:
2685:
2682:
2679:
2676:
2667:
2659:
2658:
2657:
2655:
2645:
2638:
2636:
2634:
2633:dynamic logic
2629:
2621:
2614:
2608:
2600:
2596:
2588:
2581:
2572:
2569:
2566:
2563:
2562:
2558:
2555:
2552:
2549:
2548:
2541:
2538:
2535:
2532:
2531:
2528:
2527:
2526:
2524:
2519:
2515:
2512:
2508:
2499:
2492:
2487:
2480:
2478:
2459:
2458:gated D latch
2454:
2452:
2435:
2423:
2406:
2404:
2401:
2399:
2392:
2387:
2376:
2373:
2370:
2367:
2364:
2361:
2360:
2356:
2353:
2350:
2347:
2344:
2341:
2340:
2336:
2333:
2330:
2327:
2324:
2321:
2320:
2314:
2311:
2308:
2305:
2302:
2299:
2298:
2290:
2287:
2286:
2285:
2281:
2279:
2278:
2273:
2261:
2258:
2255:
2254:
2250:
2247:
2244:
2243:
2239:
2236:
2233:
2232:
2225:
2222:
2219:
2218:
2215:
2214:
2213:
2212:Truth table:
2210:
2208:
2204:
2194:
2187:
2178:
2175:
2172:
2171:
2165:
2160:
2153:
2148:
2146:
2144:
2140:
2135:
2133:
2127:
2120:
2114:
2107:
2102:
2095:
2092:
2089:
2086:
2085:
2079:
2074:
2067:
2062:
2051:
2046:
2036:
2032:
2025:
2022:
2019:
2016:
2013:
2012:
2008:
2005:
2002:
1999:
1996:
1995:
1991:
1983:
1977:
1974:
1971:
1970:
1949:
1943:
1942:
1939:
1937:
1933:
1928:
1926:
1922:
1917:
1915:
1911:
1907:
1903:
1899:
1896:input and an
1895:
1891:
1887:
1883:
1879:
1875:
1863:Gated D latch
1862:
1852:
1848:
1841:
1838:
1837:
1833:
1830:
1829:
1825:
1821:
1815:
1814:
1811:
1809:
1805:
1801:
1797:
1793:
1789:
1784:
1782:
1778:
1773:
1771:
1763:
1759:
1756:With E high (
1754:
1752:
1748:
1743:
1741:
1733:
1729:
1725:
1718:
1714:
1706:
1702:
1697:
1685:
1678:
1676:
1674:
1670:
1666:
1662:
1658:
1654:
1650:
1642:
1640:
1637:
1625:
1620:
1617:
1614:
1613:
1609:
1606:
1603:
1600:
1599:
1595:
1592:
1589:
1586:
1585:
1581:
1578:
1575:
1572:
1571:
1567:
1561:
1558:
1555:
1554:
1548:
1547:
1546:
1540:
1538:
1536:
1530:
1526:
1515:
1512:
1509:
1508:
1504:
1501:
1498:
1497:
1493:
1490:
1487:
1486:
1482:
1479:
1476:
1475:
1469:
1468:
1467:
1465:
1462:input and an
1461:
1457:
1447:
1440:
1426:
1422:
1415:
1412:
1409:
1408:
1404:
1401:
1398:
1397:
1393:
1390:
1387:
1386:
1378:
1375:
1372:
1371:
1367:
1362:
1357:
1356:
1347:
1346:
1343:
1339:
1326:
1317:
1307:
1291:
1288:
1285:
1282:
1262:
1253:
1247:
1244:
1241:
1232:
1224:
1223:
1222:
1219:
1202:
1196:
1193:
1190:
1178:
1172:
1163:
1142:
1133:
1127:
1124:
1115:
1109:
1100:
1092:
1091:
1090:
1087:
1085:
1081:
1074:
1070:
1069:
1068:
1066:
1059:
1055:
1053:
1049:
1048:
1047:
1036:
1032:
1030:
1026:
1022:
1018:
1014:
1010:
1003:
999:
995:
990:
989:
985:
974:
971:
968:
965:
962:
959:
956:
953:
952:
948:
945:
942:
939:
936:
933:
930:
927:
926:
922:
919:
916:
913:
910:
907:
904:
901:
900:
896:
893:
890:
887:
884:
881:
878:
875:
874:
870:
867:
861:
858:
855:
849:
846:
843:
842:
839:
834:
830:
824:
823:
819:
812:
805:
797:
796:
795:
791:
784:
780:
776:
774:
761:
758:
755:
752:
751:
747:
740:
735:
728:
726:
705:
702:
700:
692:
689:
686:
680:
677:
672:
669:
667:
659:
656:
653:
647:
644:
636:
632:
630:
622:
619:
616:
610:
607:
604:
599:
596:
594:
586:
583:
580:
574:
571:
568:
561:
558:
556:
548:
545:
542:
536:
533:
530:
519:
513:
511:
503:
500:
497:
491:
488:
485:
472:
466:
464:
456:
453:
450:
444:
441:
438:
435:
430:
427:
425:
417:
414:
411:
405:
402:
399:
396:
385:
384:
383:
379:
377:
374:
370:
365:
362:
360:
352:
350:
336:
319:
315:
311:
307:
299:
297:
295:
289:
287:
281:
279:
275:
271:
267:
263:
256:
251:
244:
242:
240:
237:-input" and "
236:
231:
227:
223:
219:
214:
212:
208:
204:
200:
196:
192:
188:
184:
176:
171:
164:
162:
160:
156:
152:
147:
144:
142:
138:
134:
130:
126:
121:
119:
115:
111:
110:
105:
104:
98:
96:
92:
88:
84:
80:
76:
72:
68:
64:
52:
44:
39:
33:
19:
4994:Applications
4718:
4576:
4572:
4566:
4541:
4537:
4531:
4509:
4498:. Retrieved
4494:the original
4484:
4467:
4463:
4450:
4443:
4442:), the term
4426:
4422:(1969) (see
4414:
4381:
4377:
4367:
4348:
4320:
4300:
4289:
4278:. Retrieved
4274:the original
4264:
4253:. Retrieved
4249:the original
4239:
4196:
4192:
4163:
4144:
4140:
4134:
4087:
4081:
4062:
4033:
4026:
4007:
3997:
3985:
3965:
3958:
3936:
3916:
3909:
3898:
3892:
3872:
3865:
3845:
3838:
3814:
3810:
3797:
3772:
3764:
3753:
3739:
3735:
3721:
3717:
3704:
3685:
3666:
3650:
3642:
3622:
3615:
3598:
3545:
3528:
3523:
3516:
3511:
3504:
3462:
3439:
3430:
3426:
3417:
3409:
3407:
3395:
3380:
3376:
3372:
3367:
3364:Removal time
3363:
3362:
3357:
3353:
3352:
3347:
3346:
3341:
3337:
3336:
3331:
3327:
3326:
3321:
3318:
3121:
3056:
3052:
3033:JK flip-flop
3019:
2737:
2650:
2630:
2626:
2593:
2523:falling edge
2522:
2520:
2516:
2510:
2504:
2490:
2455:
2451:NAND latches
2445:
2402:
2395:
2282:
2275:
2271:
2269:
2211:
2199:
2143:logic hazard
2138:
2136:
2128:
2124:
1935:
1931:
1929:
1918:
1913:
1909:
1908:). The word
1905:
1901:
1897:
1893:
1889:
1888:, or simply
1885:
1881:
1877:
1873:
1866:
1807:
1803:
1800:clock signal
1795:
1792:write strobe
1791:
1787:
1785:
1780:
1776:
1775:With E low (
1774:
1769:
1761:
1757:
1755:
1750:
1746:
1744:
1735:
1731:
1727:
1720:
1716:
1712:
1710:
1672:
1668:
1664:
1660:
1656:
1652:
1649:transparent.
1648:
1646:
1635:
1633:
1544:
1531:
1527:
1523:
1452:
1340:
1329:
1220:
1217:
1088:
1079:
1077:
1072:
1062:
1057:
1051:
1041:
1020:
1016:
1012:
1008:
1001:
997:
993:
991:
987:
983:
982:
963:Not allowed
792:
782:
778:
777:, or simply
771:
769:
729:SR NOR latch
724:
380:
366:
363:
358:
356:
317:
313:
309:
305:
303:
290:
282:
262:vacuum tubes
259:
238:
234:
225:
215:
195:vacuum tubes
190:
187:F. W. Jordan
180:
148:
145:
140:
136:
122:
107:
101:
99:
70:
66:
60:
50:
42:
41:A SR latch (
5114:Logic gates
4724:Memory cell
3742:(3): 143–6.
3012:Complement
2986:Complement
2740:truth table
2639:T flip-flop
2245:Rising edge
2234:Rising edge
2188:D flip-flop
2121:Earle latch
1923:that use a
1910:transparent
1892:. It has a
1890:gated latch
1798:input is a
1794:. When the
1786:A periodic
1770:transparent
1687:NAND Gated
1667:latch by a
1661:transparent
885:Hold state
376:logic gates
278:logic gates
207:logic gates
159:7400 series
125:synchronous
63:electronics
5088:Categories
5073:Runt pulse
5045:television
4739:Logic gate
4684:Transistor
4676:Components
4515:US 6975152
4500:2009-10-17
4456:, and in
4280:2011-12-15
4255:2016-06-05
3942:US 2850566
3817:(3): 249,
3590:References
3499:See also:
3416:) and the
3410:setup time
3328:Setup time
3186:Hold state
2960:No change
2934:No change
2277:don't care
2274:denotes a
2256:Non-rising
2207:delay line
2059:NAND latch
1992:No change
1886:data latch
1726:becomes a
1582:No change
1432:NAND latch
1325:NAND gates
1311:NAND latch
1025:metastable
1017:restricted
986:don't care
312:("data"),
67:flip-flops
4929:Placement
4719:Flip-flop
4699:Capacitor
4420:Don Knuth
4398:0018-9340
4223:0163-5964
4201:CiteSeerX
4124:ignored (
4114:cite book
3691:GB 148582
3418:hold time
3338:Hold time
3287:No change
3198:No change
3102:¯
3089:¯
2734:operator)
2713:¯
2700:¯
2683:⊕
1257:¯
1182:¯
1137:¯
1119:¯
779:feedbacks
739:NOR gates
523:¯
476:¯
274:inverters
137:flip-flop
32:Flip-flop
4694:Inductor
4689:Resistor
4613:Archived
4593:61275953
4558:34323423
4406:12594672
4106:15955626
3831:39816473
3805:(1983),
3610:page 44)
3558:See also
3524:one-cold
3402:computer
3348:Aperture
3322:aperture
3027:previous
3023:counters
2908:Comment
2835:Comment
2654:equation
2295:Outputs
1967:Comment
1751:SR latch
1732:SR latch
1568:Comment
1541:JK latch
1460:inverted
1084:JK latch
773:feedback
294:drawings
75:circuits
4934:Routing
4768:(3D IC)
4231:2733845
3520:one-hot
3169:Comment
3151:Comment
3000:Toggle
2974:Toggle
2595:gates.
2570:Falling
2556:Falling
2205:, or a
1906:control
1826:Action
1626:Toggle
1483:Action
1379:Q = 1,
1368:Action
1073:E-latch
856:Action
783:control
165:History
141:latches
129:clocked
83:signals
71:latches
4911:Design
4847:Theory
4833:(ASIC)
4827:(FPOA)
4821:(FPGA)
4815:(CPLD)
4780:(EPLD)
4591:
4556:
4524:
4434:
4404:
4396:
4355:
4327:
4229:
4221:
4203:
4171:
4104:
4069:
4041:
4014:
3973:
3951:
3924:
3880:
3853:
3829:
3785:
3724:: 298.
3697:
3673:
3630:
3358:before
3332:before
3273:Toggle
2511:enable
2491:enable
2389:4-bit
2292:Inputs
2009:Reset
1934:nable/
1898:enable
1874:enable
1796:enable
1788:enable
1777:enable
1758:enable
1736:gated
1657:opaque
1636:toggle
1596:Reset
1516:Q = 0
1505:Q = 1
1405:Q = 0
1394:Q = 1
1080:toggle
911:Reset
775:inputs
155:74HC75
55:
51:R3, R4
47:
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