459:, the CP1600 used only 10. The remaining 6 bits were marked "Future Use." The 10-bit instructions meant that code stored in a typical byte-oriented ROM would waste six bits per instruction. In the era of expensive memory, this was a significant issue. To address this, General Instrument also produced special 10-bit ROMs that efficiently stored the instructions. As data and addresses would still require 16-bit values, the 1600 included a special SDBD instruction that pieced together a 16-bit argument from two 10-bit ROM reads.
17:
115:(DIP) chip design, the CP1600 multiplexed its data and address pins. This allowed a set of 16 pins to be used for both address selection and reading and writing data, but to do so required two bus cycles. It also complicated the overall machine layout as buffers were required on the memory bus to latch the address while the processor switched the pins to data mode. The interface to the system was likewise complex, requiring three pins,
108:(5 V) compatible. Each microstate or processor cycle uses four internal time slots generated by two non-overlapping clocks. A 3.3 MHz two-phase clock produces a 600 nanosecond microcycle. A 5 MHz two-phase clock produces a 400 nanosecond microcycle. Due to the voltage requirements of the clock signals, these had to be generated with external circuitry, as was common in this era of microprocessor design.
481:, although they were not truly general-purpose as in modern designs. Only R0 had no pre-defined purpose and has been described as "the primary accumulator". R1 through R3 could be used data pointers, generally used for register-based addressing ("implied addressing"). R4 and R5 auto-incremented after being accessed, which made them useful for looping over collections of data.
488:, R7 the program counter. Since both of these registers were visible to the programmer, they could be used to implement multiple stacks, or support more complex branching, among other things. There were no implicit stack instructions; when R6 was used in a "read" operation it decremented the address and then returned the data being pointed at, simulating a
90:
190:
In total, implementing a system using the CP1600 often required additional support chips and logic. This included a system to multiplex sixteen signals into a single pin if the external branching was being used, and a three-bit-to-eight-line converter to avoid having to decode the bus status signals
512:
systems. The use of a multiplexed bus and multi-state bus status made implementing I/O more difficult than would normally be the case on memory-mapped systems. This meant that implementations had to use latches or buffers to be able to interface with the CPU as it changed the bus from indicating an
469:
The system included 87 basic instructions. Instructions might be one to three 16-bit words long depending on the addressing format being used. The CP1600 did not support memory-memory indirect addressing (offsets), and looping was implemented using a dedicated adder that performed single-cycle
516:
To address this problem, GI supplied a series of 164x dedicated I/O chips that implemented the required bus logic. These included, for instance, the 1641 keyboard controller, the 1643 cassette tape controller, and the 1647 display control. Most famous among these is the 1640
147:
pin, and the state of this pin would then determine whether the branch was taken or not. This could be used, for instance, to test whether an external device had input data that needed to be processed; the processor could express the value "2" on the
142:
instruction opcode. When this instruction is performed, the pins are activated and are used to indicate which of up to sixteen external systems should be sampled. Those devices would then respond to the query by setting
533:
card to read data from a given sector on the disk. The PIC would then read the data into its own internal buffer, watch the bus for unused time when the bus status pins were all zero, and then send data to main memory.
561:
Intellivisions uses a 1.7897725 MHz two-phase clock. Although users of the CP1600 in the traditional computer role were relatively rare, over 3 million
Intellivisions were produced from 1980 until the
72:. The system saw little other use due to General Instrument's marketing philosophy of seeking out customers only with very large orders and ignoring smaller customers. They also did not pursue a
171:, which then reads additional data to determine which device called the interrupt. This additional data may be presented using dedicated pins on the CPU, but is often presented as a value on the
466:
line which stalled the CPU until released. Early documentation shows two planned chips in the series, the 1616 which added the "Extended
Instruction Set", and the 1618 "Priority Expander".
577:
were available that limited interest in a 16-bit design like the CP1600, and their main existing customer, the
Intellivision, was no longer in production. Many other products were also
525:
for the CPU. As with the other 1640 series chips, the PIC internally decoded the bus logic, but also added a very simple processor that could run its own programs to perform I/O and
839:
557:, is a compatible member of the 1600 microprocessor family. It uses a 2 MHz two-phase clock producing a 1 microsecond processor cycle. The CP1610 in the
474:(ALU) was 16-bit wide and could add two 16-bit internal registers in 2.4 microseconds, and memory to register adds of 16-bit numbers in 3.2 microseconds.
643:
Encyclopedia of
Computer Science and Technology: Volume 10 - Linear and Matrix Algebra to Microorganisms: Computer-Assisted Identification
47:, introduced in February 1975. It is one of the first single-chip 16-bit processors. The overall design bears a strong resemblance to the
777:
886:
655:
105:
944:
98:
896:
796:
705:
179:
to call to process the data. The CP1600 can implement this in fewer instructions; the interrupt handler is simply a series of
130:
A relatively uncommon feature of the CP1600 was its "external branch" concept. This was implemented as four pins on the chip,
851:
550:
183:
instructions pointing at the associated drivers which it runs through one at a time until the device in question sets the
626:
598:
58:
569:
Production of the CP1600 ended in 1985 when
General Instrument spun off its microelectronics division to create
513:
address to data. This both negatively affected I/O performance and increased the complexity of the I/O devices.
563:
76:
arrangement, which in the early days of microprocessor designs was a requirement for most potential customers.
876:
939:
160:
to true if there was data, causing the processor to jump into the code to read the data from that device.
578:
471:
601:, for instance, which output 12V signals and required extensive interfacing to use with TTL components.
537:
General
Instrument provided cross-assemblers and simulators/debuggers compatible with 16-bit or larger
163:
This contrasts with the typical solution for handling external devices; most systems have the devices
570:
526:
518:
112:
492:, and when it was used in a "write" it would write then post-increment (like R4/R5), simulating a
934:
522:
478:
69:
40:
104:
and required +12, +5, and ā3 V power supplies; I/O connections except for the clocks were
882:
651:
641:
505:
168:
16:
919:
915:
574:
485:
36:
764:
928:
554:
428:
176:
73:
66:
21:
538:
541:. GI also provided a standalone CP1600 based microcomputer system in the GIC1600.
530:
433:
521:, or PIC, which was designed to work in concert with the CP1600 and act as a
462:
The unused 6 bits were intended to be used with co-processors, asserting the
647:
423:
418:
164:
54:
44:
24:
video game console was the only widespread application of the CP1600 family.
815:
127:, which had to be decoded to understand what state the memory bus was in.
172:
89:
456:
101:
48:
33:
627:"General Instrument's microprocessor aimed at minicomputer market"
566:
led to the closing of the
Intellivision production lines in 1984.
509:
88:
15:
558:
477:
Like the PDP-11, the CP1600 used eight 16-bit "general purpose"
847:
713:(S16DOC-CP 1600 -04 ed.). General Instruments. May 1975
529:. For instance, one might send an instruction to a PIC on a
688:
686:
684:
732:
730:
728:
581:
at the same time, and their primary product was the PIC.
61:
and related systems, but its most widespread use was the
671:
669:
667:
640:
Belzer, Jack; Holzman, Albert G.; Kent, Allen (1978).
167:
which causes the processor to call special code, the
573:. By this point a number of 32-bit designs like the
463:
184:
180:
157:
153:
149:
144:
139:
135:
131:
124:
120:
116:
508:, as opposed to separate I/O pins as seen on the
111:In order to fit a 16-bit processor into a 40-pin
175:. The interrupt handler code then decides which
156:, and that device would then respond by setting
779:CP-1600 Cross Assembler Simulator Users Manual
549:The CP1610, used in game consoles such as the
8:
187:and automatically cause the code to branch.
504:As was common for the era, the CP1600 used
455:Of the 16-bits available in an instruction
748:
736:
692:
759:
757:
138:, which held the lower four bits of the
675:
618:
590:
878:Osborne 16-Bit Microprocessor Handbook
198:
804:. General Instrument. September 1975.
7:
785:. General Instrument. November 1974.
470:changes to addresses in memory. The
707:CP-1600 Microprocessor Users Manual
519:"Programmable Interface Controller"
840:"Mattel Intellivision - 1980-1984"
798:GIC1600 Microcomputer Users Manual
14:
898:Series 1600 Microprocessor System
39:created in a partnership between
57:used the CP1600 in a number of
97:The CP1600 was implemented in
1:
195:Instruction set and registers
152:to sample device 2, call the
765:"General Instruments CP1600"
904:. General Instrument. 1975.
599:National Semiconductor PACE
961:
414:
407:
388:
369:
365:egister 5 / Autoincrement
358:
354:egister 4 / Autoincrement
347:
336:
325:
314:
303:
295:
59:process control computers
564:video game crash of 1983
881:. Osborne/McGraw-Hill.
816:"Champion 2711 |Pre-83"
85:Physical implementation
945:16-bit microprocessors
94:
25:
553:and most notably the
472:arithmetic logic unit
343:egister 3 / Indirect
332:egister 2 / Indirect
321:egister 1 / Indirect
92:
19:
571:Microchip Technology
527:direct memory access
113:dual in-line package
597:In contrast to the
479:processor registers
201:
191:in external parts.
920:Intellivision Wiki
523:channel controller
310:egister 0 / Accum
199:
165:raise an interrupt
95:
70:video game console
41:General Instrument
26:
506:memory-mapped I/O
453:
452:
449:
448:
200:CP1600 registers
169:interrupt handler
952:
905:
903:
892:
875:Osborne (1981).
863:
862:
860:
859:
850:. Archived from
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830:
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99:enhancement mode
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763:Lowell Turner,
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749:Series1600 1975
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737:Series1600 1975
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726:
716:
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710:
704:
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699:
693:Series1600 1975
691:
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658:
650:. p. 402.
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629:. January 2000.
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65:version in the
12:
11:
5:
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956:
948:
947:
942:
937:
927:
926:
923:
922:
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910:External links
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807:
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767:, 10 July 2001
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678:, p. 2.1.
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297:Main registers
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290:(bit position)
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37:microprocessor
13:
10:
9:
6:
4:
3:
2:
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940:Intellivision
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888:0-931988-43-8
884:
880:
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873:
872:
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854:on 2008-06-23
853:
849:
845:
844:ClassicGaming
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657:9780824722609
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555:Intellivision
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551:Champion 2711
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539:minicomputers
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100:
93:CP1600 pinout
91:
84:
79:
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74:second source
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67:Intellivision
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50:
46:
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31:
23:
22:Intellivision
18:
897:
877:
869:Bibliography
856:. Retrieved
852:the original
843:
834:
823:. Retrieved
819:
810:
797:
791:
778:
772:
744:
739:, p. i.
715:. Retrieved
706:
700:
676:Osborne 1981
642:
635:
621:
593:
579:end-of-lifed
568:
548:
536:
515:
503:
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476:
468:
461:
454:
442:
438:
409:Status flags
408:
400:
396:
395:egister 7 /
392:
381:
377:
376:egister 6 /
373:
362:
351:
340:
329:
318:
307:
296:
289:
189:
162:
129:
110:
96:
62:
53:
29:
27:
531:floppy disk
484:R6 was the
80:Description
929:Categories
858:2008-05-16
825:2022-05-23
609:References
935:Honeywell
820:pre83.com
648:CRC Press
614:Citations
55:Honeywell
45:Honeywell
916:"CP1610"
389:R7 / PC
370:R6 / SP
173:data bus
134:through
918:at the
575:MC68000
415:
403:ounter
399:rogram
384:ointer
885:
717:5 July
695:, 2.1.
654:
457:opcode
441:tatus
63:CP1610
49:PDP-11
34:16-bit
30:CP1600
902:(PDF)
802:(PDF)
783:(PDF)
711:(PDF)
585:Notes
510:Intel
445:lags
380:tack
136:EBCA3
132:EBCA0
32:is a
883:ISBN
719:2022
652:ISBN
559:NTSC
545:Uses
494:PUSH
464:PCIT
185:EBCI
181:BEXT
158:EBCI
154:BEXT
150:EBCA
145:EBCI
140:BEXT
123:and
117:BDIR
102:nMOS
43:and
28:The
20:The
848:IGN
500:I/O
490:POP
359:R5
348:R4
337:R3
326:R2
315:R1
304:R0
125:BC2
121:BC1
106:TTL
931::
846:.
842:.
818:.
756:^
727:^
683:^
666:^
646:.
496:.
429:OV
119:,
51:.
891:.
861:.
828:.
751:.
721:.
660:.
443:F
439:S
434:C
424:Z
419:S
401:C
397:P
393:R
382:P
378:S
374:R
363:R
352:R
341:R
330:R
319:R
308:R
285:0
280:1
275:2
270:3
265:4
260:5
255:6
250:7
245:8
240:9
235:0
230:1
225:2
220:3
215:4
210:5
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