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HP Saturn

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359:(General Purpose Registers), named A, B, C and D. In addition, there are also five 64-bit "scratch" registers named R0, R1, R2, R3 and R4. These can only store data. If an ALU operation is required for data in a scratch register, then the register in question must be transferred to a GPR first. Other registers include a 1-nibble "pointer" register named P, usually used to select a nibble in a GPR or a range of nibbles (or for aligning immediate data on a specific nibble in a GPR, with wrap-around). For memory access, there are two 20-bit data pointer registers named D0 and D1. The Saturn architecture also has a PC or 637:** In the following A.W is assumed to contain the argument (< 1E14). ** The result (IP(SQRT(A.W))) is in C.W: SETDEC ASL W C=A W A=A+A W A=A+A W A=A+C W ASR W C=0 W P= 13 LC(1) 5 - CSR WP C=C-1 P -- C=C+1 P A=A-C W GONC -- A=A+C W CSR W P=P-1 P=P-1 GONC - SETHEX A=C W 47: 375: 563:
significant nibble of a GPR), XS (exponent sign, nibble 2 of a GPR), M (mantissa, nibbles 3–14 of a GPR), X (exponent, first 3 nibbles of a GPR) and B (first byte of a GPR). In addition, there is the P field which selects a nibble from a GPR based on the P register's 4-bit value. Also, there is the WP field which selects nibbles 0 through the nibble selected in the P register. The 64 bits (16 nibbles) can hold BCD-formatted coded
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register named HS, which notably, contains the SB or "sticky bit" flag indicating whether a binary 1 was right shifted off of a GPR. Furthermore, the Saturn architecture has a 12-bit OUT register and a 16-bit IN register, which in the Yorke and Clarke SoCs, are used to capture input from the keyboard and also control the beeper. There is also a 1-bit carry flag register.
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In addition to the above, the Saturn CPU has a simple, non-prioritized interrupt system. When an interrupt occurs, the CPU finishes executing the current instruction, saves the program counter to the hardware return stack (RSTK) and jumps to address 0x0000Fh, where the preceding value is in nibbles.
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Data in the general purpose registers can be accessed via fields that fall on nibble boundaries, whereas the scratch registers allow only load and store operations. The fields, as shown in the above diagram, are W (whole 64-bit GPR), A (address, first 5 nibbles of a GPR), S (sign of mantissa, most
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register which can interoperate with the GPRs. There is also an 8-level, circular, LIFO 20-bit hardware return stack named RSTK used when a subroutine call instruction is issued. Additionally, the Saturn CPU is equipped with a 16-bit software status register named ST and a 1-nibble hardware status
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and back. The virtual CPU / emulator code names were inspired by the prototype "New-Yorke" Saturn-based 8 MHz SoC that never made it to production. According to one of the ACO (Australian Calculator Operation) members, "Big Apple" was derived from the code name "New-Yorke" of the prototype
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The Saturn architecture has an internal register width of 64 bits and 20-bits of address, with memory being addressed to 4-bit (nibble) granularity. Saturn ALU instructions support variable data width, operating on one to 16 nibbles of a word. The original Saturn CPU chips provided a four-bit
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format (±499). The internal representation of BCD floating point values are a 15-digit mantissa with one sign nibble in one register combined with a 20-bit exponent, in 10's complement format, in another register. The use of BCD instead of straight binary representation is advantageous for
1725: 1654: 340:. Internally, the Saturn CPU has four 4-bit data buses that allow for nearly 1-cycle per nibble performance with one or two buses acting as a source and one or two acting as a destination. The smallest addressable 348:(BCD) digit. Any unit of data in the registers larger than a nibble, up to 64-bits, can be operated on as a whole, however the Saturn CPU performs the operation serially on a nibble-by-nibble basis internally. 614:
The original HP-71B handheld computer and the HP-28C had the Saturn processor as a separate chip. In the HP 48S/SX, 48G/GX series and HP-28S, HP-27S, HP-42S, HP-32SII and HP-20S, the
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family of processors used in earlier calculators. The HP48SX and HP48S were the last models to use HP manufactured Saturn processors, later models used processors manufactured by
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were the last calculators introduced based on the actual NEC fabricated Saturn hardware. The last calculators introduced to use the Saturn emulator were the
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8 MHz, LCD controller, memory controller, UART and IR control. This was only made as an internal HP prototype and never released in the wild.
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external data bus, but later Saturn-based SoCs included on chip bus conversion to an 8-bit external data bus and 19-bit external address bus.
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initially used the Saturn CPU until the NEC fab could no longer manufacture the processor for technical reasons in 2003. Starting with the
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The following diagram depicts the registers (with each white square being 4-bits / a nibble except for the Carry flag, which is 1 bit):
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The following is an integer implementation of a BCD decimal square root algorithm in Saturn Jazz / HP Tools assembly syntax:
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8 MHz Saturn-based SoC in a reference to New York city, hence the names "Big apple", "Mid Apple" and "Little Apple".
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Nine 64-bit GPR and "scratch" registers, two 20-bit "data pointer" registers and other miscellaneous registers
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handheld computer, released in 1984, and later for various HP calculators (starting with the
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Fernandes, Gilbert Henri (2005-07-16) . "Chapter 56.1 Real number". In Rechlin, Eric (ed.).
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HP-41C CPU, Display Driver, HP-IL, Data Storage, Timer IC, and Interface IC Specifications
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3.68–4 MHz, LCD controller, memory controller, UART and IR control, manufactured by
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architecture) which ran an emulator of the Saturn hardware in software. In 2000, the
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which contains the embedded Saturn microprocessor manufactured by HP for use in the
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The Saturn CPU's instruction and data addresses are also nibble-based. The three
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registers are 20 bits wide. Due to this, the Saturn architecture can address 1
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If the exponent is negative, the exponent is encoded as "1000 - ABS(exponent)"
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Hybrid 64-bit GPR, 20-bit address bus, 4-bit datapath, 4-bit minimum word size
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Virtual version of the Yorke CPU emulated by members of the 48/75 MHz
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The CPU also interacts with the keyboard scanning logic directly.
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of 1804–1806, the first United States overland expedition to the
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HP48 Machine Language - A Journey to the Center of the HP 48s/sx
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Fernandes, Gilbert Henri (2005-07-16) . Rechlin, Eric (ed.).
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1 MHz, 64 KB ROM, LCD driver, memory controller,
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In the emulated / virtual "Apple" series Saturn CPUs, the
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640 kHz, 16 KB ROM, 512 bytes RAM, LCD driver
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640 kHz, 10 KB ROM, 256 bytes RAM, LCD driver
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digits and a 3-digit 10's complement exponent stored in
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The original Saturn CPU gave its name to the entire
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nibble (which is "9" if the number is negative), 12
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Summary information in the Museum of HP Calculators
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Beyond that size (e.g. in the 48GX), 39: 1142:Wessman, Timothy "Tim" James (2015-12-26). 1788: 1774: 1766: 1068:is "2" but with virtual opcode extensions. 45: 1043: 1041: 115:with some exceptions which fall into the 1733:Introduction to Saturn Assembly Language 1213:Introduction to Saturn Assembly Language 1055:Japan, D3004GD, 00048-80063, 9738PX002". 651: 649:. Later chips had their own code names: 384: 355:The Saturn architecture has four 64-bit 27:Family of 4-bit datapath microprocessors 1081: 1037: 1699:Le compagnon de Voyage de la HP48 G/GX 1696:; de BrĂ©bisson, Cyrille (March 1994). 38: 1736:(3rd ed.). hpcalc.org. ID 1693. 1001:with additional virtual instructions 344:is a 4-bit nibble which can hold one 7: 1572:; Lalande, SĂ©bastien (2006-06-25) . 1527:; Lalande, SĂ©bastien (2006-06-25) . 1482:; Lalande, SĂ©bastien (2006-06-27) . 1430:de BrĂ©bisson, Cyrille (2020-06-16). 1400:de BrĂ©bisson, Cyrille (2020-06-17). 1051:, the Saturn processor is labelled " 855:and IR control, more instructions 25: 1798:Hewlett-Packard (HP) calculators 1632:Voyage au centre de la HP48 g/gx 1575:Voyage au centre de la HP48 s/sx 1340:Finseth, Craig A. (2016-12-23). 1258:Donnini, Giuseppe (2020-06-26). 716:640 kHz, more instructions 332:serial design as opposed to its 1740:from the original on 2016-08-06 1657:from the original on 2016-08-06 1600:from the original on 2018-11-13 1545:from the original on 2018-11-14 1500:from the original on 2016-08-06 1382:from the original on 2019-04-29 1348:from the original on 2017-12-21 1220:from the original on 2018-11-13 1154:from the original on 2018-07-08 1124:from the original on 2018-07-08 1485:Voyage au centre de la HP28c/s 603:nibbles or, equivalently, 512 1: 1305:. Hewlett Packard. 1993-08-20 1299:"The Saturn assembler manual" 1112:Kuperus, Klaas (2015-03-06). 1089:Kuperus, Klaas (2015-03-04). 165:Only extensions for emulated 1459:Mastracci, Matthew (1998) . 937: 918: 862: 834: 786: 750: 723: 696: 673: 647:instruction set architecture 548: 537: 530: 517: 509: 495: 117:register–memory architecture 2102:Scientific non-programmable 1366:Arnett, Dave (1994-05-03). 584:problems that occur on the 255:in the 1980s first for the 2499: 1179:"3.1 Processor Overview". 1114:"HP 50g not so good news?" 1009:Lewis and Clark Expedition 541: 533: 523: 510: 499: 386:HP Saturn register fields 157:No MMU or paging available 29: 1097:. Moravia. Archived from 1026:Digit-serial architecture 663:Used in calculator models 641:Chipsets and applications 586:binary/decimal conversion 580:calculators as it avoids 555: 552: 526: 513: 505: 496: 443: 390: 328:The Saturn hardware is a 198: 44: 1432:"RE: "New-Yorke" ?" 1402:"RE: "New-Yorke" ?" 1924:Scientific programmable 1091:"HP 50g: End of an era" 827:control, 3 V CMOS 336:predecessor, which was 113:load–store architecture 2213:Financial and business 1463:. 1.0b. Archived from 989:processor family with 565:floating point numbers 379: 2483:4-bit microprocessors 377: 169:-based "virtual" CPUs 1260:""New-Yorke" ?" 346:binary-coded decimal 263:). It succeeded the 1066:ISA level / version 975: (2003/2007), 660:Processor code-name 387: 378:HP Saturn registers 229:No vector registers 41: 2473:HP microprocessors 2445:Emulation software 997:architecture) aka 620:integrated circuit 385: 380: 292:core (part of the 288:processor with an 32:Paragon Publishing 2460: 2459: 1368:"Name that chip!" 1095:forum.hp-prime.de 1005: 1004: 560: 559: 251:was developed by 233: 232: 111:Combination of a 16:(Redirected from 2490: 1799: 1790: 1783: 1776: 1767: 1748: 1746: 1745: 1724: 1722: 1721: 1712:. Archived from 1665: 1663: 1662: 1608: 1606: 1605: 1553: 1551: 1550: 1508: 1506: 1505: 1475: 1473: 1472: 1446: 1445: 1443: 1442: 1436:www.hpmuseum.org 1427: 1416: 1415: 1413: 1412: 1406:www.hpmuseum.org 1397: 1391: 1390: 1388: 1387: 1363: 1357: 1356: 1354: 1353: 1337: 1314: 1313: 1311: 1310: 1295: 1274: 1273: 1271: 1270: 1264:www.hpmuseum.org 1255: 1234: 1231: 1226: 1225: 1207: 1201: 1200: 1193: 1187: 1186: 1176: 1163: 1162: 1160: 1159: 1139: 1133: 1132: 1130: 1129: 1109: 1103: 1102: 1086: 1069: 1062: 1056: 1045: 652: 439: 3–0  388: 219:No FPU registers 209:Four 64-bit GPRs 49: 42: 21: 2498: 2497: 2493: 2492: 2491: 2489: 2488: 2487: 2463: 2462: 2461: 2456: 2440: 2399: 2341: 2208: 2097: 1919: 1801: 1797: 1794: 1757: 1743: 1741: 1729: 1719: 1717: 1710: 1692: 1660: 1658: 1643: 1629:(2006-06-25) . 1625: 1603: 1601: 1586: 1568: 1548: 1546: 1523: 1503: 1501: 1478: 1470: 1468: 1458: 1455: 1453:Further reading 1450: 1449: 1440: 1438: 1429: 1428: 1419: 1410: 1408: 1399: 1398: 1394: 1385: 1383: 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1024: 1023: 1019: 1017: 1014: 1013:Pacific coast 1010: 1000: 996: 993:core (of the 992: 988: 985: 981: 979: (2006) 978: 974: 973:hp 48gII 970: 966: 962: 958: 955: 952: 948: 944: 940: 934: 933: 929: 926: 923: 921: 915: 914: 910: 909:Saturn 5 906: 902: 900: (1999) 899: 895: 891: 887: 883: 879: 875: 871: 868: 865: 859: 858: 854: 850: 848: (1991) 847: 843: 840: 837: 831: 830: 826: 822: 820: (1988) 819: 815: 811: 807: 806:HP 19BII 803: 799: 798:HP 17BII 795: 792: 789: 783: 782: 778: 776: (1991) 775: 771: 767: 763: 759: 756: 753: 747: 746: 742: 740: 736: 732: 729: 726: 720: 719: 715: 713: 709: 705: 702: 699: 693: 692: 689: 687: (1984) 686: 682: 679: 676: 670: 669: 665: 662: 659: 657: 654: 653: 650: 648: 640: 635: 629: 627: 625: 621: 617: 612: 610: 606: 602: 598: 594: 589: 587: 583: 578: 574: 570: 566: 549: 544: 538: 531: 520: 518: 502: 491: 488: 485: 482: 479: 476: 473: 470: 467: 464: 461: 458: 455: 452: 449: 446: 442: 438: 435: 432: 429: 426: 423: 420: 417: 414: 411: 408: 405: 402: 399: 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Moravia. 1049:HP 48G 977:HP 50g 898:HP 49G 890:HP 48G 882:HP 40G 878:HP 39G 870:HP 38G 846:HP 48S 666:Properties 182:Predecessor 177:Proprietary 2467:Categories 2390:OfficeCalc 1744:2009-02-17 1720:2015-09-06 1661:2015-09-06 1604:2015-09-06 1549:2015-09-06 1504:2015-09-06 1471:2006-05-03 1441:2020-06-18 1411:2020-06-18 1386:2019-04-22 1352:2017-12-21 1309:2020-07-06 1269:2020-07-06 1224:2019-04-29 1158:2016-01-01 1128:2016-01-01 1076:References 927:prototype 433:11–8  338:bit-serial 239:family of 162:Extensions 145:Endianness 82:Introduced 2395:PrintCalc 2380:QuickCalc 1494:636072913 1372:Newsgroup 1148:HP Museum 1118:HP Museum 947:Mid Apple 943:Big Apple 920:New-Yorke 911:platform 752:Sacajawea 656:ISA level 611:is used. 193:Registers 154:Page size 135:Branching 93:"Level 2" 2385:EasyCalc 2245:Prestige 2240:Platinum 2114:6s Solar 1807:Graphing 1738:Archived 1655:Archived 1651:29640044 1598:Archived 1594:29640044 1543:Archived 1539:34148948 1498:Archived 1380:Archived 1346:Archived 1218:Archived 1152:Archived 1122:Archived 1020:See also 941:series ( 774:HP-32SII 582:rounding 573:mantissa 318:hp 48gII 245:datapath 129:Variable 125:Encoding 64:Designer 18:HP Yorke 2363:CalcPad 1915:Xpander 1374::  1342:"names" 1047:In the 999:Saturn+ 991:ARM920T 987:S3C2410 984:Samsung 838:(1LT8) 790:(1LR2) 770:HP-32S+ 754:(1LR3) 727:(1LU7) 700:(1LK7) 677:(1LF2) 597:address 593:pointer 497:Fields 310:HP 40gs 306:HP 39gs 290:ARM920T 286:S3C2410 283:Samsung 279:HP 49g+ 90:Version 2267:17bII+ 2230:10bII+ 1706:  1649:  1639:  1592:  1582:  1537:  1492:  995:ARMv4T 836:Clarke 818:HP-42S 814:HP-28S 810:HP-27S 802:HP-19B 794:HP-17B 766:HP-32S 762:HP-22S 758:HP-14B 739:HP-21S 735:HP-20S 731:HP-10B 712:HP-71B 708:HP-28C 704:HP-18C 698:Saturn 685:HP-71B 681:HP-44A 675:Saturn 616:Saturn 553:  542:  511:  500:  444:Nibble 330:nibble 314:HP 50g 302:HP 40G 298:HP 39G 294:ARMv4T 273:. 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Index

HP Yorke
Paragon Publishing
Photo of HP48SX 1LT8 SoC die containing an embedded Saturn CPU
SoC
HP 48SX
Hewlett-Packard
Design
load–store architecture
register–memory architecture
Encoding
Branching
Endianness
ARM
Nut
Registers
General-purpose
Floating point
Vector
4-bit
datapath
microprocessors
Hewlett-Packard
HP-71B
HP-18C
Nut
NEC
HP 49 series
HP 49g+
Samsung
S3C2410

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