Channel I/O - Knowledge (XXG)

476:

The central processor is then free to proceed with non-I/O instructions until interrupted. When the channel operations are complete, the channel interrupts the central processor with an I/O interruption. In earlier models of the IBM mainframe line, the channel unit was an identifiable component, one for each channel. In modern mainframes, the channels are implemented using an independent RISC processor, the channel processor, one for all channels. IBM System/370 Extended Architecture and its successors replaced the earlier SIO (

240:, and then went on to the next lower priority channel. Preemption was possible, in some instances. Sufficient FIFO storage was provided within the "C-Unit" for all channels which were emulated by this FSM. Channels could be easily reconfigured to the customer's choice of selector, byte multiplexor) or block multiplexor channel, without any significant restrictions by using maintenance console commands. "Two-byte interface" was also supported as was "Data-In/Data-Out" and other high-performance IBM channel options. Built-in 755:(IPL) in IBM nomenclature, is carried out by channels, although the process is partially simulated by the CPU through an implied Start I/O (SIO) instruction, an implied Channel Address Word (CAW) at location 0 and an implied channel command word (CCW) with an opcode of Read IPL, also at location 0. Command chaining is assumed, so the implied CCW at location 0 falls through to the continuation of the channel program at locations 8 and 16, and possibly elsewhere should one of those CCWs be a transfer-in-channel (TIC). 770:

IPL would not be possible. On a DASD, the IPL Text is contained on cylinder X'0000', track X'0000', and record X'01' (24 bytes), and cylinder X'0000', track X'0000', and record X'02' (fairly large, certainly somewhat more than 3,000 bytes). The volume label is always contained on cylinder X'0000', track X'0000', and block X'03' (80 bytes). The volume label always points to the VTOC, with a pointer of the form HHHH (that is, the VTOC must reside within the first 65,536 tracks). The VTOC's

759:

in main storage. The first double word contains a PSW which, when fetched at the conclusion of the IPL, causes the CPU to execute the IPL Text (bootstrap loader) read in by the CCW at location 8. The IPL Text then locates, loads and transfers control to the operating system's Nucleus. The Nucleus performs or initiates any necessary initialization and then commences normal OS operations.

641: 393:

also are dedicated to input and output. There may be several CPUs and several I/O processors. The overall architecture optimizes input/output performance without degrading pure CPU performance. Since most real-world applications of mainframe systems are heavily I/O-intensive business applications, this architecture helps provide the very high levels of

96:; however, most are not. On some systems the channels use memory or registers addressable by the central processor as their working storage, while on other systems it is present in the channel hardware. Typically, there are standard interfaces between channels and external peripheral devices, and multiple channels can operate concurrently. 769:

DASD controllers accept the X'02' command, seek to cylinder X'0000' head X'0000', skip to the index point (i.e., just past the track descriptor record (R0)) and then treat the Read IPL command as if it were a Read Data (X'06') command. Without this special DASD controller behavior, device-independent

758:

To load a system, the implied Read IPL CCW reads the first block of the selected IPL device into the 24-byte data area at location 0, the channel continues with the second and third double words, which are CCWs, and this channel program loads the first portion of the system loading software elsewhere

617:

If the dataset is allocated in tracks, and the end of the track is reached without the requested record being found the channel program terminates and returns a "no record found" status indication. Similarly, if the dataset is allocated in cylinders, and the end of the cylinder is reached without the

594:

The TIC (transfer in the channel) will cause the channel program to branch to the SEARCH command until a record with a matching key (or the end of the track) is encountered. When a record with a matching key is found the DASD controller will include Status Modifier in the channel status, causing the

475:

is a sequence of channel command words (CCWs) that are executed by the I/O channel subsystem. A channel program consists of one or more channel command words. The operating system signals the I/O channel subsystem to begin executing the channel program with an SSCH (start sub-channel) instruction.

214:

hardware implementation of System/370 compatible channels was quite different. A single internal unit, called the "C-Unit", supported up to sixteen channels using the very same hardware for all supported channels. Two internal "C-Units" were possible, supporting up to 32 total channels. Each "C-Unit"

103:

to the channel in order to handle I/O tasks, which the channel and controller can, in many cases, complete without further intervention from the CPU (exception: those channel programs which utilize 'program controlled interrupts', PCIs, to facilitate program loading, demand paging and other essential

778:

If an attempt is made to IPL from a device that was not initialized with IPL Text, the system simply enters a wait state. The DASD (direct access storage device) initialization program, IBCDASDI, or the DASD initialization application, ICKDSF, places a wait state PSW and a dummy CCW string in the 24

552:

to form the channel program. Bits in the CCW indicates that the following location in storage contains a CCW that is part of the same channel program. The channel program normally executes sequential CCWs until an exception occurs, a Transfer-in-Channel (TIC) CCW is executed, or a CCW is executed

539:

by the operating system, and I/O subroutine, a utility program, or by standalone software (such as test and diagnostic programs). A limited "branching" capability, hence a dynamically programmable capability, is available within such channel programs, by use of the "status modifier" channel flag and

392:

On large mainframe computer systems, CPUs are only one of several powerful hardware components that work in parallel. Special input/output controllers (the exact names of which vary from one manufacturer to another) handle I/O exclusively, and these, in turn, are connected to hardware channels that

706:

As page fixing and unfixing is a CPU-expensive process long-term page fixing is sometimes used to reduce the CPU cost. Here the virtual memory is page-fixed for the life of the application, rather than fixing and freeing around each I/O operation. An example of a program that can use long-term page

384:

It is possible to develop very complex channel programs, including testing of data and conditional branching within that channel program. This flexibility frees the CPU from the overhead of starting, monitoring, and managing individual I/O operations. The specialized channel hardware, in turn, is

380:

Each channel may support one or more controllers and/or devices, but each channel program may only be directed at one of those connected devices. A channel program contains lists of commands to the channel itself and to the controller and device to which it is directed. Once the operating system

124:

required processing until either an ending condition or a program controlled interrupt (PCI). This eliminates much of the CPU—Channel interaction and greatly improves overall system performance. The channel may report several different types of ending conditions, which may be unambiguously normal,

192:

computers the channels were still bulky and expensive separate components, such as the IBM 2860 Selector channel (one to three selector channels in a single box), the IBM 2870 Byte multiplexor channel (one multiplexer channel, and, optionally, one selector subchannel in a single box), and the IBM

83:

Channel architecture avoids this problem by processing some or all of the I/O task without the aid of the CPU by offloading the work to dedicated logic. Channels are logically self-contained, with sufficient logic and working storage to handle I/O tasks. Some are powerful or flexible enough to be

527:

to a specialized I/O channel processor which is, in fact, a finite state machine. It is used to initiate an I/O operation, such as "read", "write" or "sense", on a channel-attached device. On system architectures that implement channel I/O, typically all devices are connected by channels, and so

244:

were also offered, called CCAs in Amdahl-speak, but called CTCs or CTCAs in IBM-speak. A real game-changer, and this forced IBM to redesign its mainframes to provide similar channel capability and flexibility. IBM's initial response was to include stripped-down Model 158s, operating in "Channel

766:, (DASD), e.g., disk, drum. The Read IPL (X'02') command, which is simulated by the CPU, is a Read EBCDIC Select Stacker 1 read command on the card reader and a Read command on tape media (which are inherently sequential access in nature), but a special Read-IPL command on DASD. 282:

and 160A. The operating system initially resided and executed in PP0. The channels had no direct access to memory and could not cause interrupts; software on a PP used synchronous instructions to transfer data between the channel and either the A register or PP memory.

235:

were performed: data was read from or written to main storage, the operating system program was interrupted if such interruption was specified by the channel program's Program Control Interrupt flag, and the "C-Unit" finally stored that channel's next state and set its

588:. The track containing the record and the desired value of the key is known. The device control unit will search the track to find the requested record. In this example <> indicate that the channel program contains the storage address of the specified field. 738:

by another special SYSEVENT (SYSEVENT DONTSWAP). Whenever such an application terminates, whether normally or abnormally, the operating system implicitly issues yet another special SYSEVENT on the application's behalf if it has not already done so (SYSEVENT OKSWAP).

125:

may unambiguously indicate an error or whose meaning may depend on the context and the results of a subsequent sense operation. In some systems an I/O controller can request an automatic retry of some operations without CPU intervention. In earlier implementations,

129:

error, no matter how small, required CPU intervention, and the overhead was, consequently, much higher. A program-controlled interruption (PCI) is still used by certain legacy operations, but the trend is to move away from such PCIs, except where unavoidable.

774:

defines the extent (size) of the VTOC, so the volume label only needs a pointer to the first track in the VTOC's extent, and as the Format 4 DSCB, which describes the VTOC, is always the very first DSCB in the VTOC, HHHH also points to the Format 4 DSCB.

698:

function which was designed into the OS Supervisor just for those "fixes" which are of relatively short duration (i.e., significantly shorter than "wall-clock time"). Pages containing data to be used by the I/O operation are locked into real memory, or

407:

terminology, a channel is a parallel data connection inside the tree-like or hierarchically organized I/O subsystem. In System/390 I/O cages, channels either directly connect to devices which are installed inside the cage (communication adapter such as

561:

indicates that the next CCW contains the address of additional data for the same command, allowing, for example, portions of one record to be written from or read to multiple data areas in storage (gather-writing and scatter-reading).

245:

Mode", only, as the Model 303x channel units. In the Amdahl "C-unit" any channel could be any type, selector, byte multiplexor, or block multiplexor, without reserving channels 0 and 4 for the byte multiplexers, as on some IBM models.

361:

Computer systems that use channel I/O have special hardware components that handle all input/output operations in their entirety independently of the systems' CPU(s). The CPU of a system that uses channel I/O typically has only one

1111:

See System/370 Principles of Operation, GA22–7000–4, pp 54—55, Initial Program Loading; System/370 Extended Architecture is quite similar, although XA utilizes an "implied" Start Subchannel (SSCH) instead of an "implied" Start

381:

has prepared a complete list of channel commands, it executes a single I/O machine instruction to initiate the channel program; the channel thereafter assumes control of the I/O operations until they are completed.

613:

SEEK <cylinder/head number> SEARCH KEY HIGH OR EQUAL <key value> TIC *-8 Back to search if not high or equal READ DATA <buffer>

618:

requested record being found the channel program terminates and returns a "no record found" status indication. In some cases, the system software has the option of updating the track or cylinder number and

146:, had two to eight 6-bit channels (the 7607) and a channel multiplexor (the 7606) which could control up to eight channels. The 7090 and 7094 could also have up to eight 8-bit channels with the 7909. 278:

utilized 10 logically independent computers called peripheral processors (PPs) and 12 simple I/O channels for this role. PPs were a modified version of CDC's first personal computers, the 12-bit

370:. I/O thereafter proceeds without intervention from the CPU until an event requiring notification of the operating system occurs, at which point the I/O hardware signals an interrupt to the CPU. 223:(FSM). Each CPU cycle, every 32 nanoseconds in the 470V/6 and /5 and every 26 nanoseconds in the 470V/7 and /8, the "C-unit" read the complete status of next channel in priority sequence and its 330:

The reference implementation of channel I/O is that of the IBM System/360 family of mainframes and its successors, but similar implementations have been adopted by IBM on other lines, e.g.,

268:. Since then, channel controllers have been a standard part of most mainframe designs and primary advantage mainframes have over smaller, faster, personal computers and network computing. 703:. The channel program is copied and all virtual addresses are replaced by real addresses before the I/O operation is started. After the operation completes, the pages are unfixed. 373:

A channel is an independent hardware component that coordinates all I/O to a set of controllers or devices. It is not merely a medium of communication, despite the name; it is a

197:

processor complexes, the channels were implemented in independent channel directors in the same cabinet as the CPU, with each channel director implementing a group of channels.

200:

Much later, the channels were implemented as an on-board processor residing in the same box as the CPU, generally referred to as a "channel processor", and which was usually a

76:

Many I/O tasks can be complex and require logic to be applied to the data to convert formats and other similar duties. In these situations, the simplest solution is to ask the

591:

SEEK <cylinder/head number> SEARCH KEY EQUAL <key value> TIC *-8 Back to search if not equal READ DATA <buffer>

184:

on the CPU, and the CPU itself operated in one of two modes, either "CPU Mode" or "Channel Mode", with the channel mode 'stealing' cycles from the CPU mode. For larger

80:

to handle the logic, but because I/O devices are relatively slow, a CPU could waste time waiting for the data from the device. This situation is called 'I/O bound'.

1086: 499:

requires only one channel program (and thus only one I/O instruction), but multiple channel command words (one per block). The program is executed by the

935: 910: 718:

area of main storage. This is accomplished by a special SYSEVENT in MVS/370 through z/OS operating systems, wherein the application is, first, swapped-

610:

must be the same as the highest key within that block (and the records must be in key sequence), and the following channel program would be utilized:

898:

Cycle-stealing is a form of interrupt in which the component needing access to memory or to the processor takes control for an entire machine cycle.

570:

Channel programs can modify their own operation during execution based on data read. For example, self modification is used extensively in OS/360

311:(DMA) devices. The rationale for these devices is the same as for the original channel controllers, namely off-loading transfer, interrupts, and 1239: 366:

in its repertoire for input and output; this instruction is used to pass input/output commands to the specialized I/O hardware in the form of

1059: 142:

vacuum tube mainframe, whose Model 766 Data Synchronizer was the first channel controller, in 1957. The 709's transistorized successor, the

385:

dedicated to I/O and can carry it out more efficiently than the CPU (and entirely in parallel with the CPU). Channel I/O is not unlike the

455:

Channels may also differ in how they associate peripheral devices with storage buffers. In UNIVAC terminology, a channel may either be

107:

When I/O transfer is complete or an error is detected, the controller typically communicates with the CPU through the channel using an

305: 999: 878: 793: 1219: 289:

introduced in 1981 as a low cost channel equivalent to the IBM Block Multiplexer Channel is now ubiquitous in the form of the

524: 1031:

Attanasio, C.R.; Markstein, P.W.; Phillips, R.J. (1976). "Penetrating an Operating System: a Study of VM/370 Integrity".

440:

supports a number of concurrent interleaved slow-speed operations, each transferring one byte from a device at a time. A

424:

as cables of the thickness of a thumb and directly connect to channel interfaces on bigger devices like tape subsystems,

1234: 763: 496: 425: 377:

device that handles all details of I/O after being given a list of I/O operations to carry out (the channel program).

595:

channel to skip the TIC CCW; thus the channel program will not branch and the channel will execute the READ command.

762:

This IPL concept is device-independent. It is capable of IPL-ing from a card deck, from a magnetic tape, or from a

241: 157:

on, e.g., the 7090, most other vendors used channels that dealt with single records. However, some systems, e.g.,

1095: 960: 962:

A Guide to the IBM 3033 Processor Complex, Attached Processor Complex, and Multiprocessor Complex of System/370

771: 714:

An alternative to long-term page fixing is moving the entire application, including all its data buffers, to a

318:

Channel controllers have been made as small as single-chip designs with multiple channels on them, used in the

939: 177: 1061:

IBM System/360 Component Descriptions: 2314 Direct Access Storage Facility and 2844 Auxiliary Storage Control

452:

supports a number of logically concurrent channel programs, but only one high-speed data transfer at a time.

42:(I/O) architecture that is implemented in various forms on a number of computer architectures, especially on 914: 853: 808: 691: 173: 752: 290: 779:

bytes, should the device be designated for data only, not for IPL, after which these programs format the

436:

Channels differ in the number and type of concurrent I/O operations they support. In IBM terminology, a

120:

In the most recent implementations, the channel program is initiated and the channel processor performs

838: 445: 417: 386: 308: 294: 220: 113: 111:. Since the channel normally has direct access to the main memory, it is also often referred to as a 1012: 363: 215:

independently performed a process generally called a "shifting channel state processor" (a type of

1068: 211: 43: 1147:

Typically the specification of the interface includes both the signals and the external cabling.

193:

2880 Block multiplexor channel (one or two block multiplexor channels in a single box). On the

312: 988:* Similarities to Mainframe, * System 360 Block Multiplexed Channel, *Trend to Microcomputers 204:

processor, but which could be a System/390 microprocessor with special microcode as in IBM's

172:

families of computer offered channel I/O on all models. For the lower-end System/360 Models

1220:

IBM System/370 Principles Of Operation (GA22-7000-4), see chapter on Input/Output Operations

1040: 658: 347: 335: 216: 813: 367: 257: 46:. In the past, channels were generally implemented with custom devices, variously named 858: 848: 833: 631: 584: 492: 185: 165: 64: 1228: 828: 818: 748: 301: 275: 158: 491:

Channel I/O provides considerable economies in input/output. For example, on IBM's

421: 339: 39: 690:

these channel programs before executing them, and for this particular purpose the

1138:

channels ran by cycle stealing rather than with completely independent hardware.

803: 343: 261: 85: 99:

A CPU typically designates a block of storage as, or sends, a relatively small

843: 394: 249: 189: 169: 1135: 351: 181: 108: 31: 17: 1000:

IBM System/370 Extended Architecture Principles of Operation, SA22-7085-0

331: 272: 253: 194: 143: 93: 89: 1044: 484:) machine instructions (System/360 and early System/370) with the SSCH ( 798: 708: 404: 279: 139: 355: 265: 734:

area (SYSEVENT TRANSWAP). Thereafter, the application may be marked

248:

Some of the earliest commercial non-IBM channel systems were on the

413: 409: 84:

used as a computer on their own and can be construed as a form of

726:

area, to swap and page external storage, and is, second, swapped-

649:

may be weighted too heavily toward only one aspect of its subject

780: 622:

the I/O operation without interrupting the application program.

571: 319: 286: 205: 201: 969: 823: 635: 401: 77: 557:

tells the channel that the next CCW contains a new command.

1156:

Using explicit tests of channel status and the instructions

459:(ISI), with a single buffer and device active at a time, or 428:(DASDs), terminal concentrators and other ESA/390 systems. 397:

that distinguish mainframes from other types of computers.

582:

The following example reads a disk record identified by a

1014:

Student Text: Introduction to IBM System/360 Architecture

389:(DMA) of microcomputers, only more complex and advanced. 936:"IBM Archives: 7090 Data Processing System (continued)" 783:

and perform other hard drive initialization functions.

654: 471:

In the IBM System/360 and subsequent architectures, a

463:(ESI), with the device selecting which buffer to use. 655:

introducing more general information to this section

444:supports one high-speed operation, transferring a 300:Modern computers may have channels in the form of 227:. The necessary actions defined by that channel's 986:. Technology Forums. October 1986. p. 202. 1130: 1128: 1067:. IBM Corporation. p. 50.2. Archived from 606:records (more than one record per block), the 913:. 03.ibm.com. 23 January 2003. Archived from 682:, while the channel programs are built using 420:) or they run outside of the cage, below the 8: 507:processor (the CPU) is free for other work. 161:, had more sophisticated I/O architectures. 722:from wherever it may be, presumably from a 686:. The operating system is responsible for 626:Channel programs in virtual storage systems 88:, for example, the 7909 Data Channel on an 911:"IBM Archives: 709 Data Processing System" 338:, and by other mainframe vendors, such as 150: 138:The first use of channel I/O was with the 27:High-performance input/output architecture 495:, the formatting of an entire track of a 938:. 03.ibm.com. 1958-12-30. Archived from 657:. Feel free to discuss the issue on the 488:) instruction (ESA/370 and successors). 180:and below, channels were implemented in 1124: 870: 678:On most systems channels operate using 886:Datapro Reports on Data Communications 153:on some of its computers, and allowed 972:. April 1979. p. 3. GC20-1859-4. 7: 1180:Output (A) words from m to channel d 879:"IBM 3705 Communications Controller" 602:records (one record per block). For 100: 1168:Input (A) words to m from channel d 219:), which implemented a specialized 25: 598:The above example is correct for 639: 1094:. pp. 8–12. Archived from 794:Autonomous peripheral operation 566:Self-modifying channel programs 540:the "transfer-in-channel" CCW. 176:and below and System/370 Model 1020:. IBM Corporation. p. 22. 532:I/O requires the use of CCWs. 1: 1240:IBM System/360 mainframe line 553:without chaining indicated. 426:direct access storage devices 154: 764:direct access storage device 680:real (or physical) addresses 304:peripheral devices, such as 242:channel-to-channel adapters 1256: 1174:Output from A to channel d 888:. McGraw-Hili. April 1990 629: 461:externally specified index 457:internally specified index 1198:Function (A) on channel d 1162:Input to A from Channel d 503:I/O processor, while the 1085:IBM Corporation (1978). 1058:IBM Corporation (1969). 1011:IBM Corporation (1968). 743:Booting with channel I/O 535:CCWs are organized into 322:computers for instance. 1204:Function m on channel d 854:UNIVAC 1100/2200 series 809:Execute Channel Program 692:Input/Output Supervisor 578:Channel program example 482:start I/O fast release 291:Fibre Channel Protocol 38:is a high-performance 511:Channel command words 448:of data at a time. A 1192:Disconnect channel d 839:Initial program load 753:Initial Program Load 694:(IOS) has a special 517:channel command word 418:Open Systems Adapter 387:Direct Memory Access 309:direct memory access 295:Serial Attached SCSI 238:I/O Channel out-tags 221:finite state machine 212:Amdahl Corporation's 149:While IBM used data 114:direct memory access 1235:Mainframe computers 1088:OS/VS2 MVS Overview 1045:10.1147/sj.151.0102 1033:IBM Systems Journal 917:on January 14, 2005 438:multiplexer channel 364:machine instruction 315:from the main CPU. 225:I/O Channel in-tags 44:mainframe computers 1186:Activate channel d 968:(Fifth ed.). 751:of the system, or 117:(DMA) controller. 942:on March 13, 2005 684:virtual addresses 676: 675: 486:start sub-channel 450:block multiplexer 432:Types of channels 313:context switching 16:(Redirected from 1247: 1207: 1154: 1148: 1145: 1139: 1132: 1113: 1109: 1103: 1102: 1100: 1093: 1082: 1076: 1075: 1073: 1066: 1055: 1049: 1048: 1028: 1022: 1021: 1019: 1008: 1002: 997: 991: 990: 980: 974: 973: 967: 957: 951: 950: 948: 947: 932: 926: 925: 923: 922: 907: 901: 900: 895: 893: 883: 875: 671: 668: 662: 643: 642: 636: 555:Command chaining 537:channel programs 442:selector channel 368:channel programs 348:General Electric 217:barrel processor 155:command chaining 151:channel commands 21: 1255: 1254: 1250: 1249: 1248: 1246: 1245: 1244: 1225: 1224: 1216: 1211: 1210: 1155: 1151: 1146: 1142: 1133: 1126: 1121: 1116: 1110: 1106: 1098: 1091: 1084: 1083: 1079: 1071: 1064: 1057: 1056: 1052: 1030: 1029: 1025: 1017: 1010: 1009: 1005: 998: 994: 982: 981: 977: 965: 959: 958: 954: 945: 943: 934: 933: 929: 920: 918: 909: 908: 904: 891: 889: 881: 877: 876: 872: 868: 863: 814:GEC 4000 series 789: 745: 672: 666: 663: 653:Please help by 652: 640: 634: 628: 615: 592: 580: 568: 546: 513: 473:channel program 469: 467:Channel program 434: 328: 258:Burroughs B5000 136: 104:system tasks). 101:channel program 74: 28: 23: 22: 15: 12: 11: 5: 1253: 1251: 1243: 1242: 1237: 1227: 1226: 1223: 1222: 1215: 1214:External links 1212: 1209: 1208: 1206: 1205: 1202: 1199: 1196: 1193: 1190: 1187: 1184: 1181: 1178: 1175: 1172: 1169: 1166: 1163: 1160: 1149: 1140: 1123: 1122: 1120: 1117: 1115: 1114: 1104: 1101:on 2011-03-16. 1077: 1074:on 2011-03-22. 1050: 1039:(1): 102–116. 1023: 1003: 992: 975: 952: 927: 902: 869: 867: 864: 862: 861: 859:z/Architecture 856: 851: 849:IBM System/360 846: 841: 836: 834:IBM System z10 831: 826: 821: 816: 811: 806: 801: 796: 790: 788: 785: 744: 741: 674: 673: 646: 644: 632:Virtual memory 630:Main article: 627: 624: 612: 590: 579: 576: 567: 564: 545: 542: 512: 509: 493:Linux on IBM Z 468: 465: 433: 430: 327: 324: 186:IBM System/360 166:IBM System/360 135: 132: 73: 70: 65:DMA controller 56:I/O controller 26: 24: 14: 13: 10: 9: 6: 4: 3: 2: 1252: 1241: 1238: 1236: 1233: 1232: 1230: 1221: 1218: 1217: 1213: 1203: 1200: 1197: 1194: 1191: 1188: 1185: 1182: 1179: 1176: 1173: 1170: 1167: 1164: 1161: 1158: 1157: 1153: 1150: 1144: 1141: 1137: 1131: 1129: 1125: 1118: 1108: 1105: 1097: 1090: 1089: 1081: 1078: 1070: 1063: 1062: 1054: 1051: 1046: 1042: 1038: 1034: 1027: 1024: 1016: 1015: 1007: 1004: 1001: 996: 993: 989: 985: 979: 976: 971: 964: 963: 956: 953: 941: 937: 931: 928: 916: 912: 906: 903: 899: 887: 880: 874: 871: 865: 860: 857: 855: 852: 850: 847: 845: 842: 840: 837: 835: 832: 830: 829:IBM System z9 827: 825: 822: 820: 819:GE-600 series 817: 815: 812: 810: 807: 805: 802: 800: 797: 795: 792: 791: 786: 784: 782: 776: 773: 772:Format 4 DSCB 767: 765: 760: 756: 754: 750: 749:bootstrapping 742: 740: 737: 736:non-swappable 733: 729: 725: 724:non-preferred 721: 717: 712: 710: 704: 702: 697: 693: 689: 685: 681: 670: 660: 656: 650: 647:This section 645: 638: 637: 633: 625: 623: 621: 611: 609: 605: 601: 596: 589: 587: 586: 577: 575: 573: 565: 563: 560: 559:Data chaining 556: 551: 548:IBM CCWs are 543: 541: 538: 533: 531: 526: 522: 518: 510: 508: 506: 502: 498: 494: 489: 487: 483: 479: 474: 466: 464: 462: 458: 453: 451: 447: 443: 439: 431: 429: 427: 423: 419: 415: 411: 406: 403: 398: 396: 390: 388: 382: 378: 376: 371: 369: 365: 359: 357: 353: 349: 345: 341: 337: 333: 332:1410 and 7010 325: 323: 321: 316: 314: 310: 307: 303: 302:bus mastering 298: 296: 292: 288: 284: 281: 277: 276:supercomputer 274: 269: 267: 263: 259: 255: 251: 246: 243: 239: 234: 230: 226: 222: 218: 213: 209: 207: 203: 198: 196: 191: 187: 183: 179: 175: 171: 167: 162: 160: 159:GE-600 series 156: 152: 147: 145: 141: 133: 131: 128: 123: 118: 116: 115: 110: 105: 102: 97: 95: 91: 87: 81: 79: 71: 69: 67: 66: 61: 57: 53: 52:I/O processor 49: 45: 41: 37: 33: 19: 1152: 1143: 1107: 1096:the original 1087: 1080: 1069:the original 1060: 1053: 1036: 1032: 1026: 1013: 1006: 995: 987: 983: 978: 961: 955: 944:. Retrieved 940:the original 930: 919:. Retrieved 915:the original 905: 897: 890:. Retrieved 885: 873: 777: 768: 761: 757: 746: 735: 731: 727: 723: 719: 715: 713: 705: 700: 695: 687: 683: 679: 677: 664: 648: 619: 616: 608:recorded key 607: 603: 599: 597: 593: 585:recorded key 583: 581: 569: 558: 554: 549: 547: 536: 534: 529: 520: 516: 514: 504: 500: 490: 485: 481: 480:) and SIOF ( 477: 472: 470: 460: 456: 454: 449: 441: 437: 435: 422:raised floor 399: 391: 383: 379: 375:programmable 374: 372: 360: 340:Control Data 329: 317: 299: 285: 270: 247: 237: 232: 228: 224: 210: 208:mainframes. 199: 163: 148: 137: 126: 121: 119: 112: 106: 98: 82: 75: 63: 60:synchronizer 59: 55: 51: 47: 40:input/output 35: 29: 804:Bus and Tag 688:translating 525:instruction 505:application 326:Description 262:UNIVAC 1107 164:Later, the 86:coprocessor 36:channel I/O 18:I/O channel 1229:Categories 1136:microcoded 984:SCSI Forum 946:2014-01-22 921:2014-01-22 866:References 844:Intel 8089 707:fixing is 701:page fixed 395:throughput 250:UNIVAC 490 229:last state 190:System/370 170:System/370 732:preferred 716:preferred 659:talk page 620:redriving 600:unblocked 501:dedicated 478:start I/O 352:Honeywell 271:The 1965 182:microcode 109:interrupt 32:computing 892:April 3, 787:See also 696:fast fix 667:May 2021 544:Chaining 523:) is an 273:CDC 6600 254:CDC 1604 231:and its 144:IBM 7090 94:IBM 7094 90:IBM 7090 72:Overview 799:Booting 604:blocked 550:chained 405:ESA/390 280:CDC 160 233:in-tags 140:IBM 709 134:History 48:channel 1201:77 FNC 1195:76 FAN 1189:75 DCN 1183:74 ACN 1177:73 OAM 1171:72 OAN 1165:71 IAM 1159:70 IAN 356:Unisys 354:) and 266:GE 635 58:, I/O 1134:Some 1119:Notes 1099:(PDF) 1092:(PDF) 1072:(PDF) 1065:(PDF) 1018:(PDF) 966:(PDF) 882:(PDF) 747:Even 730:to a 446:block 414:FICON 410:ESCON 62:, or 1112:I/O. 894:2022 781:VTOC 572:ISAM 497:DASD 344:Bull 336:7030 320:NeXT 293:and 287:SCSI 264:and 206:CMOS 202:RISC 195:303x 188:and 168:and 1041:doi 970:IBM 824:I2O 720:out 709:Db2 530:all 521:CCW 402:IBM 400:In 306:PCI 178:158 127:any 122:all 92:or 78:CPU 30:In 1231:: 1127:^ 1037:15 1035:. 896:. 884:. 728:in 711:. 574:. 515:A 416:, 412:, 358:. 342:, 334:, 297:. 260:, 256:, 252:, 174:50 68:. 54:, 50:, 34:, 1047:. 1043:: 949:. 924:. 669:) 665:( 661:. 651:. 519:( 350:/ 346:( 20:)

Text is available under the Creative Commons Attribution-ShareAlike License. Additional terms may apply.

Index