306:(EPIC). Intel's goal was to leverage the expertise HP had developed in their early VLIW work along with their own to develop a volume product line targeted at the aforementioned high-end systems that could be sold to all original equipment manufacturers (OEMs), while HP wished to be able to purchase off-the-shelf processors built using Intel's volume manufacturing and contemporary process technology that were better than their PA-RISC processors.
250:
724:
RISC processors of the time, and no-ops due to wasted slots further decrease the density of code. Additional instructions for speculative loads and hints for branches and cache are impractical to generate optimally, because a compiler cannot predict the contents of the different cache levels on a system running multiple processes and taking interrupts.
752:. The Itanium 2 bus was initially called the McKinley bus, but is now usually referred to as the Itanium bus. The speed of the bus has increased steadily with new processor releases. The bus transfers 2Ă—128 bits per clock cycle, so the 200 MHz McKinley bus transferred 6.4 GB/s, and the 533 MHz Montecito bus transfers 17.056 GB/s
530:. It uses variable-sized register windowing for parameter passing. The same mechanism is also used to permit parallel execution of loops. Speculation, prediction, predication, and renaming are under control of the compiler: each instruction word includes extra bits for this. This approach is the distinguishing characteristic of the architecture.
442:
The very next day on 5th
October 1999, AMD announced their plans to extend Intel's x86 instruction set to include a fully downward compatible 64-bit mode, additionally revealing AMD's newly coming x86 64-bit architecture, which the company had already worked on, to be incorporated into AMD's upcoming
318:
Intel's product marketing and industry engagement efforts were substantial and achieved design wins with the majority of enterprise server OEMs, including those based on RISC processors at the time. Industry analysts predicted that IA-64 would dominate in servers, workstations, and high-end desktops,
633:
indicating which type of instruction is in each slot. Those types are M-unit (memory instructions), I-unit (integer ALU, non-ALU integer, or long immediate extended instructions), F-unit (floating-point instructions), or B-unit (branch or long branch extended instructions). The template also encodes
298:
During this time, HP had begun to believe that it was no longer cost-effective for individual enterprise systems companies such as itself to develop proprietary microprocessors. Intel had also been researching several architectural options for going beyond the x86 ISA to address high-end enterprise
723:
In practice, the processor may often be underutilized, with not all slots filled with useful instructions due to e.g. data dependencies or limitations in the available bundle templates. The densest possible code requires 42.6 bits per instruction, compared to 32 bits per instruction on traditional
656:
The IA-64 assembly language and instruction format was deliberately designed to be written mainly by compilers, not by humans. Instructions must be grouped into bundles of three, ensuring that the three instructions match an allowed template. Instructions must issue stops between certain types of
338:
By 1997, it was apparent that the IA-64 architecture and the compiler were much more difficult to implement than originally thought, and the delivery of
Itanium began slipping. Since Itanium was the first ever EPIC processor, the development effort encountered more unanticipated problems than the
289:
in each clock cycle. Typical VLIW implementations rely heavily on sophisticated compilers to determine at compile time which instructions can be executed at the same time and the proper scheduling of these instructions for execution and also to help predict the direction of branch operations. The
732:
From 2002 to 2006, Itanium 2 processors shared a common cache hierarchy. They had 16 KB of Level 1 instruction cache and 16 KB of Level 1 data cache. The L2 cache was unified (both instruction and data) and is 256 KB. The Level 3 cache was also unified and varied in size from
642:, regardless of their bundling, and must be free of many types of data dependencies; this knowledge allows the processor to execute instructions in parallel without having to perform its own complicated data analysis, since that analysis was already done when the instructions were written.
563:
registers. The floating-point registers are 82 bits long to preserve precision for intermediate results. Instead of a dedicated "NaT" trap bit like the integer registers, floating-point registers have a trap value called "NaTVal" ("Not a Thing Value"), similar to (but distinct from)
290:
value of this approach is to do more useful work in fewer clock cycles and to simplify processor instruction scheduling and branch prediction hardware requirements, with a penalty in increased processor complexity, cost, and energy consumption in exchange for faster execution.
378:(the last three were canceled before reaching the market). In 1999, Intel led the formation of an open-source industry consortium to port Linux to IA-64 they named "Trillium" (and later renamed "Trillian" due to a trademark issue), which was led by Intel and included
669:
into the pipeline. When the compiler can take maximum advantage of this, the processor can execute six instructions per clock cycle. The processor has thirty functional execution units in eleven groups. Each unit can execute a particular subset of the
309:
Intel took the lead on the design and commercialization process, while HP contributed to the ISA definition, the Merced/Itanium microarchitecture, and
Itanium 2. The original goal year for delivering the first Itanium family product, Merced, was 1998.
645:
Within each slot, all but a few instructions are predicated, specifying a predicate register, the value of which (true or false) will determine whether the instruction is executed. Predicated instructions which should always execute are predicated on
814:
Cache enhancements: Montecito added a split L2 cache, which included a dedicated 1 MB L2 cache for instructions. The original 256 KB L2 cache was converted to a dedicated data cache. Montecito also included up to 12 MB of on-die L3
674:, and each unit executes at a rate of one instruction per cycle unless execution stalls waiting for data. While not all units in a group execute identical subsets of the instruction set, common instructions can be executed in multiple units.
787:
Hardware multithreading: Each processor core maintains context for two threads of execution. When one thread stalls during memory access, the other thread can execute. Intel calls this "coarse multithreading" to distinguish it from the
712:, a single floating-point instruction can perform the work of two instructions when the application requires a multiply followed by an add: this is very common in scientific processing. When it occurs, the processor can execute four
771:
architecture to permit support for legacy server applications, but performance for IA-32 code was much worse than for native code and also worse than the performance of contemporaneous x86 processors. In 2005, Intel developed the
996:
472:
In
January 2019, Intel announced that Kittson would be discontinued, with a last order date of January 2020, and a last ship date of July 2021. In November 2023, IA-64 support was removed from the
1437:
1356:
1174:"Sun Introduces Solaris Developer Kit for Intel to Speed Development of Applications On Solaris; Award-winning Sun Tools Help ISVs Easily Develop for Solaris on Intel Today"
2679:
2496:
2782:
2684:
2865:
2694:
1385:
807:: Intel added Intel Virtualization Technology (Intel VT-i), which provides hardware assists for core virtualization functions. Virtualization allows a software "
2880:
2699:
2689:
2674:
2501:
988:
270:. Both Intel and HP researchers had been exploring computer architecture options for future designs and separately began investigating a new concept known as
609:
128 special purpose (or "application") registers, which are mostly of interest to the kernel and not ordinary applications. For example, one register called
339:
team was accustomed to. In addition, the EPIC concept depended on compiler capabilities that had never been implemented before, so more research was needed.
2491:
1173:
285:) where a single instruction word contains multiple instructions encoded in one very long instruction word to facilitate the processor executing multiple
1704:
1441:
2727:
1591:
303:
78:
2787:
708:
Ideally, the compiler can often group instructions into sets of six that can execute at the same time. Since the floating-point units implement a
2870:
1544:
1518:
1492:
1319:
1293:
776:(IA-32 EL), a software emulator that provides better performance. With Montecito, Intel therefore eliminated hardware support for IA-32 code.
1346:
825:
638:
which indicate that a data dependency exists between data before and after the stop. All instructions between a pair of stops constitute an
1848:
1833:
1757:
1747:
1118:
1752:
918:
1612:
1243:
1093:
209:
architectures, which depend on the processor to manage instruction dependencies at runtime. In all
Itanium models, up to and including
1772:
1767:
1762:
1662:
709:
1462:
936:
282:
263:
1647:
889:
2737:
2717:
1980:
1826:
1804:
1799:
1794:
1789:
1742:
1737:
804:
613:
points to the second stack, which is where the hardware will automatically spill registers when the register window wraps around.
1151:
854:
452:
As AMD was never invited to be a contributing party for the IA-64 architecture and any kind of licensing seemed unlikely, AMD's
410:. As a result, a working IA-64 Linux was delivered ahead of schedule and was the first OS to run on the new Itanium processors.
2662:
1809:
1784:
449:. AMD also signaled a full disclosure of the architecture's specifications and further details to be available in August 2000.
2875:
1975:
1944:
1915:
1697:
626:
286:
2546:
2403:
2047:
1956:
1816:
1779:
1732:
1020:
464:, as opposed to Intel's approach of creating an entirely new, completely x86-incompatible 64-bit architecture with IA-64.
223:
198:
1672:
2844:
2018:
1968:
1932:
1378:
1202:
1061:
169:
2042:
2013:
2005:
1963:
1951:
1927:
302:
Intel and HP partnered in 1994 to develop the IA-64 ISA, using a variation of VLIW design concepts which Intel named
514:
It is a 64-bit register-rich explicitly parallel architecture. The base data word is 64 bits, byte-addressable. The
1920:
1652:
367:
271:
2885:
2797:
1690:
1265:
105:
966:
1727:
1713:
132:
694:
2839:
2814:
2408:
734:
188:
1581:
1181:
2829:
1885:
1875:
1870:
1838:
216:
657:
data dependencies, and stops can also only be used in limited places according to the allowed templates.
2819:
2541:
780:
773:
738:
542:
523:
267:
241:
In 2019, Intel announced the discontinuation of the last of the CPUs supporting the IA-64 architecture.
138:
73:
187:(HP), and was subsequently implemented by Intel in collaboration with HP. The first Itanium processor,
1320:"AMD Releases x86-64 Architectural Specification; Enables Market Driven Migration to 64-Bit Computing"
585:
64 one-bit predicate registers. These have 16 static registers and 48 windowed or rotating registers.
2151:
1323:
1297:
2777:
1540:
1514:
1488:
2267:
211:
2824:
2439:
538:
519:
125:
1273:
1128:
319:
and eventually supplant both RISC and CISC architectures for all general-purpose applications.
2590:
2474:
2444:
1411:
932:
527:
343:
332:
1232:
989:"Exit interview: Retiring Intel chairman Craig Barrett on the industry's unfinished business"
2527:
2325:
2219:
2074:
1906:
1861:
1623:
1269:
1082:
922:
491:
The architecture has been renamed several times during its history. HP originally called it
457:
407:
395:
387:
324:
956:
2182:
2155:
1666:
1541:"The Itanium processor, part 3: The Windows calling convention, how parameters are passed"
883:
789:
671:
546:
515:
485:
379:
275:
184:
142:
95:
46:
1466:
88:
733:
1.5 MB to 24 MB. The 256 KB L2 cache contains sufficient logic to handle
460:
capabilities to the existing x86 architecture, while still supporting legacy 32-bit x86
2722:
2386:
878:
688:
560:
456:
architecture-extension was positioned from the beginning as an evolutionary way to add
180:
150:
716:
per cycle. For example, the 800 MHz
Itanium had a theoretical rating of 3.2
541:, which are 64-bit plus one trap bit ("NaT", which stands for "not a thing") used for
2859:
2349:
2339:
2298:
2035:
1143:
1123:
846:
783:, Intel made a number of enhancements to the basic processor architecture including:
1657:
879:"Inventing Itanium: How HP Labs Helped Create the Next-Generation Chip Architecture"
249:
2602:
2288:
1939:
745:
473:
461:
1347:"Intel to Discontinue Itanium 9700 'Kittson' Processor, the Last of the Itaniums"
2508:
2459:
2449:
2344:
2311:
2306:
2293:
2252:
2246:
2240:
1992:
1987:
1821:
910:
436:
430:
375:
206:
1028:
915:
Proceedings of the 10th annual international symposium on
Computer architecture
2747:
2742:
2657:
2652:
2647:
2642:
2637:
2632:
2627:
2622:
2617:
2612:
2607:
2597:
2536:
2481:
2454:
2398:
2279:
2234:
2228:
2203:
2197:
2191:
2170:
2164:
2123:
2118:
2113:
2108:
2103:
2098:
2083:
2023:
1566:
1564:
Sharangpani, Harsh; Arora, Ken (2000). "Itanium
Processor Microarchitecture".
808:
761:
403:
371:
222:
In 2008, Itanium was the fourth-most deployed microprocessor architecture for
115:
1053:
568:. These also have 32 static registers and 96 windowed or rotating registers.
2807:
2792:
2752:
2585:
2580:
2575:
2469:
2464:
2371:
2366:
1880:
1351:
1210:
961:
720:
and the fastest
Itanium 2, at 1.67 GHz, was rated at 6.67 GFLOPS.
666:
399:
351:
328:
231:
1515:"The Itanium processor, part 2: Instruction encoding, templates, and stops"
811:" to run multiple operating system instances on the processor concurrently.
687:
Six multimedia units, two parallel shift units, one parallel multiply, one
342:
Several groups developed operating systems for the architecture, including
927:
2802:
2381:
2030:
1892:
1586:
202:
760:"Intel VT-i" redirects here. For the x86 virtualization extensions, see
545:. 32 of these are static, the other 96 are stacked using variably-sized
2834:
2732:
2570:
2563:
2558:
2553:
2513:
2434:
2426:
2421:
2415:
2393:
2093:
2088:
917:. International Symposium on Computer Architecture. New York, NY, USA:
767:
Itanium processors released prior to 2006 had hardware support for the
749:
444:
391:
363:
205:
decides which instructions to execute in parallel. This contrasts with
173:
2757:
2523:
2376:
2361:
2070:
1902:
797:
717:
701:
floating-point multiply–accumulate units (two 32-bit operations each)
665:
The fetch mechanism can read up to two bundles per clock from the L1
422:
320:
227:
31:
913:(1983). "Very Long Instruction Word architectures and the ELI-512".
17:
1682:
2321:
1857:
1617:
768:
453:
359:
355:
248:
235:
177:
50:
1677:
2669:
2486:
2356:
2334:
2130:
1237:
713:
698:
383:
347:
266:(RISC) architectures were approaching a processing limit at one
1686:
1412:"Intel Itanium IA-64 Support Removed With The Linux 6.7 Kernel"
2263:
2215:
2002:
793:
565:
426:
602:
is set to the return address when a function is called with
681:
Six general-purpose ALUs, two integer units, one shift unit
335:
architectures respectively in favor of migrating to IA-64.
1663:
Some undocumented
Itanium 2 microarchitectural information
299:
server and high-performance computing (HPC) requirements.
595:
8 branch registers, for the addresses of indirect jumps.
533:
The architecture implements a large number of registers:
1438:"Intel Itanium Architecture Software Developer's Manual"
1294:"AMD Discloses New Technologies At Microporcessor Forum"
281:
VLIW is a computer architecture concept (like RISC and
1653:
Hewlett Packard Enterprise Integrity Servers Home Page
1322:(Press release). AMD. August 10, 2000. Archived from
1296:(Press release). AMD. October 5, 1999. Archived from
413:
Intel announced the official name of the processor,
2770:
2710:
2522:
2320:
2262:
2213:
2180:
2150:
2143:
2069:
2062:
2001:
1901:
1856:
1847:
1720:
847:"The Server Biz Enjoys the X64 Upgrade Cycle in Q1"
149:
131:
124:
114:
104:
94:
84:
72:
64:
56:
42:
957:"Itanium–Is there light at the end of the tunnel?"
1582:"Intel outfits Itanium processor for faster runs"
488:and the technical press has provided overviews.
518:space is 2 bytes. The architecture implements
327:decided to abandon further development of the
197:The Itanium architecture is based on explicit
1698:
484:Intel has extensively documented the Itanium
443:eighth-generation microprocessor, code-named
417:, on October 4, 1999. Within hours, the name
8:
1015:
1013:
183:. The basic ISA specification originated at
37:
1489:"The Itanium processor, part 1: Warming up"
1203:"Next-generation chip passes key milestone"
262:In 1989, HP began to become concerned that
27:Microprocessor instruction set architecture
2147:
2066:
1853:
1705:
1691:
1683:
617:Each 128-bit instruction word is called a
34:, AMD's 64-bit extension of the IA-32 ISA.
1144:"Core-logic efforts under way for Merced"
926:
873:
871:
304:explicitly parallel instruction computing
507:, but it is still widely referred to as
439:that sank on its maiden voyage in 1912.
2783:Process–architecture–optimization model
1673:IA-64 tutorial, including code examples
1083:"Microprocessors — VLIW, The Past"
1047:
1045:
950:
948:
837:
792:technology" Intel integrated into some
737:operations without disturbing the main
2866:Computer-related introductions in 2001
1054:"Intel's Merced chip may slip further"
36:
1391:from the original on February 1, 2019
826:List of Intel Itanium microprocessors
274:(VLIW) which came out of research by
7:
2881:Very long instruction word computing
1410:Larabel, Michael (2 November 2023).
1119:"Solaris for IA-64 coming this fall"
1359:from the original on April 16, 2019
919:Association for Computing Machinery
677:The execution unit groups include:
549:, or rotating for pipelined loops.
744:Main memory is accessed through a
25:
1345:Anton Shilov (January 31, 2019).
1233:"Intel names Merced chip Itanium"
1052:Shankland, Stephen (1999-07-08).
264:reduced instruction set computing
2798:Intel HD, UHD, and Iris Graphics
1465:. September 2001. Archived from
1231:Kanellos, Michael (1999-10-04).
1117:Vijayan, Jaikumar (1999-09-01).
1886:P6 variant (Enhanced Pentium M)
1594:from the original on 2020-08-01
1580:Cataldo, Anthony (2001-08-30).
1547:from the original on 2018-11-01
1521:from the original on 2018-11-01
1495:from the original on 2018-11-01
1246:from the original on 2015-12-30
1154:from the original on 2016-03-06
1142:Wolfe, Alexander (1999-09-02).
1099:from the original on 2018-06-27
1064:from the original on 2012-10-24
999:from the original on 2018-04-21
969:from the original on 2012-05-03
892:from the original on 2012-03-04
857:from the original on 2016-03-03
145:); 64 1-bit predicate registers
987:Takahashi, Dean (2009-05-08).
955:De Gelas, Johan (2005-11-09).
845:Morgan, Timothy (2008-05-27).
653:, which always reads as true.
501:Itanium Processor Architecture
253:The Intel Itanium architecture
1:
2871:Instruction set architectures
1379:"Product Change Notification"
1264:Finstad, Kraig (1999-10-04).
779:In 2006, with the release of
710:multiply–accumulate operation
199:instruction-level parallelism
1658:Intel Itanium Specifications
1613:"Intel product announcement"
1539:Chen, Raymond (2015-07-29).
1513:Chen, Raymond (2015-07-28).
1487:Chen, Raymond (2015-07-27).
1209:. 1999-09-17. Archived from
1180:. 1998-03-10. Archived from
1027:. 2005-12-07. Archived from
1021:"Itanium: A cautionary tale"
170:instruction set architecture
2902:
1669: (archived 2007-02-23)
759:
693:Two 82-bit floating-point
505:Intel Itanium Architecture
503:(IPA), before settling on
272:very long instruction word
215:, cores execute up to six
172:(ISA) of the discontinued
166:Intel Itanium architecture
38:Intel Itanium architecture
29:
921:(ACM). pp. 140–150.
495:. Intel later called it
390:, Hewlett-Packard, IBM,
224:enterprise-class systems
194:, was released in 2001.
141:; 32 are static, 96 use
30:Not to be confused with
1648:Intel Itanium Home Page
575:always reads +0.0, and
1881:P6 variant (Pentium M)
625:each holding a 41-bit
592:always reads 1 (true).
254:
217:instructions per cycle
2876:Intel microprocessors
1274:comp.sys.mac.advocacy
928:10.1145/800046.801649
803:Hardware support for
774:IA-32 Execution Layer
756:Architectural changes
739:arithmetic logic unit
684:Four data cache units
661:Instruction execution
621:, and contains three
543:speculative execution
421:had been coined on a
268:instruction per cycle
252:
1463:"HPWorks Newsletter"
1384:. January 30, 2019.
537:128 general integer
278:in the early 1980s.
137:128 (64 bits plus 1
1626:on November 7, 2007
728:Memory architecture
695:multiply–accumulate
435:, the "unsinkable"
39:
2680:Sandy Bridge-based
1849:Microarchitectures
1834:Microarchitectures
1678:Itanium Docs at HP
1025:Tech News on ZDNet
704:Three branch units
582:always reads +1.0.
255:
110:Condition register
2853:
2852:
2766:
2765:
2139:
2138:
2058:
2057:
911:Fisher, Joseph A.
640:instruction group
528:branch prediction
344:Microsoft Windows
176:family of 64-bit
159:
158:
16:(Redirected from
2893:
2886:64-bit computers
2685:Ivy Bridge-based
2276:8/16-bit databus
2148:
2067:
2063:Current products
1854:
1714:Intel processors
1707:
1700:
1693:
1684:
1635:
1634:
1632:
1631:
1622:. Archived from
1609:
1603:
1602:
1600:
1599:
1577:
1571:
1562:
1556:
1555:
1553:
1552:
1536:
1530:
1529:
1527:
1526:
1510:
1504:
1503:
1501:
1500:
1484:
1478:
1477:
1475:
1474:
1459:
1453:
1452:
1450:
1449:
1440:. Archived from
1434:
1428:
1427:
1425:
1423:
1416:www.phoronix.com
1407:
1401:
1400:
1398:
1396:
1390:
1383:
1375:
1369:
1368:
1366:
1364:
1342:
1336:
1335:
1333:
1331:
1326:on March 8, 2012
1316:
1310:
1309:
1307:
1305:
1300:on March 8, 2012
1290:
1284:
1283:
1281:
1280:
1261:
1255:
1254:
1252:
1251:
1228:
1222:
1221:
1219:
1218:
1199:
1193:
1192:
1190:
1189:
1170:
1164:
1163:
1161:
1159:
1139:
1133:
1132:
1127:. Archived from
1114:
1108:
1107:
1105:
1104:
1098:
1087:
1079:
1073:
1072:
1070:
1069:
1049:
1040:
1039:
1037:
1036:
1017:
1008:
1007:
1005:
1004:
984:
978:
977:
975:
974:
952:
943:
942:
930:
907:
901:
900:
898:
897:
875:
866:
865:
863:
862:
842:
800:microprocessors.
689:population count
652:
612:
605:
601:
591:
581:
574:
555:
547:register windows
458:64-bit computing
408:VA Linux Systems
388:Cygnus Solutions
354:systems such as
325:Silicon Graphics
143:register windows
40:
21:
2901:
2900:
2896:
2895:
2894:
2892:
2891:
2890:
2856:
2855:
2854:
2849:
2778:Tick–tock model
2762:
2706:
2695:Broadwell-based
2586:Extreme Edition
2518:
2316:
2258:
2209:
2176:
2135:
2054:
1997:
1897:
1843:
1716:
1711:
1667:Wayback Machine
1644:
1639:
1638:
1629:
1627:
1611:
1610:
1606:
1597:
1595:
1579:
1578:
1574:
1563:
1559:
1550:
1548:
1538:
1537:
1533:
1524:
1522:
1512:
1511:
1507:
1498:
1496:
1486:
1485:
1481:
1472:
1470:
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1456:
1447:
1445:
1436:
1435:
1431:
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790:hyper-threading
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748:to an off-chip
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672:instruction set
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647:
629:, plus a 5-bit
610:
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516:logical address
486:instruction set
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425:newsgroup as a
380:Caldera Systems
316:
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276:Yale University
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2303:32-bit databus
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2285:16-bit databus
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1131:on 2000-01-15.
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1092:. 2002-04-18.
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2036:Goldmont Plus
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1469:on 2008-11-20
1468:
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1444:on 2019-04-08
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1213:on 2011-08-09
1212:
1208:
1207:CNET News.com
1204:
1198:
1195:
1184:on 2004-09-20
1183:
1179:
1178:Business Wire
1175:
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1124:Computerworld
1120:
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1091:
1090:NY University
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1031:on 2008-02-09
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938:0-89791-101-6
934:
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888:. June 2001.
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19:
2144:Discontinued
1981:Cypress Cove
1940:Sandy Bridge
1628:. Retrieved
1624:the original
1616:
1607:
1596:. Retrieved
1585:
1575:
1570:. pp. 38–39.
1565:
1560:
1549:. Retrieved
1534:
1523:. Retrieved
1508:
1497:. Retrieved
1482:
1471:. Retrieved
1467:the original
1457:
1446:. Retrieved
1442:the original
1432:
1420:. Retrieved
1415:
1405:
1393:. Retrieved
1373:
1361:. Retrieved
1350:
1340:
1328:. Retrieved
1324:the original
1314:
1302:. Retrieved
1298:the original
1288:
1277:. Retrieved
1266:"Re:Itanium"
1259:
1248:. Retrieved
1236:
1226:
1215:. Retrieved
1211:the original
1206:
1197:
1186:. Retrieved
1182:the original
1177:
1168:
1158:February 27,
1156:. Retrieved
1147:
1137:
1129:the original
1122:
1112:
1101:. Retrieved
1089:
1077:
1066:. Retrieved
1057:
1033:. Retrieved
1029:the original
1024:
1001:. Retrieved
992:
982:
971:. Retrieved
960:
914:
905:
894:. Retrieved
882:
859:. Retrieved
850:
840:
778:
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492:
490:
483:
480:Architecture
474:Linux kernel
471:
451:
446:SledgeHammer
445:
441:
431:
429:on the name
418:
414:
412:
341:
337:
317:
308:
301:
297:
287:instructions
280:
261:
240:
221:
210:
196:
191:
165:
161:
160:
1993:Golden Cove
1988:Willow Cove
1969:Cannon Lake
993:VentureBeat
697:units, two
627:instruction
524:speculation
520:predication
493:PA-WideWord
468:End of life
437:ocean liner
376:Monterey/64
258:Development
207:superscalar
2860:Categories
2788:Intel GPUs
2502:Core-based
2266:(external
2154:oriented (
2024:Silvermont
1976:Sunny Cove
1945:Ivy Bridge
1728:Processors
1630:2007-05-16
1598:2020-01-19
1567:IEEE Micro
1551:2018-10-31
1525:2018-10-31
1499:2018-10-31
1473:2008-01-24
1448:2019-04-08
1422:4 November
1418:. Phoronix
1330:August 15,
1304:August 15,
1279:2013-12-19
1250:2007-04-30
1217:2007-11-01
1188:2008-10-16
1103:2018-06-26
1068:2008-10-16
1035:2007-11-01
1003:2009-05-17
973:2007-03-23
896:2007-03-23
861:2008-10-29
832:References
809:hypervisor
762:Intel VT-x
404:TurboLinux
372:Tru64 UNIX
294:Production
120:Selectable
116:Endianness
89:Load–store
65:Introduced
2840:Codenames
2753:StrongARM
2591:Dual-Core
2564:Dual-Core
2475:Dual-Core
2445:OverDrive
2394:A100/A110
2387:OverDrive
2181:pre-x86 (
2048:Gracemont
1957:Broadwell
1363:April 16,
1352:AnandTech
1270:Newsgroup
1058:CNET News
962:AnandTech
851:IT Jungle
781:Montecito
735:semaphore
539:registers
352:Unix-like
314:Marketing
232:Power ISA
226:, behind
189:codenamed
168:) is the
126:Registers
106:Branching
2845:Larrabee
2723:iAPX 432
2658:11th gen
2653:10th gen
2492:P6-based
2382:RapidCAD
2124:14th gen
2119:13th gen
2114:12th gen
2109:11th gen
2104:10th gen
2031:Goldmont
2019:Saltwell
1933:Westmere
1893:NetBurst
1839:Chipsets
1620:web site
1592:Archived
1587:EE Times
1545:Archived
1519:Archived
1493:Archived
1386:Archived
1357:Archived
1244:Archived
1240:News.com
1152:Archived
1148:EE Times
1094:Archived
1062:Archived
997:Archived
967:Archived
890:Archived
855:Archived
820:See also
631:template
203:compiler
139:trap bit
96:Encoding
43:Designer
2835:Stratix
2771:Related
2733:Itanium
2648:9th gen
2643:8th gen
2638:7th gen
2633:6th gen
2628:5th gen
2623:4th gen
2618:3rd gen
2613:2nd gen
2608:1st gen
2571:Pentium
2554:Celeron
2514:Tolapai
2435:Pentium
2418:(1998)
2416:Celeron
2307:80387DX
2299:80387SX
2094:Pentium
2089:Celeron
2043:Tremont
2014:Bonnell
1964:Skylake
1952:Haswell
1928:Nehalem
1827:Itanium
1743:Pentium
1738:Celeron
1665:at the
1272::
750:chipset
741:(ALU).
604:br.call
499:, then
432:Titanic
415:Itanium
392:Red Hat
368:Solaris
364:FreeBSD
245:History
212:Tukwila
174:Itanium
2758:XScale
2528:64-bit
2524:x86-64
2429:(2004)
2326:32-bit
2289:80C187
2282:(1980)
2255:(1982)
2249:(1982)
2243:(1982)
2237:(1979)
2231:(1978)
2220:16-bit
2214:Early
2206:(1977)
2200:(1974)
2194:(1972)
2173:(1974)
2167:(1971)
2075:64-bit
2071:x86-64
1921:Penryn
1907:64-bit
1903:x86-64
1862:32-bit
1395:May 9,
935:
815:cache.
798:x86-64
718:GFLOPS
619:bundle
526:, and
423:Usenet
419:Itanic
374:, and
321:Compaq
234:, and
228:x86-64
192:Merced
74:Design
60:64-bit
32:x86-64
2830:PIIXs
2711:Other
2509:Quark
2322:IA-32
2312:80487
2294:80287
2253:80286
2247:80188
2241:80186
2183:8-bit
2156:4-bit
1858:IA-32
1822:Quark
1721:Lists
1618:Intel
1389:(PDF)
1382:(PDF)
1097:(PDF)
1086:(PDF)
769:IA-32
714:FLOPs
667:cache
636:stops
623:slots
509:IA-64
497:IA-64
454:AMD64
360:HP-UX
356:Linux
329:Alpha
236:SPARC
178:Intel
162:IA-64
100:Fixed
51:Intel
2825:ICHs
2820:SCHs
2815:PCHs
2748:i960
2743:i860
2738:RISC
2728:EPIC
2718:CISC
2670:Xeon
2598:Core
2537:Atom
2487:Xeon
2482:Core
2399:Atom
2357:i486
2335:i386
2328:x86)
2280:8087
2268:FPUs
2235:8088
2229:8086
2204:8085
2198:8080
2192:8008
2171:4040
2165:4004
2131:Xeon
2099:Core
2084:Atom
1916:Core
1864:x86)
1817:Xeon
1780:Core
1733:Atom
1424:2023
1397:2019
1365:2019
1332:2022
1306:2022
1238:CNET
1160:2016
933:ISBN
886:Labs
796:and
699:SIMD
559:128
462:code
406:and
400:SuSE
384:CERN
350:and
348:Unix
333:MIPS
331:and
323:and
283:CISC
85:Type
79:EPIC
68:2001
57:Bits
49:and
18:Ia64
2808:Arc
2793:GMA
2542:SoC
2460:III
2450:Pro
2409:SoC
2372:DX4
2367:DX2
2345:376
2264:x87
2216:x86
2152:BCD
2006:ULV
2003:x86
1758:III
1748:Pro
923:doi
794:x86
746:bus
611:bsp
566:NaN
427:pun
396:SGI
155:128
2862::
2803:Xe
2547:CE
2455:II
2404:CE
2377:SL
2362:SX
2350:EX
2340:SX
1876:P6
1871:P5
1805:i9
1800:i7
1795:i5
1790:i3
1753:II
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884:HP
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648:pr
597:br
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577:fr
570:fr
551:gr
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386:,
382:,
370:,
366:,
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2663:M
2603:2
2581:D
2576:4
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2427:D
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