List of discontinued x86 instructions

1355:

The selected AVX512 vector register is then interpreted as a vector of indexes, causing the standard x86 base+index+displacement address calculation to be performed for each vector lane, causing one associated memory operation (prefetches in case of the AVX512PF instructions) to be performed for each active lane. The instruction encodings all follow a pattern where:

4704:

The TBM instructions are all encoded using the XOP prefix. They are all available in 32-bit and 64-bit forms, selected with the XOP.W bit (0=32bit, 1=64bit). (XOP.W is ignored outside 64-bit mode.) Like all instructions encoded with VEX/XOP prefixes, they are unavailable in Real Mode and Virtual-8086

5797:

The first argument specifies a V25/V35 Special Function Register to test a bit in. The second argument specifies a bit position in that register. The third argument specifies a short branch offset. If the bit was set to 1, then it is cleared and a short branch is taken, else the branch is not taken.

1612:

The AVX512_4VNNIW instructions read a 128-bit data item from memory, containing 4 two-component vectors (each component being signed 16-bit). Then, for each of 4 consecutive AVX-512 registers, they will, for each 32-bit lane, interpret the lane as a two-component vector (signed 16-bit) and perform a

1354:

The AVX512PF instructions are a set of 16 prefetch instructions. These instructions all use VSIB encoding, where a memory addressing mode using the SIB byte is required, and where the index part of the SIB byte is taken to index into the AVX512 vector register file rather than the GPR register file.

4379:

were originally defined by Intel in early drafts of the AVX specification − they were removed in later drafts and were never implemented in any Intel processor. They were, however, implemented by AMD, who designated them as being a part of the XOP instruction set extension. (Like the other parts of

5469:

Perform a bitfield read from memory. DS:SI (DS0:IX in NEC nomenclature) points to memory location to read from, first argument specifies bit-offset to read from, and second argument specifies the number of bits to read minus 1. The result is placed in AX. After the bitfield read, SI and the first

5500:

Perform a bitfield write to memory. ES:DI (DS1:IY in NEC nomenclature) points to memory location to write to, AX contains data to write, first argument specifies bit-offset to write to, and second argument specifies the number of bits to write minus 1. After the bitfield write, DI and the first

6791:

These instructions are integer SIMD instructions acting on 64-bit vectors in MMX registers or memory. Each instruction takes two explicit operands, where the first one is an MMX register operand and the second one is either a memory operand or a second MMX register. In addition, several of the

3065:

For XOP vector instructions, W is used to swap the last two vector source arguments to the instruction. For instructions that allow W=1, encodings with W=0 allow the second-to-last vector argument to be a memory argument, while encodings with W=1 allow the last vector argument to be a memory

2867:

SSE5 was a proposed SSE extension by AMD, using a new "DREX" instruction encoding to add support for new 3-operand and 4-operand instructions to SSE. The bundle did not include the full set of Intel's SSE4 instructions, making it a competitor to SSE4 rather than a successor.

851:

processors, codenamed "Knights Corner" (KNC), supported a large number of instructions that are not seen in any later x86 processor. An instruction reference is available − the instructions/opcodes unique to KNC are the ones with VEX and MVEX prefixes (except for the

5084:

Decrement the event counter associated with the programmed value sample event. If the resulting counter value ends up negative, insert an event record with EventID=1 in LWP ring buffer. (The instruction arguments are inserted in this record in the same way as for

924:

subsets "AVX512ER", "AVX512_4FMAPS", "AVX512PF" and "AVX512_4VNNIW", all of which are unique to the Xeon Phi series of processors. The ER and PF subsets were introduced in "Knights Landing" − the 4FMAPS and 4VNNIW instructions were later added in "Knights Mill".

7263:

The C&T F8680 PC/Chip is a system-on-a-chip featuring an 80186-compatible CPU core, with a few additional instructions to support the F8680-specific "SuperState R" supervisor/system-management feature. Some of the added instructions for "SuperState R" are:

5652:

Jump to an address picked from the IVT using the imm8 argument. Enables a simple memory paging mechanism after reading the IVT but before executing the jump. The paging mechanism uses an on-chip page table with 16Kbyte pages and no access rights checking.

1613:

dot-product with the corresponding two-component vector that was read from memory (the first two-component vector from memory is used for the first AVX-512 source register, and so on). These results are then accumulated into a destination vector register.

7110:

Condition is evaluated on a per-byte-lane basis, by comparing byte lanes in the implied source to zero (with signed compare) − if the comparison passes, then the corresponding destination lane is loaded from memory, otherwise it keeps its original value.

4253:

instruction, a series of alias mnemonics are available for the instruction, one for each of the eight comparison functions encodable in the imm8 argument. These alias mnemonics specify the comparison to perform after the "VPCOM" part of the mnemonic. For

4094:

Shift-amount is provided on a per-vector-lane basis, and is taken from the bottom 8 bits of each lane of the last source argument. The shift-amount is considered signed − a positive value will cause left-shift, while a negative value causes right-shift.

5008:

Loading an address of 0 disables LWP. Loading a nonzero address will cause the CPU to perform validation of the specified LWPCB, then enable LWP if the validation passed. If LWP was already enabled, state for the previous LWPCB is flushed to memory.

7976:

Multiply 4-component vector with 4x4 matrix. For proper operation, the matrix must be preloaded into Coprocessor Register banks 1 and 2 (unique to IIT FPUs), and the vector must be loaded into Coprocessor Register Bank 0. Example code is available.

8183: 3687:

For src1 and src2, the factors to multiply may be taken as signed values from the low half of each lane, high half of each lane or the lane in full (picked in the same way for src1 and src2) − the addend and the result use the full lane.

5898:

segment registers except that they are left-shifted by 8 rather than 4, enabling access to 16MB of memory. Block transfer instructions, such as MOVBKW, can access the 16MB memory space by simultaneously prefixing with DS2 and DS3.

5376:

Performs a string addition of integers in packed BCD format (2 BCD digits per byte). DS:SI points to a source integer, ES:DI to a destination integer, and CL provides the number of digits to add. The operation is then:

339:

Intel MPX adds 4 new registers, BND0 to BND3, that each contains a pair of addresses. MPX also defines a bounds-table as a 2-level directory/table data structure in memory that contains sets of upper/lower bounds.

5431:

Concatenates its 8-bit argument with the bottom 4 bits of AL to form a 12-bit bitvector, then left-rotates this bitvector by 4 bits, then writes this bitvector back to its argument and the bottom 4 bits of AL.

8179: 7314:

C&T also developed a 386-compatible processor known as the Super386. This processor supports, in addition to the basic Intel 386 instruction set, a number of instructions to support the Super386-specific

758:(11th generation mobile Core processors), but were never officially supported on any other Intel processors - they are now considered deprecated and are listed in the Intel SDM as removed from 2023 onwards. 9243: 5158:

These instructions are specific to the NEC V20/V30 CPUs and their successors, and do not appear in any non-NEC CPUs. Many of their opcodes have been reassigned to other instructions in later non-NEC CPUs.

259:

These instructions are only present in the x86 operation mode of early Intel Itanium processors with hardware support for x86. This support was added in "Merced" and removed in "Montecito", replaced with

1718:

without a valid license, resulting in a lawsuit that AMD lost in late 1994. As a result of this loss, the ICE microcode was removed from all later AMD CPUs, and the SMM instructions removed with it.

2871:

AMD chose not to implement SSE5 as originally proposed − it was instead reworked into FMA4 and XOP, which provided similar functionality but with a quite different instruction encoding − using the

1362:

The bottom bit of the opcode is used to indicate whether the AVX512 index register is considered a vector of sixteen signed 32-bit indexes (bit 0 not set) or eight signed 64-bit indexes (bit 0 set)

8717: 5593:

escape opcodes, but uses them to encode an instruction set that is unique to the 72291 and not compatible with x87. A listing of the opcodes/instructions supported by the 72291 is available.

3258:

For each vector-register lane, compare src1 to src2, then set destination to all-1s if the comparison passes, all-0s if it fails. The imm8 argument specifies comparison function to perform:

1677:, prefetch into L2 cache with intent to write) − these were the only Intel CPUs to officially support this instruction, but it continues to be supported on some non-Intel processors (e.g. 8607: 7846:

Instruction to signal to the FPU that the main CPU is exiting protected mode, similar to how the FSETPM instruction is used to signal to the FPU that the CPU is entering protected mode.

5091:

Executes as NOP if LWP is not enabled or if the event counter is not enabled. If no event record is inserted, then the second argument (which may be a memory argument) is not accessed.

3949:

Rotation amount is given in the last source argument. It may be provided as an immediate or a vector register − in the latter case, the rotation amount is provided on a per-lane basis.

2302: 7696:

series of embedded microcontrollers feature a 386SX-class CPU core with a few M6117-specific additions to the Intel 386 instruction set. The ones documented for DM&P M6117D are:

9009: 8416: 6361:("Joshua" core only, not "Samuel") and a few SoCs such as STPC ATLAS and ZFMicro ZFx86. Many of these opcodes have been reassigned to other instructions in later non-Cyrix CPUs. 3620:

For each N-bit lane, split the lane into two signed sub-lanes of N/2 bits each, then subtract the upper lane from the lower lane, then store the result as a signed N-bit result.

8248: 3422:

For each N-bit lane, split the lane into a series of M-bit lanes, add the M-bit lanes together, then store the result into the destination as an N-bit zero/sign-extended value.

8822: 2258: 1898:

components in a 64-bit vector register). The instructions were mainly promoted by AMD, but were supported on some non-AMD CPUs as well. The processors supporting 3DNow! were:

7236:

instruction, however its opcode and function differ (the EMMI instruction right-shifts its multiply-result by 15 bits, while the 3DNow! instruction right-shifts by 16 bits).

6353:

These instructions are present in Cyrix CPUs as well as NatSemi/AMD Geode CPUs derived from Cyrix microarchitectures (Geode GX and LX, but not NX). They are also present in

2553:

instruction, however its opcode and function differ (the EMMI instruction right-shifts its multiply-result by 15 bits, while the 3DNow! instruction right-shifts by 16 bits).

743:

prefix may have other meanings). When used with such instructions during hardware lock elision, will end the associated transaction instead of performing the store/atomic.

86: 2778:

in K6-2 would set the top 16 bits of each 32-bit result lane to all-0s, while the documented variant in later processors would sign-extend the 16-bit result to 32 bits.

8589: 7802:

Several 80387-class floating-point coprocessors provided extra instructions in addition to the standard 80387 ones − none of these are supported in later processors:

1217: 1107: 1032: 8166: 1187: 9230: 3910:, src2:src1 are considered a 32-element vector of bytes. For each byte-lane, the byte in src3 is used to index into this 32-byte vector and transform the element: 8917: 9342: 878:) in 2023, some of the old KNC MVEX instruction encodings have been reused for new APX encodings. For example, both KNC and APX accept the instruction encoding 8505: 8192: 5842:

Jump to an address picked from the IVT using the imm8 argument, and then continue execution with "Software Guard" enabled. The "Software Guard" is an 8-bit

103:

processors, but where the processor series containing the instructions are discontinued or superseded, with no known plans to reintroduce the instructions.

3858:

For each 32-bit lane, treat src1 and src2 as 2-component vectors of signed 16-bit values, then compute their dot-product, then add src3 as a 32-bit value.

8446: 831:

Store, in an even/odd pair of mask registers, the indicators of the locations of value matches between 64-bit lanes in the two vector source arguments.

804:

Store, in an even/odd pair of mask registers, the indicators of the locations of value matches between 32-bit lanes in the two vector source arguments.

9040: 3069:

For XOP-encoded integer-register instructions (the TBM and LWP instruction set extensions, see below), W is used for operand size. (0=32-bit, 1=64-bit)

1821:

Takes a pointer in ES:EDI to a processor save state to resume from − this save state has format nearly identical to that of the undocumented Intel 386

8721: 8369:, (vol 8, no.7, May 30, 1994) — describes the UMC U5S as having "built-in SMM, which is hardware- and software-compatible with AMD’s implementation." 8266: 8794: 6764:

v0.98.31 and later uses /0 for these instructions, while sandpile.org's opcode tables indicate that the reg field is ignored for these instructions.

682: 9099: 47: 8912:

NEC V55SC 16-bit Microprocessor Preliminary Data Sheet (O.D.No ID-8206A, March 1993), pages 70 and 127. Located on Apr 20, 2022 by searching for

9183: 8614: 53: 8433: 724:

prefix may have other meanings). When used with such instructions, may start a transaction instead of performing the memory atomic operation.

3086:

is an embedded prefix − nominally 0/1/2/3=none/66h/F2h/F3h, but only 0 was ever used with any of the instructions defined for the XOP prefix.

8844: 8103: 8062:

instruction can be executed not just on the Intel 387SL FPU but on the Intel 387SX as well - executing the instruction immediately after an

8764: 8639: 8370: 739:

Instruction prefix to indicate end of hardware lock elision, used with memory atomic/store instructions only (for other instructions, the

8951: 8213: 941:

The instructions all support result masking by opmask registers. The AVX512ER instructions also all support broadcast of memory operands.

864:

instructions − these are kept with the same opcodes and function in AVX-512, but with an added "W" appended to their instruction names).

9005: 8781: 8576: 8977: 8856: 8806: 8400: 8244: 720:

Instruction prefix to indicate start of hardware lock elision, used with memory atomic instructions only (for other instructions, the

5674:

Jump to an address picked from the IVT using the imm8 argument. Disables paging after reading the IVT but before executing the jump.

9569: 9335: 9311: 8818: 8353: 8297: 4691: 72: 9141: 874:

Early versions of AVX-512 avoided the instruction encodings used by KNC's MVEX prefix, however with the introduction of Intel APX (

4979:

These instructions are available in Ring 3, but not available in Real Mode and Virtual-8086 mode. All of them use the XOP prefix.

9225:

Intel "Intel387 SL Mobile Math Coprocessor" (feb 1992, order no 290427-001), appendix A. Located on Jan 7, 2022 by searching for

8526: 8387: 8212:(vol 6, no. 8, june 17, 1992) − includes a listing of the AMD/Cyrix SMM opcodes and the C&T Super386 "SuperState V" opcodes. 4973: 4701:

line of processors; later AMD Jaguar and Zen-based processors do not support TBM. No Intel processors (as of 2023) support TBM.

8136: 8900: 529:

prefix is ignored for the MPX instructions − address size is always 64-bit. These behaviors are unique to the MPX instructions.

9200: 9383: 8964: 8460: 6788:

and Geode GX1 processors. (In later non-Cyrix processors, all of their opcodes have been used for SSE or SSE2 instructions.)

3077:

is an extra source register argument, normally the first non-r/m source argument for instructions with ≥3 register arguments.

8593: 8475: 2616:). These instructions, unlike the rest of 3DNow!, are not discontinued but continue to be supported on modern AMD CPUs. The 79: 8742: 5047:

Insert user event record with EventID=255 in LWP ring buffer. The arguments are inserted into the event record as follows:

521:

For all of the MPX instructions, 16-bit addressing is disallowed − this effectively makes the address-size override prefix

8180:

Reference Implementations for Intel® Architecture Approximation Instructions VRCP14, VRSQRT14, VRCP28, VRSQRT28, and VEXP2

6715:

as a destination register is only supported on NatSemi Geode GX2 and AMD Geode GX/LX - on other processors, it causes #UD.

5125:

converts it back by subtracting the DS base address. Changing the DS base address while LWP is enabled will thereby cause

4965: 4396: 2625: 1919: 41: 8285: 9328: 8678: 5589:

The FPO2 escape opcodes are used by the NEC 72291 floating-point coprocessor - this coprocessor also uses the standard

9154: 2217:

instructions − instead, it imposes requirements on the results of using these instructions together in specific ways:

507:

Instruction prefix used with certain branch instructions to indicate that they should not clear the bounds registers.

329: 8934: 8162: 8509: 371:

The lower bound is given by base component of address, the upper bound by 1-s complement of the address as a whole.

8539: 8189: 7219:

instructions, the second explicit operand is required to be a memory operand − register operands are not supported.

5846:

that, during instruction fetch/decode, translates opcode bytes using a 256-entry lookup table stored in an on-chip

1923: 6068:

1704:

were introduced in the Am386SXLV and Am386DXLV processors. They were also present in the later Am486SXLV/DXLV and

9564: 9439: 3066:

argument. For instructions that don't allow their last two vector arguments to be swapped, W is required to be 0.

1949: 928:

The ER and 4FMAPS instructions are floating-point arithmetic instructions that all follow a given pattern where:

685:

is marked in the Intel SDM as removed from 2019 onwards. This feature took the form of two instruction prefixes,

582:

instructions produce a #BR exception if bounds directory entry is not valid (which prevents address translation).

9303: 9057: 8989: 2518:

instructions would instead compute their results with full 24-bit precision − this made it possible to turn the

9538: 9408: 9368: 8149: 8083: 5579:"Floating Point Operation 2": extra escape opcodes for floating-point coprocessor, in addition to the standard 904: 653:

prefix will clear all four bounds registers. (Other branch instructions − such as e.g. far jumps, short jumps (

35: 26: 2278: 8302:

Covers instruction set additions of Am486SXLV on page 210, Cyrix 486S on page 273 and IBM 386SLC on page 298.

5619:

Jump to an address picked from the IVT (Interrupt Vector Table) using the imm8 argument, similar to the 8086

9533: 9036: 6004:

Instructions to load both extended segment register and general-purpose register at once, similar to 8086's

4400: 2896:

The XOP instructions mostly make use of the XOP prefix, which is a 3-byte prefix with the following layout:

2887: 1927: 9213: 8327: 3080:

L is a vector length specifier. L=1 indicates 256-bit operation, L=0 indicates scalar or 128-bit operation.

8262: 7256: 6792:

instructions take an implied operand, which is an MMX register implied from the first operand as follows:

4698: 3917:

bits 7:6 specify a transform to perform on the byte (0=keep, 1=bitreverse, 2=set-to-zero, 3=replicate-MSB)

2261: 1701: 8869: 8339:

Hans Peter Messmer, "The Indispensable PC Hardware Book" (ISBN 0201403994), chapter 10.6.1, pages 280-281

5820:

instruction in that the clock is stopped too, so that an NMI or CPU reset is needed to resume operation.

649:). If the BNDPRESERVE config bit is not set, then executing any of these branch instructions without the 562:

instructions requires memory addressing modes that use the SIB byte − non-SIB addressing modes cause #UD.

9457: 9398: 9095: 261: 2236: 492:

Store bounds into the bounds-table, using address translation using an sib-addressing expression mib.

9124: 1712: 477:

Load bounds from the bounds-table, using address translation using an sib-addressing expression mib.

9179: 9433: 8429: 7685: 5843: 4388: 2879: 693:, that could be attached to memory atomics/stores to elide the memory locking that they represent. 6699:

is not a Cyrix-specific instruction, and it continues to exist in modern non-Cyrix x86 processors.

2875:

for the FMA4 instructions and the new VEX-like XOP prefix for most of the remaining instructions.

9528: 8840: 8263:"Case No.C-93-20301 PVT, Findings of fact and conclusions of law following "ICE" module of trial" 5694:

Transfer both SS and SP of old register bank after the bank has been switched by an interrupt or

4406: 1746: 935:

The bottom opcode bit is used to select between packed and scalar operation (0: packed, 1:scalar)

216: 8760: 8226: 6523:

Cyrix 486S and later processors - not available on older Cyrix 486SLC/DLC/SRx2/DRx2 processors.

5716:

Perform software interrupt with context switch to register bank specified by low 3 bits of r16.

3025:

is an opcode-map specifier. While capable of encoding values from 8 to 31 (values 0 to 7 map to

9285: 8654: 8366: 9445: 9363: 9307: 9024: 8947: 8349: 8293: 8209: 6761: 6725: 6346: 4297:

XOP also included two vector instructions that used the VEX prefix instead of the XOP prefix:

1956: 8777: 8564: 5776:

Transfer SS and SP of current register bank to register bank indicated by low 3 bits of r16.

5121:

converts this effective-address to a linear-address by adding the DS base address to it, and

1192: 1082: 1007: 5847: 99:

Instructions that have at some point been present as documented instructions in one or more

9082: 8679:"AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and System Instructions" 8132: 2158:

Converts packed floating-point operand to packed 32-bit signed integer, with round-to-zero

1165: 9523: 9451: 9378: 8550:

on pages 411 and 420, as well as FMA4 instructions on pages 612 to 660. Archived from the

8447:"Windows 10 64-bit requirements: Does my CPU support CMPXCHG16b, PrefetchW and LAHF/SAHF?" 8234:, publication #21020, rev A, apr 1997 − has SMM instruction descriptions on pages 5 and 6. 7693: 7677: 7238:

Some assemblers/disassemblers, such as NASM, resolve this ambiguity by using the mnemonic

2555:

Some assemblers/disassemblers, such as NASM, resolve this ambiguity by using the mnemonic

2480:

The 3DNow! precision requirements can be fulfilled in several different ways, for example:

1894:, mainly adding support for floating-point SIMD instructions using the MMX registers (two 5894:

The DS2 and DS3 registers (which are specific to the NEC V55) act similar to regular x86

4972:. On all supported CPUs, the latest available microcode updates have disabled LWP due to 9137: 8119: 4526:

Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values

4513:

Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values

4500:

Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values

4487:

Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values

938:

For a given operation, all the scalar/packed variants belong to the same AVX-512 subset.

9513: 9496: 9491: 9481: 9416: 9393: 9167: 9070: 7078:

Packed signed word multiply high with rounding and accumulation to implied destination:

2496: 867:

Most of these KNC-unique instructions are similar but not identical to instructions in

122:

The following instructions were introduced in the Intel 80386, but later discontinued:

9258: 8522: 8383: 9558: 9501: 9427: 9196: 9112: 7429:

Read from bank 1 of the register file (includes visible and invisible CPU registers)

6989:

Packed unsigned byte distance and accumulate to implied destination, with saturation:

5064:

instruction sets CF=1 if LWP is enabled and the ring buffer is full, CF=0 otherwise.

3019:

The R/X/B bits are argument extension bits similar to the RXB bits of the REX prefix.

2667:

Packed 32-bit floating-point to 16-bit signed integer conversion, with round-to-zero

1873: 210: 8890: 2530:

instructions into pure data movement instructions, performing the same operation as

1347:

For the AVX512ER instructions, a numerically exact reference is available as C code.

9388: 9373: 6773: 5056:

The low 16 bits of the imm32 are stored in bytes 3:2 (the high 16 bits are ignored)

9226: 7291:

Load datum into F8680 "CREG" configuration register (AH=register-index, AL=datum)

2205:

The 3DNow! specification does not directly specify the operation performed by the

8523:

AMD64 Architecture Programmer’s Manual Volume 6: 128-Bit and 256-Bit XOP and FMA4

8483: 4682:

Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values

4669:

Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values

4656:

Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values

4643:

Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values

1663:

Dot-product of signed words with dword accumulation and saturation, 4 iterations

8913: 3043: 2428:

Multiply signed packed 16-bit integers with rounding and store the high 16 bits:

2320:

Floating-point reciprocal square root approximation (at least 15 bit precision):

1944:(both "Joshua" and "Samuel" variants), and the "Samuel" and "Ezra" revisions of 1705: 333: 220: 173: 2585:

makes the FP/MMX register contents undefined after the instruction is executed.

2379:

Packed floating-point reciprocal/reciprocal square root, second iteration step

9486: 9476: 5624: 5614: 2872: 2637: 2175:

Packed 32-bit signed integer to floating-point conversion, with round-to-zero

1903: 1855: 761:

As of July 2024, the VP2INTERSECT instructions have been re-introduced on AMD

755: 9270: 6756:

instructions, Cyrix's documentation specifies that the instruction accepts a

5117:

is an effective-address, specified relative to the DS: segment base address.

9506: 8693: 8014:

Round st(0) to integer, with round-to-nearest ties-away-from-zero rounding.

6393:

Save segment register and descriptor to memory as a 10-byte data structure.

6358: 6127:

Bit test and clear for second bank of special purpose registers (similar to

5895: 4630:

Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values

4617:

Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values

4604:

Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values

4591:

Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values

2772:

instructions also existed as undocumented instructions on the original K6-2.

2268:

PFRSQRT mm1,mm0 MOVQ mm2,mm1 PFMUL mm1,mm1 PFRSQIT1 mm1,mm0 PFRCPIT2 mm1,mm2

2223:

initially contains a value X in FP32 format, then the instruction sequence:

1941: 1715: 542:

in 64-bit mode, RIP-relative addressing is not permitted and will cause #UD.

525:

mandatory in 16-bit mode and prohibited in 32-bit mode. In 64-bit mode, the

323: 8567:, order no. 319433-004, December 2008 − does not contain specifications of 6395:

The first 8 bytes are the descriptor, the last two bytes are the selector.

332:

CPUs. The last CPU generation to support them was the 9th generation Core "

8930: 8163:

Intel® Xeon Phi™ Coprocessor Instruction Set Architecture Reference Manual

6091:

Count Trailing Zeroes and store result in CL. Sets ZF=1 for all-0s input.

2499:

iteration to improve the precision of a low-precision initial result from

1948:. (Later VIA CPUs, from C3 "Nehemiah" onwards, dropped 3DNow! in favor of 1359:

EVEX.W is used to specify format of the prefetchable data (0:FP32, 1:FP64)

9113:

Application Note 108 − Cyrix Extensions to the Multimedia Instruction Set

8227:"Am386®SX/SXL/SXLV High-Performance, Low-Power, Embedded Microprocessors" 2805: 917: 848: 448:

Move a pair of memory bounds to/from memory or between bounds-registers.

8551: 7010:

Packed subtract signed words with saturation, using implied destination:

4578:

Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values

4565:

Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values

4552:

Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values

4539:

Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values

7059:

Packed signed word multiply high with rounding and implied destination:

6785: 6760:

byte but does not specify the encoding of the ModR/M byte's reg field.

6635:

Read from CPU internal special register (EBX=register-index, EAX=data)

6328: 5151: 4969: 4381: 1934: 1915: 1860: 1823: 1678: 921: 868: 252: 9320: 6620:

Write to CPU internal special register (EBX=register-index, EAX=data)

3856:

Packed multiply, add and accumulate signed word to signed doubleword.

1711:

The SMM functionality of these processors was implemented using Intel

871:− later Xeon Phi processors replaced these instructions with AVX-512. 9518: 9053: 7681: 6781: 6757: 5761:

Perform task switch to register bank indicated by low 3 bits of r16.

5501:

argument are updated to point just beyond the just-written bitfield.

5050:

The first argument is stored in bytes 23:16 (zero-extended if 32-bit)

3026: 2633: 1945: 1911: 1907: 1885: 1669:

Xeon Phi processors (from Knights Landing onwards) also featured the

754:

The VP2INTERSECT instructions (an AVX-512 subset) were introduced in

7849:

Different sources provide different encodings for this instruction.

2194:

Floating-point reciprocal approximation (at least 14 bit precision):

219:

or any later Intel CPUs (except they're present in the i486-derived

6949:

Packed add signed words with saturation, using implied destination:

6327:

Designated opcode for termination of the x86 emulation mode on the

4474:

Fused Multiply-Add of Scalar Single-Precision Floating-Point Values

4461:

Fused Multiply-Add of Scalar Double-Precision Floating-Point Values

4448:

Fused Multiply-Add of Packed Single-Precision Floating-Point Values

4435:

Fused Multiply-Add of Packed Double-Precision Floating-Point Values

2362:

Packed floating-point reciprocal square root, first iteration step

1365:

The instructions all support operation masking by opmask registers.

7795: 6354: 6342: 5470:

argument are updated to point just beyond the just-read bitfield.

5203:

First argument specifies an 8/16-bit register or memory location.

4964:

The AMD Lightweight Profiling (LWP) feature was introduced in AMD

1693: 1644:

Dot-product of signed words with dword accumulation, 4 iterations

762: 226: 107: 9008:, Feb 2009, publication ID 33234H, section 8.3.4, pages 643-657. 6041:

Segment-override prefixes for the DS2 and DS3 extended segments.

3090:

The XOP instructions encoded with the XOP prefix are as follows:

2886:

Introduced with the Bulldozer processor core, removed again from

2682:

Packed 16-bit signed integer to 32-bit floating-point conversion

665:

etc − do not clear the bounds registers regardless of whether an

9421: 8542:, order no. 319433-002, March 2008 - contains specifications of 8348:

Frank van Gilluwe, "The Undocumented PC, second edition", 1997,

8323: 5025:

Store LWPCB address to register, and flush LWP state to memory.

2860: 1895: 1891: 932:

EVEX.W is used to specify floating-point format (0=FP32, 1=FP64)

328:

These instructions were introduced in 6th generation Intel Core

115: 9324: 4409:

with four operands. FMA4 was realized in hardware before FMA3.

1890:

The 3DNow! instruction set extension was introduced in the AMD

9543: 9286:"Everything You Always Wanted To Know About Math Coprocessors" 8689: 8650: 5584: 1685: 875: 100: 8415:

perform their Newton-Raphson iterations on pages 118 to 125.

8403:, pub.no.26569, rev 3.16, Nov 2021 − provides details on how 8044:

Round st(0) to integer, with round-to-nearest-even rounding.

7384:

Return from SMM with interrupts disabled for one instruction

5873:, excepts disables "Software Guard" rather than enabling it. 7654:

Write general-purpose register or any bank of register file

2792:

instruction uses same opcode as the older undocumented K6-2

7609:

Read general-purpose register or any bank of register file

6897:

refer to the two explicit operands of the instruction, and

4349:

Permute two-source single-precision floating-point values.

4328:

Permute two-source double-precision floating-point values.

2853:

Packed Floating-point Reciprocal Square Root Approximation

369:

Make lower and upper bound from memory address expression.

169:

was moved to different opcode from 486 stepping B onwards.

9157:

contains descriptions of many of the F8680 CREG registers.

8793:

NEC 72291 FPU: an instruction listing can be found in the

8104:

Itanium Architecture Software Developer's Manual, volume 4

5006:

Load LWPCB (Lightweight Profiling Control Block) address.

2620:

instruction is also supported on Intel CPUs starting with

2592:

3DNow! also introduced a couple of prefetch instructions:

1918:

microarchitectures. (Later AMD microarchitectures such as

7308:

Read F8680 status register into AL (imm8=register-index)

5892:

Move to/from the DS2 and DS3 extended segment registers.

5129:

to return a different address than what was specified to

2466:

Faster Enter/Exit of the MMX or x87 floating-point state

2304:

in FP32 format, computed with an error of at most 1 ulp.

1079:

Reciprocal square root approximation with an accuracy of

416:

Check address against upper bound in 1's-complement form

9244:

Intel's SL Architecture: Designing Portable Applications

8247:, order no. 20665A, April 1996, section 1.9.4, page 49. 8245:Élan™SC310 Microcontroller Programmer’s Reference Manual 7723:

System management interrupt − enters "hyper state mode"

2120:

Packed floating-point comparison, greater than or equal:

1842:

Return from SMM interrupt handler (Am486SXLV/DXLV only).

8508:, pub.no. 43479, rev 3.01, Aug 2007. Archived from the 3055:

for instructions that don't take an immediate, and map

2345:

Packed floating-point reciprocal, first iteration step

1819:

Return from SMM interrupt handler (Am386SXLV/DXLV only)

400:

all produce a #BR exception if the bounds check fails.

8891:

NEC V55PI Users Manual Instruction, U10231J (Japanese)

7319:

system-management feature. The added instructions for

3920:

bit 5, if set, inverts the result after the transform.

3033:

instruction, making them unusable for XOP), only maps

1561:

Prefetch into L2 cache (T1 hint) with intent to write

1511:

Prefetch into L1 cache (T0 hint) with intent to write

8743:

x86/svm: Drop support for AMD's Lightweight Profiling

8070:

on 387SX, but a nonzero signature value on the 387SL.

8029:

Round st(0) to integer, with round-to-zero rounding.

7108:

Packed conditional load from memory to MMX register.

5552:

Repeat if not carry. Instruction prefix for use with

2281: 2239: 1343: 1341: 1339: 1195: 1168: 1085: 1010: 8106:, (document number: 323208, revision 2.3, May 2010). 6889:

In the instruction descriptions in the below table,

6425:

Restore segment register and descriptor from memory

6401:

Not present on stepping A of Cx486SLC and Cx486DLC.

5731:

Return from register bank context switch interrupt.

3125:

Extract fractional portion of floating-point value.

2549:

instruction has the same mnemonic as the Cyrix EMMI

2260:

in FP32 format, computed with an error of at most 1

2123:

dst <- (dst >= src) ? 0xFFFFFFFF : 0

215:

Present in Intel 386 and 486 − not present in Intel

159:

Discontinued from revision B1 of the 80386 onwards.

9467: 9407: 9356: 9140:contains some F8680 instruction macros on page 34. 8841:

NEC V55PI 16-bit microprocessor Data Sheet, U11775E

7187:

instruction treats the bytes as signed or unsigned.

3051:for instructions that take an 8-bit immediate, map 2741:

Packed Floating-Point Positive-Negative Accumulate:

2142:

dst <- (dst > src) ? 0xFFFFFFFF : 0

1764:Move data between registers and main system memory 9020: 9018: 8857:NEC 16-bit V-series Microprocessor Data Book, 1991 8819:Renesas Data Sheet MOS Integrated Circuit uPD70320 8807:NEC 16-bit V-series Microprocessor Data Book, 1991 7955:Select Coprocessor Register Bank 3 (undocumented) 6971:if (abs(arg2) > abs(arg1)) then arg1 <- arg2 6744: 6742: 6519:encoding on Cyrix 6x86MX, MII, MediaGX and Geode. 2296: 2252: 1211: 1181: 1101: 1026: 9000: 8998: 6784:and MII processors, and were also present in the 5529:Repeat if carry. Instruction prefix for use with 4753:(src >> start) & ((1 << len) − 1) 3224:dst <- (src1 AND src3) OR (src2 AND NOT(src3)) 2104:dst <- (dst == src) ? 0xFFFFFFFF : 0 920:"Knights Landing" and later models belong to the 912:"Knights Landing" and "Knights Mill" instructions 8565:Advanced Vector Extensions Programming Reference 8540:Advanced Vector Extensions Programming Reference 7232:instruction has the same mnemonic as the 3DNow! 6780:These instructions were introduced in the Cyrix 6695:; Return from System Management mode), however, 6404:Present on Cx486SLC/e and all later Cyrix CPUs. 5027:If LWP is not enabled, the stored address is 0. 2893:A revision of most of the SSE5 instruction set. 1854:These SMM instructions were also present on the 1749:bit 12 is set; not available on Am486SXLV/DXLV) 884:as valid, but assign different meanings to it: 8835: 8833: 8831: 8608:"New "Bulldozer" and "Piledriver" instructions" 8401:AMD64 Architecture Programmer’s Manual Volume 5 8280: 8278: 8276: 8114: 8112: 7038:Packed signed word multiply high with rounding: 4952:, a register form is available as part of BMI1. 2836:Packed Floating-point Reciprocal Approximation 2226:PFRCP mm1,mm0 PFRCPIT1 mm0,mm1 PFRCPIT2 mm0,mm1 2139:Packed floating-point comparison, greater than: 903:- vector load with one of the new APX extended- 9039:at SourceForge, see sections B.275 and B.331. 8506:AMD64 Technology: 128-bit SSE5 Instruction Set 8470: 8468: 7081:imp <- imp + ((arg1*arg2+0x4000)>>15) 4403:. Not supported by any Intel chip as of 2023. 4395:Supported in AMD processors starting with the 4245: 4243: 4241: 4239: 4237: 4235: 4233: 4231: 3059:for instructions that take a 32-bit immediate. 2760: 2758: 2495:instructions would perform various parts of a 2085:dst <- (dst < src) ? dst : src 2066:dst <- (dst > src) ? dst : src 9336: 8613:. Advanced Micro Devices, Inc. Archived from 8122:, order no. 253665-083, mar 2024, chapter 2.5 7203: 7201: 7199: 7197: 7195: 7193: 6992:imp <- saturate_u8(imp + (abs(arg1-arg2))) 6510:encoding on Cyrix 486, 5x86, 6x86 and ZFx86. 5206:Second argument specifies which bit to test. 5105: 5103: 4697:AMD introduced TBM together with BMI1 in its 3914:bits 4:0 is used to pick one of the 32 bytes. 1004:Reciprocal approximation with an accuracy of 80: 8: 9304:PC Magazine Programmer's Technical Reference 9259:IIT 3c87 Advanced Math CoProcessor Data Book 8755: 8753: 8751: 8204: 8202: 5452:, except performs a right-rotate by 4 bits. 2431:dst <- ((dst * src) + 0x8000) >> 16 1368:The only supported vector width is 512 bits. 944:The only supported vector width is 512 bits. 838:Instructions specific to Xeon Phi processors 550: 548: 8795:HP 64873 V-series Cross Assembler Reference 8318: 8316: 8314: 8312: 8310: 8308: 7414:Load one of the six interrupt or I/O traps 6968:Packed signed word magnitude maximum value: 2398:Floating-point accumulate (horizontal add): 993:Xeon Phi specific instructions (ER, 4FMAPS) 820:VP2INTERSECTQ k1+1, zmm2, zmm3/m512/m64bcst 816:VP2INTERSECTQ k1+1, ymm2, ymm3/m256/m64bcst 811:VP2INTERSECTQ k1+1, xmm2, xmm3/m128/m64bcst 793:VP2INTERSECTD k1+1, zmm2, zmm3/m512/m32bcst 789:VP2INTERSECTD k1+1, ymm2, ymm3/m256/m32bcst 784:VP2INTERSECTD k1+1, xmm2, xmm3/m128/m32bcst 570: 568: 9343: 9329: 9321: 8965:TI486 Microprocessor Reference Guide, 1993 8950:, june 5, 2005, section 2.2.6.3, page 76. 8948:ZFx86 System-on-a-chip Data Book 1.0 Rev D 7639:Read from extra bank of the register file 7148:if (imp < 0) then arg1 <- arg2 5053:The second argument is stored in bytes 7:4 2718:Packed Floating-Point Negative Accumulate: 2577:instruction differs from the standard MMX 2447:Average of unsigned packed 8-bit integers: 2025:Packed floating-point reverse subtraction: 1848:, but with a different save state format. 591:The branch instructions that can accept a 87: 73: 17: 9298: 9296: 9294: 9254: 9252: 8590:Recent Intel(R) AVX Architectural Changes 7399:Exit from SMM and issue a shutdown cycle 6407:Present on all Cyrix-derived Geode CPUs. 6108:Watchdog Timer Manipulation Instruction. 5869:Break and Enable Native Mode. Similar to 4092:Packed shift, with signed shift-amounts. 3062:W is used in a couple of different ways: 2282: 2280: 2240: 2238: 1200: 1194: 1173: 1167: 1090: 1084: 1015: 1009: 9280: 9278: 7804: 7698: 7325: 7266: 6903: 6794: 6685:The Cyrix SMM instructions also include 6363: 6357:from IBM, ST and TI, as well as the VIA 5161: 4981: 4809:Isolate lowest clear bit and complement 4707: 4411: 4353:VPERMIL2PS ymm1,ymm2,ymm3/m256,ymm4,imm4 4332:VPERMIL2PD ymm1,ymm2,ymm3/m256,ymm4,imm4 4299: 3092: 2898: 2811: 2642: 2624:Pentium 4, albeit executed as NOP until 2297:{\displaystyle {\frac {1.0}{\sqrt {X}}}} 2101:Packed floating-point comparison, equal: 1962: 1720: 1615: 1371: 947: 916:Some of the AVX-512 instructions in the 767: 695: 342: 266: 124: 8899:listed in macro definitions on p. 378. 8367:UMC Announces Enhanced 486SX-Compatible 8095: 8051: 7176: 7129:if (imp != 0) then arg1 <- arg2 7041:arg1 <- (arg1*arg2+0x4000)>>15 6724:Some assemblers/disassemblers, such as 6678: 6525:Not available on any Ti486 processors. 5398:destination <- destination − source 5380:destination <- destination + source 5099: 4941: 4227: 2754: 2473: 1335: 1292:Fused negate-multiply-add, 4 iterations 891:VMOVDQA32 zmm0, k0, xmmword ptr {uint8} 514: 295:Jump To Intel Itanium Instruction Set. 25: 9216:, (oct 1992, order no 290376-003) p.33 8931:uPD70616 Programmer's Reference Manual 8432:, pub.no. 33234H, Feb 2009, page 673. 7669:Write extra bank of the register file 7624:Read from bank 0 of the register file 7459:Read from bank 3 of the register file 7444:Read from bank 2 of the register file 7183:Implementations differ on whether the 7062:imp <- (arg1*arg2+0x4000)>>15 6502:System management software interrupt. 4889:Isolate lowest set bit and complement 4692:Trailing Bit Manipulation Instructions 3216:Vector per-bit-lane conditional move. 9136:Institute Of Oceanographic Sciences, 8525:, pub.no. 43479, rev 3.04, Nov 2009. 8066:will cause the instruction to return 7772:Read page address of SMI entry point 7167:if (imp >= 0) then arg1 <- arg2 6399:System Management Mode instructions. 4737:The imm32 is interpreted as follows: 2913: 2908: 2903: 2044:Packed floating-point multiplication: 1858:and its derivatives (albeit with the 1700:A handful of instructions to support 971: 966: 961: 681:The Hardware Lock Elision feature of 7: 8640:"Family 16h AMD A-Series Data Sheet" 8461:AMD 3DNow! undocumented instructions 8135:(about VP2INTERSECT), Jul 19, 2023. 7757:Set page address of SMI entry point 5623:instruction, but start executing as 3679:Vector Signed Integer Multiply-Add. 3618:Vector Integer Horizontal Subtract. 2266:Similarly, the instruction sequence: 1745:Call SMM interrupt handler (only if 1651:VP4DPWSSDS zmm1{k1}{z}, zmm2+3, m128 7938:Select Coprocessor Register Bank 2 7923:Select Coprocessor Register Bank 1 7905:Select Coprocessor Register Bank 0 7890:Store FPU Signature Register to AX 6605:Reset BLT Buffer Pointer 1 to base 6584:Reset BLT Buffer Pointer 0 to base 5816:Differs from the conventional 8086 5672:Return from Extended Address Mode. 5137:to fail to save LWP state properly. 4735:Bit field extract (immediate form) 3867:VPMADCSSWD xmm1,xmm2,xmm3/m128,xmm4 3840:VPMACSSDQH xmm1,xmm2,xmm3/m128,xmm4 3807:VPMACSSDQL xmm1,xmm2,xmm3/m128,xmm4 1632:VP4DPWSSD zmm1{k1}{z}, zmm2+3, m128 635:), and the short/near forms of the 431:Check address against upper bound. 387:Check address against lower bound. 9246:, (1993, ISBN 0-07-911336-2) p.127 9214:"Intel287 XL/XLT Math Coprocessor" 8476:"Undocumented 3DNow! Instructions" 8165:, sep 2012, order no. 327364-001. 7369:Return from SMM interrupt handler 7103:if (imp == 0) then arg1 <- arg2 6671:Return from Debug Management Mode 6569:Write SMM Header Pointer Register 4960:Lightweight Profiling instructions 4520:VFMSUBADDPS xmm0, xmm1, xmm2, xmm3 4507:VFMSUBADDPD xmm0, xmm1, xmm2, xmm3 4494:VFMADDSUBPS xmm0, xmm1, xmm2, xmm3 4481:VFMADDSUBPD xmm0, xmm1, xmm2, xmm3 3889:VPMADCSWD xmm1,xmm2,xmm3/m128,xmm4 3822:VPMACSSDD xmm1,xmm2,xmm3/m128,xmm4 3792:VPMACSSWD xmm1,xmm2,xmm3/m128,xmm4 3777:VPMACSSWW xmm1,xmm2,xmm3/m128,xmm4 3762:VPMACSDQH xmm1,xmm2,xmm3/m128,xmm4 3732:VPMACSDQL xmm1,xmm2,xmm3/m128,xmm4 2006:Packed floating-point subtraction: 1906:, and all processors based on the 894:- vector load with data conversion 14: 9155:F8680 PC/Chip System Design Guide 9096:AMD Geode GX1 Processor Data Book 8592:, 29 Jan 2009. Archived from the 8269:from the original on 10 May 2021. 7794:Instructions present in specific 7549:Read TLB data (physical address) 7013:imp <- saturate_s16(arg1-arg2) 6952:imp <- saturate_s16(arg1+arg2) 6931:arg1 <- (arg1+arg2) >> 1 6548:Read SMM Header Pointer Register 6146:Queue manipulation instructions. 5840:Break and Enable Software Guard. 3747:VPMACSDD xmm1,xmm2,xmm3/m128,xmm4 3717:VPMACSWD xmm1,xmm2,xmm3/m128,xmm4 3696:VPMACSWW xmm1,xmm2,xmm3/m128,xmm4 3016:Overlines indicate inverted bits. 1461:Prefetch into L2 cache (T1 hint) 1411:Prefetch into L1 cache (T0 hint) 8990:Cyrix 486SLC/e Data Sheet (1992) 8386:, pub.no. 21928G/0, March 2000. 8210:System Management Mode Explained 7999:Cyrix EMC87, 83s87, 83d87, 387+ 7787:Write to power control register 6650:Debug Management Mode Interrupt 6355:Cyrix manufacturing partner CPUs 5650:Break to Extended Address Mode. 5448:Rotate Right Nibble. Similar to 4909:Inverse mask from trailing ones 4676:VFNMSUBSS xmm0, xmm1, xmm2, xmm3 4663:VFNMSUBSD xmm0, xmm1, xmm2, xmm3 4650:VFNMSUBPS xmm0, xmm1, xmm2, xmm3 4637:VFNMSUBPD xmm0, xmm1, xmm2, xmm3 4624:VFNMADDSS xmm0, xmm1, xmm2, xmm3 4611:VFNMADDSD xmm0, xmm1, xmm2, xmm3 4598:VFNMADDPS xmm0, xmm1, xmm2, xmm3 4585:VFNMADDPD xmm0, xmm1, xmm2, xmm3 3405:VPCOMUQ xmm1,xmm2,xmm3/m128,imm8 3390:VPCOMUD xmm1,xmm2,xmm3/m128,imm8 3374:VPCOMUW xmm1,xmm2,xmm3/m128,imm8 3358:VPCOMUB xmm1,xmm2,xmm3/m128,imm8 2804:3DNow! instructions specific to 2450:dst <- (src+dst+1) >> 1 2323:temp <- approx(1.0/sqrt(src)) 2253:{\displaystyle {\frac {1.0}{X}}} 1251:Fused-multiply-add, 4 iterations 9138:Sonic buoy − Formatter Handbook 9054:x86 architecture 2 byte opcodes 8778:V30MZ Preliminary User's Manual 7738:Return from "hyper state mode" 7474:Load TLB with page table entry 7242:for the 3DNow! instruction and 6728:, use the instruction mnemonic 5145:Instructions from other vendors 4572:VFMSUBSS xmm0, xmm1, xmm2, xmm3 4559:VFMSUBSD xmm0, xmm1, xmm2, xmm3 4546:VFMSUBPS xmm0, xmm1, xmm2, xmm3 4533:VFMSUBPD xmm0, xmm1, xmm2, xmm3 4468:VFMADDSS xmm0, xmm1, xmm2, xmm3 4455:VFMADDSD xmm0, xmm1, xmm2, xmm3 4442:VFMADDPS xmm0, xmm1, xmm2, xmm3 4429:VFMADDPD xmm0, xmm1, xmm2, xmm3 3926:VPPERM xmm1,xmm2,xmm3/m128,xmm4 3420:Vector Integer Horizontal Add. 3343:VPCOMQ xmm1,xmm2,xmm3/m128,imm8 3328:VPCOMD xmm1,xmm2,xmm3/m128,imm8 3313:VPCOMW xmm1,xmm2,xmm3/m128,imm8 3292:VPCOMB xmm1,xmm2,xmm3/m128,imm8 3232:VPCMOV ymm1,ymm2,ymm3/m256,ymm4 3029:-encoded variants of the older 2632:3DNow+ instructions added with 2559:for the 3DNow! instruction and 2271:must fill both 32-bit lanes of 2229:must fill both 32-bit lanes of 1987:Packed floating-point addition: 876:Advanced Performance Extensions 165:in Intel 486 stepping A only − 9384:Low-level programming language 9197:M6117D : System on a chip 9115:, rev 0.93, 9 sep 1998, page 7 9073:, v1.00, Jan 25, 2000, p. 103. 8692:. October 2013. Archived from 8653:. October 2013. Archived from 8575:and has FMA3 instead of FMA4. 7564:Read TLB tag (linear address) 3818:32-bit, full-lane, saturating 3773:16-bit, full-lane, saturating 3582:4x16bit -> 64bit, unsigned 3567:2x16bit -> 32bit, unsigned 2082:Packed floating-point minimum: 2063:Packed floating-point maximum: 1: 9098:, rev 5.0, dec 2003, p. 226. 9071:Cyrix III Processor Data Book 9006:Geode LX Processors Data Book 8870:"V55PI 16-BIT MICROPROCESSOR" 8761:16-bit V-series User's Manual 8430:Geode LX Processors Data Book 8150:Zen5's AVX512 Teardown + More 7594:Store configuration register 6589:NatSemi Geode GXm, GXLV, GX1 4741:Bit 7:0 : start position 4380:XOP, they've been removed in 3834:64-bit, high-half, saturating 3803:64-bit, low-half, saturating 3788:32-bit, low-half, saturating 3681:For each N-bit lane, perform 3598:2x32bit -> 64bit, unsigned 3552:8x8bit -> 64bit, unsigned 3537:4x8bit -> 32bit, unsigned 3522:2x8bit -> 16bit, unsigned 3271:3: GE (greater-than-or-equal) 1567:EVEX.66.0F38 (C6/C7) /6 /vsib 1517:EVEX.66.0F38 (C6/C7) /5 /vsib 1467:EVEX.66.0F38 (C6/C7) /2 /vsib 1417:EVEX.66.0F38 (C6/C7) /1 /vsib 843:"Knights Corner" instructions 595:prefix are the near forms of 9180:Calling C&T SCALL safely 9168:More on the C&T Super386 9125:BYTE Magazine, november 1991 8182:, id #671685, Dec 28, 2015. 7870:Store FPU Device Word to AX 7579:Load configuration register 6457:Restore LDTR and descriptor 6211:Dedicated fax instructions. 3507:2x32bit -> 64bit, signed 3492:4x16bit -> 64bit, signed 3477:2x16bit -> 32bit, signed 2774:The undocumented variant of 7354:Call SMM interrupt handler 6587:Cyrix MediaGX and MediaGXm 6487:Restore TSR and descriptor 5627:code rather than x86 code. 5072:LWPVAL r32/64, r/m32, imm32 5035:LWPINS r32/64, r/m32, imm32 4829:Mask from lowest clear bit 4769:Fill from lowest clear bit 3683:dest <- src1*src2 + src3 3462:8x8bit -> 64bit, signed 3447:4x8bit -> 32bit, signed 3426:2x8bit -> 16bit, signed 3221:performs the equivalent of 161:Opcodes briefly reused for 9586: 9037:NASM 0.98.31 documentation 8718:"tbmintrin.h from GCC 4.8" 8322:Potemkin's Hackers Group, 8286:The Complete X86, Volume 1 7844:FPU Reset Protected Mode. 6901:to the implied operand. 5902: 5854:V25, V35 "Software Guard" 5210:All V-series except V30MZ 5209: 4214:VPSHLQ xmm1,xmm2/m128,xmm3 4199:VPSHLD xmm1,xmm2/m128,xmm3 4184:VPSHLW xmm1,xmm2/m128,xmm3 4169:VPSHLB xmm1,xmm2/m128,xmm3 4154:VPSHAQ xmm1,xmm2/m128,xmm3 4139:VPSHAD xmm1,xmm2/m128,xmm3 4124:VPSHAW xmm1,xmm2/m128,xmm3 4103:VPSHAB xmm1,xmm2/m128,xmm3 4074:VPROTQ xmm1,xmm2/m128,imm8 4059:VPROTQ xmm1,xmm2/m128,xmm3 4041:VPROTD xmm1,xmm2/m128,imm8 4026:VPROTD xmm1,xmm2/m128,xmm3 4008:VPROTW xmm1,xmm2/m128,imm8 3993:VPROTW xmm1,xmm2/m128,xmm3 3975:VPROTB xmm1,xmm2/m128,imm8 3957:VPROTB xmm1,xmm2/m128,xmm3 3707: 3704: 3678: 3441: 3438: 3419: 3265:1: LE (less-than-or-equal) 2197:temp <- approx(1.0/src) 1883: 669:prefix is present or not.) 321: 9440:Microsoft Macro Assembler 9229:at datasheetarchive.com. 8916:at datasheetarchive.com. 7998: 7996:followed by a stack pop. 7907: 7872: 7676:Instructions specific to 7255:Instructions specific to 7246:for the EMMI instruction. 7107: 7086: 7077: 7058: 7037: 7009: 6988: 6967: 6948: 6927: 6912: 6652: 6586: 6550: 6522: 6501: 6491: 6442:Save LDTR and descriptor 6398: 6341:Instructions specific to 6314: 6213: 6210: 6196: 6174: 6145: 6040: 6003: 5891: 5877: 5853: 5825: 5700: 5679: 5656: 5635: 5598: 5497: 5466: 5396:Subtract Nibble Strings. 5338: 5295: 5252: 5200: 5178: 5150:Instructions specific to 4929:Mask from trailing zeros 4869:Fill from lowest set bit 4789:Isolate lowest clear bit 4399:architecture, removed in 4114: 4111: 4091: 4087: 4054: 4021: 3988: 3968: 3952: 3946: 3942: 3908:VPPERM dst,src1,src2,src3 3903: 3899: 3879: 3876: 3855: 3851: 3674: 3639: 3636: 3617: 3613: 3415: 3303: 3300: 3255: 3251: 3219:VPCMOV dst,src1,src2,src3 3215: 3211: 3124: 3120: 3095: 3005: 2999: 2993: 2915: 2910: 2563:for the EMMI instruction. 2465: 2446: 2427: 2397: 2383: 2219:If the bottom 32 bits of 2204: 2179: 2174: 2157: 2138: 2119: 2100: 2081: 2062: 2043: 2024: 2005: 1986: 1971: 1763: 1658:EVEX.512.F2.0F38.W0 53 /r 1639:EVEX.512.F2.0F38.W0 52 /r 1603:VSCATTERPF1QPD vm64y {k1} 1594:VSCATTERPF1QPS vm64z {k1} 1585:VSCATTERPF1DPD vm32y {k1} 1576:VSCATTERPF1DPS vm32z {k1} 1553:VSCATTERPF0QPD vm64y {k1} 1544:VSCATTERPF0QPS vm64z {k1} 1535:VSCATTERPF0DPD vm32y {k1} 1526:VSCATTERPF0DPS vm32z {k1} 1387: 1380: 1377: 1374: 997: 995: 992: 973: 968: 963: 958: 953: 950: 826:EVEX.NDS.F2.0F38.W1 68 /r 799:EVEX.NDS.F2.0F38.W0 68 /r 750:VP2Intersect instructions 447: 294: 214: 172:Opcodes later reused for 158: 44:(MMX, SSE, AVX, FMA, AMX) 9570:Instruction set listings 9369:Comparison of assemblers 9314:, pages 670-672 and 710. 8980:, archived on 2004-06-04 8967:, section A.14, page 308 8933:(november 1986), p.287. 8741:Xen-devel mailing list, 8588:Intel Software Network, 8384:3DNow! Technology Manual 8084:x86 instruction listings 6472:Save TSR and descriptor 5414:Compare Nibble Strings. 4747:Bit 31:16 : ignored 4720:Equivalent C expression 4679:C4E3 WvvvvL01 7E /r /is4 4666:C4E3 WvvvvL01 7F /r /is4 4653:C4E3 WvvvvL01 7C /r /is4 4640:C4E3 WvvvvL01 7D /r /is4 4627:C4E3 WvvvvL01 7A /r /is4 4614:C4E3 WvvvvL01 7B /r /is4 4601:C4E3 WvvvvL01 78 /r /is4 4588:C4E3 WvvvvL01 79 /r /is4 4575:C4E3 WvvvvL01 6E /r /is4 4562:C4E3 WvvvvL01 6F /r /is4 4549:C4E3 WvvvvL01 6C /r /is4 4536:C4E3 WvvvvL01 6D /r /is4 4523:C4E3 WvvvvL01 5E /r /is4 4510:C4E3 WvvvvL01 5F /r /is4 4497:C4E3 WvvvvL01 5C /r /is4 4484:C4E3 WvvvvL01 5D /r /is4 4471:C4E3 WvvvvL01 6A /r /is4 4458:C4E3 WvvvvL01 6B /r /is4 4445:C4E3 WvvvvL01 68 /r /is4 4432:C4E3 WvvvvL01 69 /r /is4 4303:Instruction description 3603:VPHADDUDQ xmm1,xmm2/m128 3586:VPHADDUWQ xmm1,xmm2/m128 3571:VPHADDUWD xmm1,xmm2/m128 3556:VPHADDUBQ xmm1,xmm2/m128 3541:VPHADDUBD xmm1,xmm2/m128 3526:VPHADDUBW xmm1,xmm2/m128 3256:Vector integer compare. 3096:Instruction description 2821:Instruction description 2652:Instruction description 1972:Instruction description 1864:-like SMM return opcode 1503:VGATHERPF1QPD vm64y {k1} 1494:VGATHERPF1QPS vm64z {k1} 1485:VGATHERPF1DPD vm32y {k1} 1476:VGATHERPF1DPS vm32z {k1} 1453:VGATHERPF0QPD vm64y {k1} 1444:VGATHERPF0QPS vm64z {k1} 1435:VGATHERPF0DPD vm32y {k1} 1426:VGATHERPF0DPS vm32z {k1} 969:FP64 instructions (W=1) 964:FP32 instructions (W=0) 27:x86 instruction listings 9083:Cyrix MediaGX Data Book 8365:Microprocessor Report, 8208:Microprocessor Report, 6798:First explicit operand 4269:VPCOMB xmm1,xmm2,xmm3,4 3664:VPHSUBDQ xmm1,xmm2/m128 3649:VPHSUBWD xmm1,xmm2/m128 3628:VPHSUBBW xmm1,xmm2/m128 3511:VPHADDDQ xmm1,xmm2/m128 3496:VPHADDWQ xmm1,xmm2/m128 3481:VPHADDWD xmm1,xmm2/m128 3466:VPHADDBQ xmm1,xmm2/m128 3451:VPHADDBD xmm1,xmm2/m128 3430:VPHADDBW xmm1,xmm2/m128 3280:6: FALSE (always-false) 2888:Zen (microarchitecture) 2697:Packed Swap Doubleword: 1955:National Semiconductor 1388:64-bit indexes (opcode 1381:32-bit indexes (opcode 1300:EVEX.F2.0F38 (AA/AB) /r 1259:EVEX.F2.0F38 (9A/9B) /r 1212:{\displaystyle 2^{-23}} 1116:EVEX.66.0F38 (CC/CD) /r 1102:{\displaystyle 2^{-28}} 1041:EVEX.66.0F38 (CA/CB) /r 1027:{\displaystyle 2^{-28}} 62:(e.g. 3DNow!, MPX, XOP) 9025:Cyrix 6x86MX Data Book 8606:Hollingsworth, Brent. 7257:Chips and Technologies 6189:Put CPU in idle mode. 4744:Bit 15:8 : length 4358:VEX.NP.0F3A 48 /r /is4 4337:VEX.NP.0F3A 49 /r /is4 4306:Instruction mnemonics 3904:Packed Permute Bytes. 3401:Unsigned 64-bit lanes 3386:Unsigned 32-bit lanes 3369:Unsigned 16-bit lanes 3153:VFRCZPD ymm1,ymm2/m256 3132:VFRCZPS ymm1,ymm2/m256 3099:Instruction mnemonics 2298: 2254: 1959:; AMD Geode GX and LX. 1930:do not support 3DNow!) 1708:SC300/310 processors. 1702:System Management Mode 1213: 1183: 1103: 1028: 639:instructions (opcodes 245:Move to test register 38:(integer, system, x87) 9458:Open Watcom Assembler 9399:x86 assembly language 9271:Hamarsoft 86BUGS List 8797:, pages F-31 to F-34. 8290:MicroDesign Resources 7762:(mnemonic not listed) 6928:Packed average bytes: 6551:Cyrix 6x86MX and MII 5133:, and may also cause 4849:Set lowest clear bit 3354:Unsigned 8-bit lanes 3283:7: TRUE (always-true) 3195:VFRCZSD xmm1,xmm2/m64 3174:VFRCZSS xmm1,xmm2/m32 2510:On AMD Geode LX, the 2299: 2255: 1872:), as well as on the 1317:V4FNMADDSS x,x+3,m128 1308:V4FNMADDPS z,z+3,m128 1214: 1184: 1182:{\displaystyle 2^{x}} 1142:VRSQRT28PD z,z,z/m512 1124:VRSQRT28PS z,z,z/m512 1104: 1029: 847:The first generation 677:Hardware Lock Elision 56:(e.g. RDRAND, AES-NI) 9539:Instruction listings 9288:, 01-oct-94 revision 5795:Bit Test and Clear. 5429:Rotate Left Nibble. 5374:Add Nibble Strings. 5109:The address used by 4286:VPCOMUQ xmm1,xmm2,,6 3947:Packed left-rotate. 3660:2x32bit -> 64bit 3645:2x16bit -> 32bit 3339:Signed 64-bit lanes 3324:Signed 32-bit lanes 3309:Signed 16-bit lanes 3268:2: GT (greater-than) 3047:were ever used: map 2863:derived instructions 2842:PFRSQRTV mm1,mm2/m64 2581:instruction in that 2418:PMULHRWA mm1,mm2/m64 2369:PFRCPIT2 mm1,mm2/m64 2352:PFRSQIT1 mm1,mm2/m64 2335:PFRCPIT1 mm1,mm2/m64 2279: 2237: 1673:instruction (opcode 1406:FP64 prefetch (W=1) 1403:FP32 prefetch (W=0) 1400:FP64 prefetch (W=1) 1397:FP32 prefetch (W=0) 1276:V4FMADDSS x,x+3,m128 1267:V4FMADDPS z,z+3,m128 1193: 1166: 1151:VRSQRT28SD x,x,x/m64 1133:VRSQRT28SS x,x,x/m32 1083: 1008: 907:used as scaled index 881:62 F1 79 48 6F 04 C1 9534:Calling conventions 9434:High Level Assembly 9351:x86 assembly topics 8963:Texas Instruments, 6115:BTCLRL imm8,imm8,cb 5844:Substitution cipher 5631:V20, V30, V40, V50 4726:BEXTR reg,r/m,imm32 3885:without saturation 3624:2x8bit -> 16bit 3288:Signed 8-bit lanes 2746:dst <- src + src 2744:dst <- dst − dst 2731:PFPNACC mm1,mm2/m64 2723:dst <- src − src 2721:dst <- dst − dst 2438:PAVGUSB mm1,mm2/m64 2411:PMULHRW mm1,mm2/m64 2403:dst <- src + src 2401:dst <- dst + dst 2311:PFRSQRT mm1,mm2/m64 2130:PFCMPGT mm1,mm2/m64 2111:PFCMPGE mm1,mm2/m64 2092:PFCMPEQ mm1,mm2/m64 2047:dst <- dst * src 2028:dst <- src − dst 2009:dst <- dst − src 1990:dst <- dst + src 1880:3DNow! instructions 1189:approximation with 1062:VRCP28PD z,z,z/m512 1048:VRCP28PS z,z,z/m512 21:Part of a series on 9529:Processor register 9302:Robert L. Hummel, 9199:, pages 31,34,68. 8978:CPU identification 8486:on 30 January 2003 8480:grafi.ii.pw.edu.pl 7049:PMULHRIW mm,mm/m64 7028:PMULHRWC mm,mm/m64 6653:NatSemi Geode GX2 5783:BTCLR imm8,imm8,cb 5746:Finish Interrupt. 5467:Bitfield extract. 4407:Fused multiply-add 3758:64-bit, high-half 3743:32-bit, full-lane 3692:16-bit, full-lane 2827:PFRCPV mm1,mm2/m64 2709:PFNACC mm1,mm2/m64 2688:PSWAPD mm1,mm2/m64 2294: 2250: 2016:PFSUBR mm1,mm2/m64 1226:EVEX.66.0F38 C8 /r 1209: 1179: 1099: 1069:VRCP28SD x,x,x/m64 1055:VRCP28SS x,x,x/m32 1024: 699:Instruction prefix 262:software emulation 192:Insert Bit String 156:Extract Bit String 50:(VT-x, AMD-V, TDX) 9552: 9551: 9446:Netwide Assembler 9364:Assembly language 9269:Harald Feldmann, 8780:, 1998, page 14. 8284:John H. Wharton, 8048: 8047: 7791: 7790: 7673: 7672: 7534:Write cache data 7312: 7311: 7173: 7172: 7021:PMULHRW mm,mm/m64 7000:PSUBSIW mm,mm/m64 6939:PADDSIW mm,mm/m64 6887: 6886: 6675: 6674: 6655:AMD Geode GX, LX 6338: 6337: 5498:Bitfield Insert. 5220:TEST1 r/m16, imm8 5096: 5095: 5079:XOP.A 12 /1 imm32 5042:XOP.A 12 /0 imm32 4938: 4937: 4913:~x | (x + 1) 4893:~x | (x − 1) 4793:x | ~(x + 1) 4731:XOP.A 10 /r imm32 4688: 4687: 4371:The instructions 4369: 4368: 4224: 4223: 4210:64-bit, unsigned 4195:32-bit, unsigned 4180:16-bit, unsigned 3728:64-bit, low-half 3713:32-bit, low-half 3277:5: NE (not-equal) 3262:0: LT (less-than) 3010: 3009: 2857: 2856: 2751: 2750: 2673:PI2FW mm1,mm2/m64 2658:PF2IW mm1,mm2/m64 2483:On AMD K6-2, the 2470: 2469: 2389:PFACC mm1,mm2/m64 2292: 2291: 2248: 2185:PFRCP mm1,mm2/m64 2164:PI2FD mm1,mm2/m64 2149:PF2ID mm1,mm2/m64 2073:PFMIN mm1,mm2/m64 2054:PFMAX mm1,mm2/m64 2035:PFMUL mm1,mm2/m64 1997:PFSUB mm1,mm2/m64 1978:PFADD mm1,mm2/m64 1852: 1851: 1667: 1666: 1610: 1609: 1332: 1331: 835: 834: 747: 746: 511: 510: 315: 314: 249: 248: 97: 96: 9577: 9565:X86 instructions 9345: 9338: 9331: 9322: 9315: 9300: 9289: 9282: 9273: 9267: 9261: 9256: 9247: 9240: 9234: 9223: 9217: 9210: 9204: 9193: 9187: 9176: 9170: 9166:Michal Necasek, 9164: 9158: 9151: 9145: 9134: 9128: 9122: 9116: 9109: 9103: 9092: 9086: 9080: 9074: 9067: 9061: 9050: 9044: 9043:on Jul 21, 2023. 9034: 9028: 9027:, section 2.15.3 9022: 9013: 9002: 8993: 8987: 8981: 8974: 8968: 8961: 8955: 8954:on Feb 11, 2009. 8944: 8938: 8927: 8921: 8920:on Nov 22, 2022. 8910: 8904: 8903:on Dec 11, 2022. 8898: 8897: 8896:PUSH/POP DS2/DS3 8887: 8881: 8880: 8878: 8877: 8872:. pp. 21–22 8866: 8860: 8854: 8848: 8847:on Jul 27, 2023. 8837: 8826: 8816: 8810: 8804: 8798: 8791: 8785: 8774: 8768: 8757: 8746: 8739: 8733: 8732: 8730: 8729: 8720:. Archived from 8714: 8708: 8707: 8705: 8704: 8698: 8683: 8675: 8669: 8668: 8666: 8665: 8659: 8644: 8636: 8630: 8629: 8627: 8625: 8619: 8612: 8603: 8597: 8586: 8580: 8579:on Sep 24, 2023. 8574: 8570: 8561: 8555: 8549: 8545: 8536: 8530: 8529:on Oct 11, 2018. 8519: 8513: 8512:on Jan 24, 2009. 8502: 8496: 8495: 8493: 8491: 8482:. Archived from 8472: 8463: 8459:Grzegorz Mazur, 8457: 8451: 8450: 8443: 8437: 8426: 8420: 8414: 8410: 8406: 8397: 8391: 8380: 8374: 8363: 8357: 8346: 8340: 8337: 8331: 8324:OPCODE.LST v4.51 8320: 8303: 8282: 8271: 8270: 8258: 8252: 8241: 8235: 8233: 8231: 8223: 8217: 8206: 8197: 8195:on Sep 18, 2023. 8186:on Sep 18, 2023. 8176: 8170: 8159: 8153: 8146: 8140: 8139:on Jul 23, 2023. 8133:Yes. Deprecated. 8129: 8123: 8116: 8107: 8100: 8071: 8069: 8065: 8061: 8056: 8041: 8036: 8026: 8021: 8011: 8006: 7995: 7989: 7984: 7973: 7967: 7962: 7952: 7951: 7945: 7935: 7930: 7920: 7915: 7902: 7897: 7887: 7882: 7881: 7867: 7862: 7861: 7840: 7839: 7831: 7830: 7824: 7805: 7784: 7779: 7769: 7768: 7754: 7753: 7747: 7746: 7735: 7730: 7720: 7715: 7699: 7666: 7661: 7651: 7646: 7636: 7631: 7621: 7616: 7606: 7601: 7591: 7586: 7576: 7571: 7561: 7556: 7546: 7541: 7531: 7526: 7519:Read cache data 7516: 7511: 7504:Write cache tag 7501: 7496: 7486: 7481: 7471: 7466: 7456: 7451: 7441: 7436: 7426: 7421: 7411: 7406: 7396: 7391: 7381: 7376: 7366: 7361: 7351: 7350: 7344: 7343: 7326: 7322: 7318: 7305: 7304: 7298: 7288: 7283: 7267: 7248: 7245: 7241: 7235: 7231: 7226: 7220: 7218: 7214: 7210: 7205: 7188: 7186: 7181: 7169: 7168: 7162: 7157: 7150: 7149: 7143: 7138: 7131: 7130: 7124: 7119: 7105: 7104: 7098: 7093: 7082: 7075: 7070: 7063: 7056: 7051: 7050: 7042: 7035: 7030: 7029: 7024: 7022: 7014: 7007: 7002: 7001: 6993: 6986: 6985: 6979: 6972: 6965: 6960: 6953: 6946: 6941: 6940: 6932: 6925: 6920: 6904: 6900: 6896: 6892: 6883: 6878: 6873: 6868: 6863: 6858: 6853: 6848: 6843:Implied operand 6838: 6833: 6828: 6823: 6818: 6813: 6808: 6803: 6795: 6765: 6755: 6751: 6746: 6737: 6735: 6731: 6722: 6716: 6714: 6710: 6706: 6700: 6698: 6694: 6693: 6688: 6683: 6668: 6663: 6647: 6642: 6632: 6627: 6617: 6612: 6602: 6597: 6581: 6576: 6566: 6561: 6545: 6540: 6533: 6518: 6517: 6509: 6508: 6499: 6494: 6484: 6479: 6469: 6464: 6454: 6449: 6439: 6438: 6432: 6422: 6417: 6416: 6390: 6385: 6384: 6364: 6324: 6310: 6305: 6298: 6293: 6286: 6281: 6274: 6269: 6262: 6257: 6250: 6245: 6238: 6233: 6226: 6221: 6208: 6203: 6186: 6181: 6170: 6165: 6158: 6153: 6143: 6138: 6130: 6124: 6123: 6122:0F 9D ib ib rel8 6117: 6116: 6105: 6100: 6099: 6098:RSTWDT imm8,imm8 6088: 6084: 6079: 6075: 6065: 6060: 6053: 6048: 6038: 6033: 6026: 6021: 6020: 6011: 6007: 6001: 5996: 5995: 5987: 5982: 5975: 5970: 5963: 5958: 5951: 5946: 5939: 5934: 5927: 5922: 5915: 5910: 5889: 5884: 5872: 5866: 5861: 5837: 5832: 5819: 5811: 5806: 5792: 5791: 5790:0F 9C ib ib rel8 5785: 5784: 5773: 5768: 5758: 5753: 5743: 5738: 5728: 5723: 5713: 5708: 5697: 5691: 5686: 5669: 5664: 5647: 5642: 5622: 5617:emulation mode. 5610: 5605: 5592: 5582: 5576: 5572: 5567: 5559: 5555: 5549: 5544: 5536: 5532: 5526: 5521: 5514: 5509: 5495: 5490: 5483: 5478: 5464: 5459: 5451: 5445: 5440: 5426: 5421: 5411: 5406: 5393: 5388: 5371: 5366: 5359: 5355: 5350: 5349:NOT1 r/m16, imm8 5346: 5339:Invert one bit. 5336: 5332: 5327: 5323: 5316: 5312: 5307: 5306:SET1 r/m16, imm8 5303: 5293: 5289: 5284: 5280: 5273: 5269: 5264: 5263:CLR1 r/m16, imm8 5260: 5250: 5246: 5241: 5237: 5230: 5226: 5221: 5217: 5216:TEST1 r/m8, imm8 5198: 5194: 5189: 5185: 5162: 5138: 5136: 5132: 5128: 5124: 5120: 5116: 5112: 5107: 5088: 5081: 5080: 5074: 5073: 5063: 5044: 5043: 5037: 5036: 5022: 5017: 5003: 4998: 4982: 4953: 4951: 4946: 4934: 4933:~x & (x − 1) 4926: 4921: 4914: 4906: 4901: 4894: 4886: 4881: 4874: 4873:x | (x − 1) 4866: 4861: 4854: 4853:x | (x + 1) 4846: 4841: 4834: 4826: 4821: 4814: 4813:~x & (x + 1) 4806: 4801: 4794: 4786: 4781: 4774: 4766: 4761: 4754: 4732: 4727: 4708: 4412: 4378: 4374: 4359: 4354: 4338: 4333: 4300: 4291: 4288: 4287: 4283:is an alias for 4282: 4281: 4271: 4270: 4266:is an alias for 4265: 4264: 4263:B xmm1,xmm2,xmm3 4252: 4247: 4220: 4215: 4205: 4200: 4190: 4185: 4175: 4170: 4165:8-bit, unsigned 4160: 4155: 4145: 4140: 4130: 4125: 4109: 4104: 4080: 4075: 4065: 4060: 4047: 4042: 4032: 4027: 4014: 4009: 3999: 3994: 3981: 3976: 3963: 3958: 3932: 3931:XOP.8 A3 /r /is4 3927: 3909: 3895: 3894:XOP.8 B6 /r /is4 3890: 3874: 3873:XOP.8 A6 /r /is4 3869: 3868: 3862:with saturation 3847: 3846:XOP.8 8F /r /is4 3842: 3841: 3835: 3828: 3827:XOP.8 8E /r /is4 3823: 3813: 3812:XOP.8 87 /r /is4 3808: 3798: 3797:XOP.8 86 /r /is4 3793: 3783: 3782:XOP.8 85 /r /is4 3778: 3768: 3767:XOP.8 9F /r /is4 3763: 3753: 3752:XOP.8 9E /r /is4 3748: 3738: 3737:XOP.8 97 /r /is4 3733: 3723: 3722:XOP.8 96 /r /is4 3718: 3702: 3701:XOP.8 95 /r /is4 3697: 3684: 3670: 3665: 3655: 3650: 3634: 3629: 3609: 3604: 3599: 3592: 3587: 3577: 3572: 3562: 3557: 3547: 3542: 3532: 3527: 3517: 3512: 3502: 3497: 3487: 3482: 3472: 3467: 3457: 3452: 3436: 3431: 3411: 3406: 3396: 3391: 3381: 3376: 3375: 3364: 3359: 3349: 3344: 3334: 3329: 3319: 3314: 3298: 3293: 3241: 3240: 3239:XOP.8 A2 /r /is4 3234: 3233: 3226: 3225: 3220: 3201: 3196: 3180: 3175: 3159: 3154: 3138: 3133: 3093: 3058: 3054: 3050: 3046: 3040: 3036: 3032: 2982: 2899: 2850: 2849: 2843: 2833: 2828: 2812: 2797: 2795: 2791: 2786: 2780: 2777: 2771: 2767: 2762: 2747: 2738: 2733: 2732: 2724: 2715: 2710: 2703: 2694: 2689: 2679: 2674: 2664: 2659: 2643: 2623: 2619: 2615: 2614: 2609: 2608: 2603: 2602: 2597: 2596: 2586: 2584: 2580: 2576: 2571: 2565: 2562: 2558: 2552: 2548: 2543: 2537: 2533: 2529: 2525: 2521: 2517: 2513: 2506: 2502: 2494: 2490: 2486: 2478: 2463: 2458: 2451: 2444: 2439: 2432: 2425: 2420: 2419: 2414: 2412: 2404: 2395: 2390: 2376: 2371: 2370: 2359: 2354: 2353: 2342: 2337: 2336: 2328: 2317: 2312: 2303: 2301: 2300: 2295: 2293: 2287: 2283: 2274: 2259: 2257: 2256: 2251: 2249: 2241: 2232: 2222: 2216: 2212: 2208: 2202: 2191: 2186: 2172: 2171: 2165: 2155: 2150: 2143: 2136: 2131: 2124: 2117: 2112: 2105: 2098: 2093: 2086: 2079: 2074: 2067: 2060: 2055: 2048: 2041: 2036: 2029: 2022: 2017: 2010: 2003: 1998: 1991: 1984: 1979: 1963: 1871: 1867: 1863: 1847: 1839: 1834: 1826: 1816: 1811: 1804: 1803: 1797: 1796: 1795:UMOV r16/32, r/m 1788: 1783: 1776: 1771: 1770:UMOV r/m, r16/32 1761: 1756: 1742: 1737: 1721: 1696:SMM instructions 1676: 1672: 1660: 1659: 1653: 1652: 1641: 1640: 1634: 1633: 1616: 1606: 1605: 1604: 1597: 1596: 1595: 1588: 1587: 1586: 1579: 1578: 1577: 1570: 1569: 1568: 1556: 1555: 1554: 1547: 1546: 1545: 1538: 1537: 1536: 1529: 1528: 1527: 1520: 1519: 1518: 1506: 1505: 1504: 1497: 1496: 1495: 1488: 1487: 1486: 1479: 1478: 1477: 1470: 1469: 1468: 1456: 1455: 1454: 1447: 1446: 1445: 1438: 1437: 1436: 1429: 1428: 1427: 1420: 1419: 1418: 1391: 1384: 1372: 1348: 1345: 1320: 1319: 1318: 1311: 1310: 1309: 1302: 1301: 1279: 1278: 1277: 1270: 1269: 1268: 1261: 1260: 1240: 1239:VEXP2PD z,z/m512 1232: 1231:VEXP2PS z,z/m512 1227: 1218: 1216: 1215: 1210: 1208: 1207: 1188: 1186: 1185: 1180: 1178: 1177: 1154: 1153: 1152: 1145: 1144: 1143: 1136: 1135: 1134: 1127: 1126: 1125: 1118: 1117: 1108: 1106: 1105: 1100: 1098: 1097: 1071: 1070: 1064: 1063: 1057: 1056: 1050: 1049: 1043: 1042: 1033: 1031: 1030: 1025: 1023: 1022: 948: 902: 901: 900:VMOVDQA32 zmm0, 893: 892: 883: 882: 863: 859: 855: 828: 827: 821: 817: 813: 812: 801: 800: 794: 790: 786: 785: 768: 742: 736: 731: 723: 717: 712: 696: 692: 688: 670: 668: 664: 660: 656: 652: 648: 647: 642: 638: 634: 630: 626: 622: 621: 616: 612: 608: 607: 602: 598: 594: 589: 583: 581: 577: 572: 563: 561: 557: 552: 543: 541: 536: 530: 528: 524: 519: 504: 499: 489: 484: 474: 469: 462: 461: 455: 445: 440: 439: 428: 423: 413: 408: 399: 395: 391: 384: 379: 366: 365: 359: 343: 318:MPX instructions 311: 310: 304: 303: 292: 287: 283: 267: 242: 237: 206: 201: 200: 189: 184: 168: 164: 153: 152: 146: 145: 125: 89: 82: 75: 18: 9585: 9584: 9580: 9579: 9578: 9576: 9575: 9574: 9555: 9554: 9553: 9548: 9524:Program counter 9469: 9463: 9452:Turbo Assembler 9403: 9379:Instruction set 9352: 9349: 9319: 9318: 9301: 9292: 9283: 9276: 9268: 9264: 9257: 9250: 9241: 9237: 9233:on Jan 7, 2022. 9224: 9220: 9211: 9207: 9203:on Jul 20,2006. 9194: 9190: 9186:on 27 Oct 2020. 9177: 9173: 9165: 9161: 9152: 9148: 9144:on Nov 4, 2018. 9135: 9131: 9123: 9119: 9110: 9106: 9102:on 20 Apr 2020. 9093: 9089: 9085:, section 4.1.5 9081: 9077: 9068: 9064: 9060:on Nov 3, 2011. 9051: 9047: 9035: 9031: 9023: 9016: 9003: 8996: 8992:, section 2.6.4 8988: 8984: 8975: 8971: 8962: 8958: 8945: 8941: 8937:on Dec 5, 2006. 8928: 8924: 8911: 8907: 8895: 8894: 8888: 8884: 8875: 8873: 8868: 8867: 8863: 8855: 8851: 8838: 8829: 8825:on Jan 6, 2022. 8817: 8813: 8805: 8801: 8792: 8788: 8784:on Dec 2, 2021. 8775: 8771: 8767:on Dec 2, 2021. 8758: 8749: 8740: 8736: 8727: 8725: 8716: 8715: 8711: 8702: 8700: 8696: 8681: 8677: 8676: 8672: 8663: 8661: 8657: 8642: 8638: 8637: 8633: 8623: 8621: 8617: 8610: 8605: 8604: 8600: 8587: 8583: 8572: 8568: 8562: 8558: 8547: 8543: 8537: 8533: 8520: 8516: 8503: 8499: 8489: 8487: 8474: 8473: 8466: 8458: 8454: 8445: 8444: 8440: 8436:on 15 Mar 2019. 8427: 8423: 8419:on 24 Sep 2023. 8412: 8408: 8404: 8398: 8394: 8381: 8377: 8364: 8360: 8347: 8343: 8338: 8334: 8330:on 21 May 2001. 8326:, 15 Oct 1999. 8321: 8306: 8301: 8283: 8274: 8265:. Oct 7, 1994. 8261: 8259: 8255: 8242: 8238: 8229: 8225: 8224: 8220: 8216:on 29 Jun 2022. 8207: 8200: 8190:"RECIP28EXP2.c" 8177: 8173: 8160: 8156: 8148:Alexander Yee, 8147: 8143: 8130: 8126: 8117: 8110: 8101: 8097: 8092: 8080: 8075: 8074: 8067: 8063: 8059: 8057: 8053: 8039: 8034: 8024: 8019: 8009: 8004: 7993: 7987: 7982: 7971: 7965: 7960: 7949: 7948: 7943: 7933: 7928: 7918: 7913: 7908:IIT 2c87, 3c87 7900: 7895: 7885: 7879: 7878: 7865: 7859: 7858: 7837: 7836: 7828: 7827: 7822: 7800: 7782: 7777: 7766: 7765: 7751: 7750: 7744: 7743: 7733: 7728: 7718: 7713: 7690: 7664: 7659: 7649: 7644: 7634: 7629: 7619: 7614: 7604: 7599: 7589: 7584: 7574: 7569: 7559: 7554: 7544: 7539: 7529: 7524: 7514: 7509: 7499: 7494: 7489:Read cache tag 7484: 7479: 7469: 7464: 7454: 7449: 7439: 7434: 7424: 7419: 7409: 7404: 7394: 7389: 7379: 7374: 7364: 7359: 7348: 7347: 7341: 7340: 7320: 7316: 7302: 7301: 7296: 7286: 7281: 7261: 7252: 7251: 7243: 7239: 7233: 7229: 7228:The Cyrix EMMI 7227: 7223: 7216: 7212: 7208: 7206: 7191: 7184: 7182: 7178: 7166: 7165: 7160: 7155: 7147: 7146: 7141: 7136: 7128: 7127: 7122: 7117: 7102: 7101: 7096: 7091: 7080: 7079: 7073: 7069:PMACHRIW mm,m64 7068: 7061: 7060: 7054: 7048: 7047: 7040: 7039: 7033: 7027: 7026: 7025: 7020: 7019: 7012: 7011: 7005: 6999: 6998: 6991: 6990: 6983: 6982: 6977: 6970: 6969: 6963: 6959:PMAGW mm,mm/m64 6958: 6951: 6950: 6944: 6938: 6937: 6930: 6929: 6923: 6919:PAVEB mm,mm/m64 6918: 6898: 6894: 6890: 6881: 6876: 6871: 6866: 6861: 6856: 6851: 6846: 6836: 6831: 6826: 6821: 6816: 6811: 6806: 6801: 6778: 6769: 6768: 6753: 6749: 6747: 6740: 6733: 6729: 6723: 6719: 6712: 6708: 6707: 6703: 6696: 6691: 6690: 6686: 6684: 6680: 6666: 6661: 6645: 6640: 6630: 6625: 6615: 6610: 6600: 6595: 6579: 6574: 6564: 6559: 6543: 6538: 6531: 6515: 6514: 6506: 6505: 6497: 6492: 6482: 6477: 6467: 6462: 6452: 6447: 6436: 6435: 6430: 6420: 6414: 6413: 6388: 6382: 6381: 6351: 6322: 6308: 6303: 6296: 6291: 6284: 6279: 6272: 6267: 6260: 6255: 6248: 6243: 6236: 6231: 6224: 6219: 6206: 6201: 6184: 6179: 6168: 6163: 6156: 6151: 6141: 6136: 6128: 6121: 6120: 6114: 6113: 6103: 6097: 6096: 6086: 6085: 6082: 6077: 6076: 6073: 6063: 6058: 6051: 6046: 6036: 6031: 6024: 6019:MOV DS2,r16,m32 6018: 6017: 6009: 6005: 5999: 5994:MOV DS3,r16,m32 5993: 5992: 5985: 5980: 5973: 5968: 5961: 5956: 5949: 5944: 5937: 5932: 5925: 5920: 5913: 5908: 5887: 5882: 5870: 5864: 5859: 5835: 5830: 5817: 5809: 5804: 5789: 5788: 5782: 5781: 5771: 5766: 5756: 5751: 5741: 5736: 5726: 5721: 5711: 5706: 5695: 5689: 5684: 5667: 5662: 5645: 5640: 5620: 5608: 5603: 5590: 5580: 5574: 5573: 5570: 5565: 5557: 5553: 5547: 5542: 5534: 5530: 5524: 5519: 5512: 5507: 5493: 5488: 5481: 5476: 5462: 5457: 5449: 5443: 5438: 5424: 5419: 5409: 5404: 5391: 5386: 5369: 5364: 5357: 5356: 5353: 5348: 5347: 5345:NOT1 r/m8, imm8 5344: 5334: 5333: 5330: 5325: 5324: 5321: 5314: 5313: 5310: 5305: 5304: 5302:SET1 r/m8, imm8 5301: 5291: 5290: 5287: 5282: 5281: 5278: 5271: 5270: 5267: 5262: 5261: 5259:CLR1 r/m8, imm8 5258: 5253:Clear one bit. 5248: 5247: 5244: 5239: 5238: 5235: 5228: 5227: 5224: 5219: 5218: 5215: 5196: 5195: 5192: 5188:TEST1 r/m16, CL 5187: 5186: 5183: 5156: 5147: 5142: 5141: 5134: 5130: 5126: 5122: 5118: 5114: 5110: 5108: 5101: 5086: 5078: 5077: 5071: 5070: 5061: 5041: 5040: 5034: 5033: 5020: 5015: 5001: 4996: 4968:and removed in 4962: 4957: 4956: 4949: 4947: 4943: 4932: 4924: 4919: 4912: 4904: 4899: 4892: 4884: 4879: 4872: 4864: 4860:BLSFILL reg,r/m 4859: 4852: 4844: 4839: 4832: 4824: 4819: 4812: 4804: 4799: 4792: 4784: 4779: 4773:x & (x + 1) 4772: 4764: 4760:BLCFILL reg,r/m 4759: 4752: 4730: 4725: 4695: 4393: 4376: 4372: 4357: 4352: 4336: 4331: 4322: 4320: 4315: 4313: 4295: 4294: 4285: 4284: 4275: 4274: 4268: 4267: 4258: 4257: 4250: 4248: 4229: 4218: 4213: 4203: 4198: 4188: 4183: 4173: 4168: 4158: 4153: 4150:64-bit, signed 4143: 4138: 4135:32-bit, signed 4128: 4123: 4120:16-bit, signed 4107: 4102: 4078: 4073: 4063: 4058: 4045: 4040: 4030: 4025: 4012: 4007: 3997: 3992: 3979: 3974: 3961: 3956: 3930: 3925: 3907: 3893: 3888: 3872: 3866: 3865: 3845: 3839: 3838: 3833: 3826: 3821: 3811: 3806: 3796: 3791: 3781: 3776: 3766: 3761: 3751: 3746: 3736: 3731: 3721: 3716: 3700: 3695: 3682: 3668: 3663: 3653: 3648: 3632: 3627: 3607: 3602: 3597: 3590: 3585: 3575: 3570: 3560: 3555: 3545: 3540: 3530: 3525: 3515: 3510: 3500: 3495: 3485: 3480: 3470: 3465: 3455: 3450: 3434: 3429: 3409: 3404: 3394: 3389: 3379: 3373: 3372: 3362: 3357: 3347: 3342: 3332: 3327: 3317: 3312: 3296: 3291: 3238: 3237: 3231: 3230: 3223: 3222: 3218: 3199: 3194: 3178: 3173: 3157: 3152: 3136: 3131: 3115: 3113: 3108: 3106: 3056: 3052: 3048: 3042: 3038: 3034: 3030: 2980: 2884: 2865: 2847: 2846: 2841: 2831: 2826: 2810: 2801: 2800: 2793: 2789: 2787: 2783: 2775: 2769: 2765: 2763: 2756: 2745: 2743: 2742: 2736: 2730: 2729: 2722: 2720: 2719: 2713: 2708: 2701: 2699: 2698: 2692: 2687: 2677: 2672: 2662: 2657: 2641: 2621: 2617: 2612: 2611: 2606: 2605: 2600: 2599: 2594: 2593: 2590: 2589: 2582: 2578: 2574: 2572: 2568: 2560: 2556: 2550: 2546: 2544: 2540: 2531: 2527: 2523: 2519: 2515: 2511: 2504: 2500: 2492: 2488: 2484: 2479: 2475: 2461: 2456: 2449: 2448: 2442: 2437: 2430: 2429: 2423: 2417: 2416: 2415: 2410: 2409: 2402: 2400: 2399: 2393: 2388: 2374: 2368: 2367: 2357: 2351: 2350: 2340: 2334: 2333: 2326: 2324: 2322: 2321: 2315: 2310: 2277: 2276: 2272: 2269: 2235: 2234: 2230: 2227: 2220: 2214: 2210: 2206: 2200: 2198: 2196: 2195: 2189: 2184: 2169: 2168: 2163: 2153: 2148: 2141: 2140: 2134: 2129: 2122: 2121: 2115: 2110: 2103: 2102: 2096: 2091: 2084: 2083: 2077: 2072: 2065: 2064: 2058: 2053: 2046: 2045: 2039: 2034: 2027: 2026: 2020: 2015: 2008: 2007: 2001: 1996: 1989: 1988: 1982: 1977: 1888: 1882: 1869: 1865: 1859: 1845: 1843: 1837: 1832: 1822: 1820: 1814: 1809: 1801: 1800: 1794: 1793: 1786: 1781: 1774: 1769: 1759: 1754: 1740: 1735: 1698: 1690: 1674: 1670: 1657: 1656: 1650: 1649: 1638: 1637: 1631: 1630: 1602: 1601: 1600: 1593: 1592: 1591: 1584: 1583: 1582: 1575: 1574: 1573: 1566: 1565: 1564: 1552: 1551: 1550: 1543: 1542: 1541: 1534: 1533: 1532: 1525: 1524: 1523: 1516: 1515: 1514: 1502: 1501: 1500: 1493: 1492: 1491: 1484: 1483: 1482: 1475: 1474: 1473: 1466: 1465: 1464: 1452: 1451: 1450: 1443: 1442: 1441: 1434: 1433: 1432: 1425: 1424: 1423: 1416: 1415: 1414: 1389: 1382: 1352: 1351: 1346: 1337: 1316: 1315: 1314: 1307: 1306: 1305: 1299: 1298: 1275: 1274: 1273: 1266: 1265: 1264: 1258: 1257: 1238: 1230: 1225: 1196: 1191: 1190: 1169: 1164: 1163: 1150: 1149: 1148: 1141: 1140: 1139: 1132: 1131: 1130: 1123: 1122: 1121: 1115: 1114: 1086: 1081: 1080: 1068: 1067: 1061: 1060: 1054: 1053: 1047: 1046: 1040: 1039: 1011: 1006: 1005: 955: 914: 899: 898: 890: 889: 880: 879: 861: 857: 853: 845: 840: 825: 824: 819: 818: 815: 814: 810: 809: 798: 797: 792: 791: 788: 787: 783: 782: 752: 740: 734: 729: 721: 715: 710: 690: 686: 679: 674: 673: 666: 662: 658: 654: 650: 645: 644: 640: 636: 632: 628: 624: 619: 618: 614: 610: 605: 604: 600: 596: 592: 590: 586: 579: 575: 573: 566: 559: 555: 553: 546: 539: 537: 533: 526: 522: 520: 516: 502: 497: 487: 482: 472: 467: 459: 458: 453: 443: 437: 436: 426: 421: 411: 406: 397: 393: 389: 382: 377: 363: 362: 357: 326: 320: 308: 307: 301: 300: 290: 285: 284: 281: 257: 240: 235: 225:Present in all 204: 198: 197: 187: 182: 166: 162: 150: 149: 143: 142: 120: 112: 93: 12: 11: 5: 9583: 9581: 9573: 9572: 9567: 9557: 9556: 9550: 9549: 9547: 9546: 9541: 9536: 9531: 9526: 9521: 9516: 9514:Memory address 9511: 9510: 9509: 9504: 9499: 9497:Interrupt flag 9494: 9492:Direction flag 9489: 9479: 9473: 9471: 9465: 9464: 9462: 9461: 9455: 9449: 9443: 9437: 9431: 9425: 9422:Flat Assembler 9419: 9413: 9411: 9405: 9404: 9402: 9401: 9396: 9394:Microassembler 9391: 9386: 9381: 9376: 9371: 9366: 9360: 9358: 9354: 9353: 9350: 9348: 9347: 9340: 9333: 9325: 9317: 9316: 9290: 9284:Norbert Juffa 9274: 9262: 9248: 9242:Desmond Yuen, 9235: 9218: 9205: 9188: 9182:, 5 Dec 2015. 9171: 9159: 9146: 9129: 9117: 9104: 9087: 9075: 9062: 9045: 9029: 9014: 9012:on 3 Dec 2023. 8994: 8982: 8976:Debbie Wiles, 8969: 8956: 8939: 8922: 8905: 8893:. Opcodes for 8882: 8861: 8849: 8827: 8811: 8799: 8786: 8769: 8747: 8734: 8724:on 23 Feb 2017 8709: 8670: 8631: 8620:on 26 Jul 2014 8598: 8596:on 2 Feb 2009. 8581: 8556: 8554:on 7 Aug 2011. 8531: 8514: 8497: 8464: 8452: 8438: 8421: 8392: 8390:on 9 Oct 2018. 8375: 8373:on 7 Sep 2024. 8358: 8341: 8332: 8304: 8272: 8260:Intel vs AMD, 8253: 8251:on 5 Sep 2024. 8236: 8218: 8198: 8171: 8169:on 4 Aug 2021. 8154: 8141: 8124: 8108: 8094: 8093: 8091: 8088: 8087: 8086: 8079: 8076: 8073: 8072: 8050: 8049: 8046: 8045: 8042: 8037: 8031: 8030: 8027: 8022: 8016: 8015: 8012: 8007: 8001: 8000: 7997: 7992:Equivalent to 7990: 7985: 7979: 7978: 7974: 7969: 7957: 7956: 7953: 7946: 7940: 7939: 7936: 7931: 7925: 7924: 7921: 7916: 7910: 7909: 7906: 7903: 7898: 7892: 7891: 7888: 7883: 7875: 7874: 7871: 7868: 7863: 7855: 7854: 7851: 7842: 7825: 7819: 7818: 7815: 7812: 7809: 7799: 7792: 7789: 7788: 7785: 7780: 7774: 7773: 7770: 7763: 7759: 7758: 7755: 7748: 7745:LDUSR UGRS,EAX 7740: 7739: 7736: 7731: 7725: 7724: 7721: 7716: 7710: 7709: 7706: 7703: 7689: 7674: 7671: 7670: 7667: 7662: 7656: 7655: 7652: 7647: 7641: 7640: 7637: 7632: 7626: 7625: 7622: 7617: 7611: 7610: 7607: 7602: 7596: 7595: 7592: 7587: 7581: 7580: 7577: 7572: 7566: 7565: 7562: 7557: 7551: 7550: 7547: 7542: 7536: 7535: 7532: 7527: 7521: 7520: 7517: 7512: 7506: 7505: 7502: 7497: 7491: 7490: 7487: 7482: 7476: 7475: 7472: 7467: 7461: 7460: 7457: 7452: 7446: 7445: 7442: 7437: 7431: 7430: 7427: 7422: 7416: 7415: 7412: 7407: 7401: 7400: 7397: 7392: 7386: 7385: 7382: 7377: 7371: 7370: 7367: 7362: 7356: 7355: 7352: 7345: 7337: 7336: 7333: 7330: 7321:"SuperState V" 7317:"SuperState V" 7310: 7309: 7306: 7299: 7297:STFEAT AL,imm8 7293: 7292: 7289: 7284: 7278: 7277: 7274: 7271: 7260: 7253: 7250: 7249: 7221: 7189: 7175: 7174: 7171: 7170: 7163: 7158: 7156:PMVGEZB mm,m64 7152: 7151: 7144: 7139: 7133: 7132: 7125: 7120: 7114: 7113: 7106: 7099: 7094: 7088: 7087: 7084: 7083: 7076: 7071: 7065: 7064: 7057: 7052: 7044: 7043: 7036: 7031: 7016: 7015: 7008: 7003: 6995: 6994: 6987: 6980: 6978:PDISTIB mm,m64 6974: 6973: 6966: 6961: 6955: 6954: 6947: 6942: 6934: 6933: 6926: 6921: 6915: 6914: 6911: 6908: 6885: 6884: 6879: 6874: 6869: 6864: 6859: 6854: 6849: 6844: 6840: 6839: 6834: 6829: 6824: 6819: 6814: 6809: 6804: 6799: 6777: 6770: 6767: 6766: 6738: 6717: 6701: 6677: 6676: 6673: 6672: 6669: 6664: 6658: 6657: 6651: 6648: 6643: 6637: 6636: 6633: 6628: 6622: 6621: 6618: 6613: 6607: 6606: 6603: 6598: 6592: 6591: 6585: 6582: 6577: 6571: 6570: 6567: 6562: 6556: 6555: 6553:VIA Cyrix III 6549: 6546: 6541: 6535: 6534: 6528: 6527: 6521: 6500: 6495: 6489: 6488: 6485: 6480: 6474: 6473: 6470: 6465: 6459: 6458: 6455: 6450: 6444: 6443: 6440: 6433: 6427: 6426: 6423: 6418: 6410: 6409: 6397: 6391: 6386: 6378: 6377: 6374: 6371: 6368: 6350: 6339: 6336: 6335: 6332: 6325: 6320: 6319:(no mnemonic) 6316: 6315: 6312: 6311: 6306: 6300: 6299: 6294: 6288: 6287: 6282: 6276: 6275: 6270: 6264: 6263: 6258: 6252: 6251: 6246: 6240: 6239: 6234: 6228: 6227: 6222: 6216: 6215: 6212: 6209: 6204: 6198: 6197: 6194: 6193: 6190: 6187: 6182: 6176: 6175: 6172: 6171: 6166: 6160: 6159: 6154: 6148: 6147: 6144: 6139: 6133: 6132: 6125: 6118: 6110: 6109: 6106: 6101: 6093: 6092: 6089: 6080: 6070: 6069: 6066: 6061: 6055: 6054: 6049: 6043: 6042: 6039: 6034: 6028: 6027: 6022: 6014: 6013: 6002: 5997: 5989: 5988: 5983: 5977: 5976: 5971: 5965: 5964: 5959: 5953: 5952: 5947: 5941: 5940: 5935: 5929: 5928: 5923: 5917: 5916: 5911: 5905: 5904: 5901: 5890: 5885: 5879: 5878: 5875: 5874: 5867: 5862: 5856: 5855: 5852: 5838: 5833: 5827: 5826: 5823: 5822: 5812: 5807: 5801: 5800: 5793: 5786: 5778: 5777: 5774: 5769: 5763: 5762: 5759: 5754: 5748: 5747: 5744: 5739: 5733: 5732: 5729: 5724: 5718: 5717: 5714: 5709: 5703: 5702: 5701:V25, V35, V55 5699: 5692: 5687: 5681: 5680: 5677: 5676: 5670: 5665: 5659: 5658: 5655: 5648: 5643: 5637: 5636: 5633: 5632: 5629: 5611: 5606: 5600: 5599: 5596: 5595: 5583:ones used for 5577: 5568: 5562: 5561: 5550: 5545: 5539: 5538: 5527: 5522: 5516: 5515: 5510: 5504: 5503: 5496: 5491: 5485: 5484: 5479: 5473: 5472: 5465: 5460: 5454: 5453: 5446: 5441: 5435: 5434: 5427: 5422: 5416: 5415: 5412: 5407: 5401: 5400: 5394: 5389: 5383: 5382: 5372: 5367: 5361: 5360: 5351: 5341: 5340: 5337: 5328: 5326:NOT1 r/m16, CL 5318: 5317: 5308: 5298: 5297: 5294: 5285: 5283:SET1 r/m16, CL 5275: 5274: 5265: 5255: 5254: 5251: 5242: 5240:CLR1 r/m16, CL 5232: 5231: 5222: 5212: 5211: 5208: 5201:Test one bit. 5199: 5190: 5184:TEST1 r/m8, CL 5180: 5179: 5176: 5175: 5172: 5169: 5166: 5155: 5148: 5146: 5143: 5140: 5139: 5098: 5097: 5094: 5093: 5082: 5075: 5067: 5066: 5058: 5057: 5054: 5051: 5045: 5038: 5030: 5029: 5023: 5018: 5012: 5011: 5004: 4999: 4993: 4992: 4989: 4986: 4961: 4958: 4955: 4954: 4940: 4939: 4936: 4935: 4930: 4927: 4922: 4916: 4915: 4910: 4907: 4902: 4900:T1MSKC reg,r/m 4896: 4895: 4890: 4887: 4882: 4876: 4875: 4870: 4867: 4862: 4856: 4855: 4850: 4847: 4842: 4836: 4835: 4830: 4827: 4822: 4820:BLCMSK reg,r/m 4816: 4815: 4810: 4807: 4802: 4796: 4795: 4790: 4787: 4782: 4776: 4775: 4770: 4767: 4762: 4756: 4755: 4750: 4749: 4748: 4745: 4742: 4733: 4728: 4722: 4721: 4718: 4715: 4712: 4694: 4689: 4686: 4685: 4683: 4680: 4677: 4673: 4672: 4670: 4667: 4664: 4660: 4659: 4657: 4654: 4651: 4647: 4646: 4644: 4641: 4638: 4634: 4633: 4631: 4628: 4625: 4621: 4620: 4618: 4615: 4612: 4608: 4607: 4605: 4602: 4599: 4595: 4594: 4592: 4589: 4586: 4582: 4581: 4579: 4576: 4573: 4569: 4568: 4566: 4563: 4560: 4556: 4555: 4553: 4550: 4547: 4543: 4542: 4540: 4537: 4534: 4530: 4529: 4527: 4524: 4521: 4517: 4516: 4514: 4511: 4508: 4504: 4503: 4501: 4498: 4495: 4491: 4490: 4488: 4485: 4482: 4478: 4477: 4475: 4472: 4469: 4465: 4464: 4462: 4459: 4456: 4452: 4451: 4449: 4446: 4443: 4439: 4438: 4436: 4433: 4430: 4426: 4425: 4422: 4419: 4416: 4392: 4386: 4367: 4366: 4363: 4360: 4355: 4350: 4346: 4345: 4342: 4339: 4334: 4329: 4325: 4324: 4317: 4310: 4307: 4304: 4293: 4292: 4290: 4289: 4272: 4226: 4225: 4222: 4221: 4216: 4211: 4207: 4206: 4201: 4196: 4192: 4191: 4186: 4181: 4177: 4176: 4171: 4166: 4162: 4161: 4156: 4151: 4147: 4146: 4141: 4136: 4132: 4131: 4126: 4121: 4117: 4116: 4113: 4110: 4105: 4100: 4099:8-bit, signed 4097: 4089: 4088: 4085: 4084: 4081: 4079:XOP.8 C3 /r ib 4076: 4070: 4069: 4066: 4061: 4056: 4052: 4051: 4048: 4046:XOP.8 C2 /r ib 4043: 4037: 4036: 4033: 4028: 4023: 4019: 4018: 4015: 4013:XOP.8 C1 /r ib 4010: 4004: 4003: 4000: 3995: 3990: 3986: 3985: 3982: 3980:XOP.8 C0 /r ib 3977: 3971: 3970: 3967: 3964: 3959: 3954: 3951: 3944: 3943: 3940: 3939: 3936: 3933: 3928: 3923: 3922: 3921: 3918: 3915: 3901: 3900: 3897: 3896: 3891: 3886: 3882: 3881: 3878: 3875: 3870: 3863: 3860: 3853: 3852: 3849: 3848: 3843: 3836: 3830: 3829: 3824: 3819: 3815: 3814: 3809: 3804: 3800: 3799: 3794: 3789: 3785: 3784: 3779: 3774: 3770: 3769: 3764: 3759: 3755: 3754: 3749: 3744: 3740: 3739: 3734: 3729: 3725: 3724: 3719: 3714: 3710: 3709: 3706: 3703: 3698: 3693: 3690: 3676: 3675: 3672: 3671: 3666: 3661: 3657: 3656: 3651: 3646: 3642: 3641: 3638: 3635: 3630: 3625: 3622: 3615: 3614: 3611: 3610: 3605: 3600: 3594: 3593: 3588: 3583: 3579: 3578: 3573: 3568: 3564: 3563: 3558: 3553: 3549: 3548: 3543: 3538: 3534: 3533: 3528: 3523: 3519: 3518: 3513: 3508: 3504: 3503: 3498: 3493: 3489: 3488: 3483: 3478: 3474: 3473: 3468: 3463: 3459: 3458: 3453: 3448: 3444: 3443: 3440: 3437: 3432: 3427: 3424: 3417: 3416: 3413: 3412: 3410:XOP.8 EF /r ib 3407: 3402: 3398: 3397: 3395:XOP.8 EE /r ib 3392: 3387: 3383: 3382: 3380:XOP.8 ED /r ib 3377: 3370: 3366: 3365: 3363:XOP.8 EC /r ib 3360: 3355: 3351: 3350: 3348:XOP.8 CF /r ib 3345: 3340: 3336: 3335: 3333:XOP.8 CE /r ib 3330: 3325: 3321: 3320: 3318:XOP.8 CD /r ib 3315: 3310: 3306: 3305: 3302: 3299: 3297:XOP.8 CC /r ib 3294: 3289: 3286: 3285: 3284: 3281: 3278: 3275: 3272: 3269: 3266: 3263: 3253: 3252: 3249: 3248: 3245: 3242: 3235: 3228: 3213: 3212: 3209: 3208: 3205: 3202: 3197: 3192: 3188: 3187: 3184: 3181: 3176: 3171: 3167: 3166: 3163: 3160: 3155: 3150: 3146: 3145: 3142: 3139: 3134: 3129: 3126: 3122: 3121: 3118: 3117: 3110: 3103: 3100: 3097: 3088: 3087: 3081: 3078: 3072: 3071: 3070: 3067: 3060: 3020: 3017: 3008: 3007: 3004: 3001: 2998: 2995: 2992: 2989: 2986: 2983: 2978: 2974: 2973: 2970: 2967: 2964: 2961: 2958: 2955: 2952: 2949: 2946: 2943: 2940: 2937: 2934: 2931: 2928: 2925: 2922: 2918: 2917: 2914: 2912: 2909: 2907: 2904: 2902: 2883: 2877: 2864: 2858: 2855: 2854: 2851: 2844: 2838: 2837: 2834: 2829: 2823: 2822: 2819: 2816: 2809: 2802: 2799: 2798: 2781: 2753: 2752: 2749: 2748: 2739: 2734: 2726: 2725: 2716: 2711: 2705: 2704: 2695: 2690: 2684: 2683: 2680: 2675: 2669: 2668: 2665: 2660: 2654: 2653: 2650: 2647: 2640: 2630: 2588: 2587: 2566: 2538: 2536: 2535: 2508: 2497:Newton-Raphson 2472: 2471: 2468: 2467: 2464: 2459: 2453: 2452: 2445: 2440: 2434: 2433: 2426: 2421: 2406: 2405: 2396: 2391: 2385: 2384: 2381: 2380: 2377: 2372: 2364: 2363: 2360: 2355: 2347: 2346: 2343: 2338: 2330: 2329: 2327:dst <- temp 2325:dst <- temp 2318: 2313: 2307: 2306: 2290: 2286: 2267: 2247: 2244: 2225: 2203: 2201:dst <- temp 2199:dst <- temp 2192: 2187: 2181: 2180: 2177: 2176: 2173: 2166: 2160: 2159: 2156: 2151: 2145: 2144: 2137: 2132: 2126: 2125: 2118: 2113: 2107: 2106: 2099: 2094: 2088: 2087: 2080: 2075: 2069: 2068: 2061: 2056: 2050: 2049: 2042: 2037: 2031: 2030: 2023: 2018: 2012: 2011: 2004: 1999: 1993: 1992: 1985: 1980: 1974: 1973: 1970: 1967: 1961: 1960: 1953: 1938: 1931: 1884:Main article: 1881: 1878: 1850: 1849: 1840: 1835: 1829: 1828: 1817: 1812: 1806: 1805: 1798: 1790: 1789: 1784: 1778: 1777: 1772: 1766: 1765: 1762: 1757: 1751: 1750: 1743: 1738: 1732: 1731: 1728: 1725: 1697: 1691: 1689: 1683: 1671:PREFETCHWT1 m8 1665: 1664: 1661: 1654: 1646: 1645: 1642: 1635: 1627: 1626: 1623: 1620: 1608: 1607: 1598: 1589: 1580: 1571: 1562: 1558: 1557: 1548: 1539: 1530: 1521: 1512: 1508: 1507: 1498: 1489: 1480: 1471: 1462: 1458: 1457: 1448: 1439: 1430: 1421: 1412: 1408: 1407: 1404: 1401: 1398: 1394: 1393: 1386: 1379: 1376: 1370: 1369: 1366: 1363: 1360: 1350: 1349: 1334: 1333: 1330: 1329: 1327: 1324: 1321: 1312: 1303: 1296: 1293: 1289: 1288: 1286: 1283: 1280: 1271: 1262: 1255: 1252: 1248: 1247: 1244: 1241: 1236: 1233: 1228: 1223: 1220: 1219:relative error 1206: 1203: 1199: 1176: 1172: 1159: 1158: 1155: 1146: 1137: 1128: 1119: 1112: 1109: 1096: 1093: 1089: 1076: 1075: 1072: 1065: 1058: 1051: 1044: 1037: 1034: 1021: 1018: 1014: 1001: 1000: 998: 996: 994: 990: 989: 986: 983: 980: 976: 975: 972: 970: 967: 965: 962: 960: 957: 952: 946: 945: 942: 939: 936: 933: 913: 910: 909: 908: 895: 844: 841: 839: 836: 833: 832: 829: 822: 806: 805: 802: 795: 779: 778: 775: 772: 751: 748: 745: 744: 737: 732: 726: 725: 718: 713: 707: 706: 703: 700: 678: 675: 672: 671: 584: 564: 544: 531: 513: 512: 509: 508: 505: 500: 494: 493: 490: 485: 479: 478: 475: 470: 464: 463: 456: 450: 449: 446: 441: 433: 432: 429: 424: 418: 417: 414: 409: 403: 402: 385: 380: 374: 373: 367: 360: 354: 353: 350: 347: 322:Main article: 319: 316: 313: 312: 309:0F B8 rel16/32 305: 302:JMPE disp16/32 297: 296: 293: 288: 278: 277: 274: 271: 256: 250: 247: 246: 243: 238: 232: 231: 213: 207: 202: 194: 193: 190: 185: 179: 178: 157: 154: 147: 139: 138: 137:Eventual fate 135: 132: 129: 119: 113: 111: 105: 95: 94: 92: 91: 84: 77: 69: 66: 65: 64: 63: 57: 51: 48:Virtualization 45: 39: 30: 29: 23: 22: 13: 10: 9: 6: 4: 3: 2: 9582: 9571: 9568: 9566: 9563: 9562: 9560: 9545: 9542: 9540: 9537: 9535: 9532: 9530: 9527: 9525: 9522: 9520: 9517: 9515: 9512: 9508: 9505: 9503: 9502:Overflow flag 9500: 9498: 9495: 9493: 9490: 9488: 9485: 9484: 9483: 9480: 9478: 9475: 9474: 9472: 9466: 9459: 9456: 9453: 9450: 9447: 9444: 9441: 9438: 9435: 9432: 9429: 9428:GNU Assembler 9426: 9423: 9420: 9418: 9415: 9414: 9412: 9410: 9406: 9400: 9397: 9395: 9392: 9390: 9387: 9385: 9382: 9380: 9377: 9375: 9372: 9370: 9367: 9365: 9362: 9361: 9359: 9355: 9346: 9341: 9339: 9334: 9332: 9327: 9326: 9323: 9313: 9312:1-56276-016-5 9309: 9305: 9299: 9297: 9295: 9291: 9287: 9281: 9279: 9275: 9272: 9266: 9263: 9260: 9255: 9253: 9249: 9245: 9239: 9236: 9232: 9228: 9227:"intel387 sl" 9222: 9219: 9215: 9209: 9206: 9202: 9198: 9192: 9189: 9185: 9181: 9175: 9172: 9169: 9163: 9160: 9156: 9150: 9147: 9143: 9139: 9133: 9130: 9126: 9121: 9118: 9114: 9108: 9105: 9101: 9097: 9091: 9088: 9084: 9079: 9076: 9072: 9066: 9063: 9059: 9055: 9049: 9046: 9042: 9038: 9033: 9030: 9026: 9021: 9019: 9015: 9011: 9007: 9001: 8999: 8995: 8991: 8986: 8983: 8979: 8973: 8970: 8966: 8960: 8957: 8953: 8949: 8943: 8940: 8936: 8932: 8926: 8923: 8919: 8915: 8909: 8906: 8902: 8892: 8886: 8883: 8871: 8865: 8862: 8858: 8853: 8850: 8846: 8842: 8836: 8834: 8832: 8828: 8824: 8820: 8815: 8812: 8808: 8803: 8800: 8796: 8790: 8787: 8783: 8779: 8773: 8770: 8766: 8762: 8756: 8754: 8752: 8748: 8745:, 20 May 2019 8744: 8738: 8735: 8723: 8719: 8713: 8710: 8699:on 4 Jan 2014 8695: 8691: 8687: 8680: 8674: 8671: 8660:on 7 Nov 2013 8656: 8652: 8648: 8641: 8635: 8632: 8616: 8609: 8602: 8599: 8595: 8591: 8585: 8582: 8578: 8566: 8560: 8557: 8553: 8541: 8535: 8532: 8528: 8524: 8518: 8515: 8511: 8507: 8501: 8498: 8485: 8481: 8477: 8471: 8469: 8465: 8462: 8456: 8453: 8448: 8442: 8439: 8435: 8431: 8425: 8422: 8418: 8402: 8396: 8393: 8389: 8385: 8379: 8376: 8372: 8368: 8362: 8359: 8355: 8354:0-201-47950-8 8351: 8345: 8342: 8336: 8333: 8329: 8325: 8319: 8317: 8315: 8313: 8311: 8309: 8305: 8299: 8298:1-885330-02-2 8295: 8291: 8287: 8281: 8279: 8277: 8273: 8268: 8264: 8257: 8254: 8250: 8246: 8240: 8237: 8228: 8222: 8219: 8215: 8211: 8205: 8203: 8199: 8196: 8194: 8191: 8185: 8181: 8175: 8172: 8168: 8164: 8158: 8155: 8151: 8145: 8142: 8138: 8134: 8128: 8125: 8121: 8120:SDM, volume 1 8115: 8113: 8109: 8105: 8099: 8096: 8089: 8085: 8082: 8081: 8077: 8055: 8052: 8043: 8038: 8033: 8032: 8028: 8023: 8018: 8017: 8013: 8008: 8003: 8002: 7991: 7986: 7981: 7980: 7975: 7970: 7968: 7959: 7958: 7954: 7947: 7942: 7941: 7937: 7932: 7927: 7926: 7922: 7917: 7912: 7911: 7904: 7899: 7894: 7893: 7889: 7884: 7877: 7876: 7869: 7864: 7857: 7856: 7852: 7850: 7847: 7843: 7841: 7834: 7826: 7821: 7820: 7817:Available on 7816: 7813: 7810: 7807: 7806: 7803: 7797: 7793: 7786: 7781: 7778:MOV PWRCR,EAX 7776: 7775: 7771: 7764: 7761: 7760: 7756: 7749: 7742: 7741: 7737: 7732: 7727: 7726: 7722: 7717: 7712: 7711: 7707: 7704: 7701: 7700: 7697: 7695: 7687: 7683: 7679: 7675: 7668: 7663: 7658: 7657: 7653: 7648: 7643: 7642: 7638: 7633: 7628: 7627: 7623: 7618: 7613: 7612: 7608: 7603: 7598: 7597: 7593: 7588: 7583: 7582: 7578: 7573: 7568: 7567: 7563: 7558: 7553: 7552: 7548: 7543: 7538: 7537: 7533: 7528: 7523: 7522: 7518: 7513: 7508: 7507: 7503: 7498: 7493: 7492: 7488: 7483: 7478: 7477: 7473: 7468: 7463: 7462: 7458: 7453: 7448: 7447: 7443: 7438: 7433: 7432: 7428: 7423: 7418: 7417: 7413: 7408: 7403: 7402: 7398: 7393: 7388: 7387: 7383: 7378: 7373: 7372: 7368: 7363: 7358: 7357: 7353: 7346: 7339: 7338: 7334: 7331: 7328: 7327: 7324: 7307: 7300: 7295: 7294: 7290: 7285: 7280: 7279: 7275: 7272: 7269: 7268: 7265: 7258: 7254: 7247: 7225: 7222: 7204: 7202: 7200: 7198: 7196: 7194: 7190: 7180: 7177: 7164: 7159: 7154: 7153: 7145: 7140: 7137:PMVLZB mm,m64 7135: 7134: 7126: 7121: 7118:PMVNZB mm,m64 7116: 7115: 7112: 7100: 7095: 7090: 7089: 7085: 7072: 7067: 7066: 7053: 7046: 7045: 7032: 7018: 7017: 7004: 6997: 6996: 6981: 6976: 6975: 6962: 6957: 6956: 6943: 6936: 6935: 6922: 6917: 6916: 6909: 6906: 6905: 6902: 6880: 6875: 6870: 6865: 6860: 6855: 6850: 6845: 6842: 6841: 6835: 6830: 6825: 6820: 6815: 6810: 6805: 6800: 6797: 6796: 6793: 6789: 6787: 6783: 6775: 6771: 6763: 6759: 6745: 6743: 6739: 6727: 6721: 6718: 6705: 6702: 6682: 6679: 6670: 6665: 6660: 6659: 6656: 6649: 6644: 6639: 6638: 6634: 6629: 6624: 6623: 6619: 6614: 6609: 6608: 6604: 6599: 6594: 6593: 6590: 6583: 6578: 6573: 6572: 6568: 6563: 6558: 6557: 6554: 6547: 6542: 6537: 6536: 6530: 6529: 6526: 6520: 6511: 6496: 6490: 6486: 6481: 6476: 6475: 6471: 6466: 6461: 6460: 6456: 6451: 6446: 6445: 6441: 6434: 6429: 6428: 6424: 6419: 6415:RSDC sreg,m80 6412: 6411: 6408: 6405: 6402: 6396: 6392: 6387: 6383:SVDC m80,sreg 6380: 6379: 6376:Available on 6375: 6372: 6369: 6366: 6365: 6362: 6360: 6356: 6348: 6344: 6340: 6333: 6330: 6326: 6321: 6318: 6317: 6313: 6307: 6302: 6301: 6295: 6290: 6289: 6283: 6278: 6277: 6271: 6266: 6265: 6259: 6254: 6253: 6247: 6242: 6241: 6235: 6230: 6229: 6223: 6218: 6217: 6205: 6200: 6199: 6195: 6191: 6188: 6183: 6178: 6177: 6173: 6167: 6162: 6161: 6155: 6150: 6149: 6140: 6135: 6134: 6126: 6119: 6112: 6111: 6107: 6102: 6095: 6094: 6090: 6081: 6072: 6071: 6067: 6062: 6057: 6056: 6050: 6045: 6044: 6035: 6030: 6029: 6023: 6016: 6015: 6012:instructions 5998: 5991: 5990: 5984: 5979: 5978: 5972: 5967: 5966: 5960: 5955: 5954: 5948: 5943: 5942: 5936: 5931: 5930: 5924: 5919: 5918: 5912: 5907: 5906: 5900: 5897: 5886: 5881: 5880: 5876: 5868: 5863: 5858: 5857: 5851: 5849: 5845: 5839: 5834: 5829: 5828: 5824: 5821: 5813: 5808: 5803: 5802: 5799: 5794: 5787: 5780: 5779: 5775: 5770: 5765: 5764: 5760: 5755: 5750: 5749: 5745: 5740: 5735: 5734: 5730: 5725: 5720: 5719: 5715: 5710: 5705: 5704: 5698:instruction. 5693: 5688: 5683: 5682: 5678: 5675: 5671: 5666: 5661: 5660: 5654: 5649: 5644: 5639: 5638: 5634: 5630: 5628: 5626: 5616: 5612: 5607: 5602: 5601: 5597: 5594: 5586: 5578: 5569: 5564: 5563: 5551: 5546: 5541: 5540: 5528: 5523: 5518: 5517: 5511: 5506: 5505: 5502: 5492: 5487: 5486: 5480: 5475: 5474: 5471: 5461: 5456: 5455: 5447: 5442: 5437: 5436: 5433: 5428: 5423: 5418: 5417: 5413: 5408: 5403: 5402: 5399: 5395: 5390: 5385: 5384: 5381: 5378: 5373: 5368: 5363: 5362: 5352: 5343: 5342: 5329: 5322:NOT1 r/m8, CL 5320: 5319: 5309: 5300: 5299: 5296:Set one bit. 5286: 5279:SET1 r/m8, CL 5277: 5276: 5266: 5257: 5256: 5243: 5236:CLR1 r/m8, CL 5234: 5233: 5223: 5214: 5213: 5207: 5204: 5191: 5182: 5181: 5177: 5174:Available on 5173: 5170: 5167: 5164: 5163: 5160: 5153: 5149: 5144: 5106: 5104: 5100: 5092: 5083: 5076: 5069: 5068: 5065: 5055: 5052: 5049: 5048: 5046: 5039: 5032: 5031: 5028: 5024: 5019: 5016:SLWPCB r32/64 5014: 5013: 5010: 5005: 5000: 4997:LLWPCB r32/64 4995: 4994: 4990: 4987: 4984: 4983: 4980: 4977: 4976:mitigations. 4975: 4971: 4967: 4959: 4945: 4942: 4931: 4928: 4923: 4920:TZMSK reg,r/m 4918: 4917: 4911: 4908: 4903: 4898: 4897: 4891: 4888: 4883: 4880:BLSIC reg,r/m 4878: 4877: 4871: 4868: 4863: 4858: 4857: 4851: 4848: 4843: 4838: 4837: 4831: 4828: 4823: 4818: 4817: 4811: 4808: 4803: 4800:BLCIC reg,r/m 4798: 4797: 4791: 4788: 4783: 4778: 4777: 4771: 4768: 4763: 4758: 4757: 4751: 4746: 4743: 4740: 4739: 4738: 4734: 4729: 4724: 4723: 4719: 4716: 4713: 4710: 4709: 4706: 4702: 4700: 4693: 4690: 4684: 4681: 4678: 4675: 4674: 4671: 4668: 4665: 4662: 4661: 4658: 4655: 4652: 4649: 4648: 4645: 4642: 4639: 4636: 4635: 4632: 4629: 4626: 4623: 4622: 4619: 4616: 4613: 4610: 4609: 4606: 4603: 4600: 4597: 4596: 4593: 4590: 4587: 4584: 4583: 4580: 4577: 4574: 4571: 4570: 4567: 4564: 4561: 4558: 4557: 4554: 4551: 4548: 4545: 4544: 4541: 4538: 4535: 4532: 4531: 4528: 4525: 4522: 4519: 4518: 4515: 4512: 4509: 4506: 4505: 4502: 4499: 4496: 4493: 4492: 4489: 4486: 4483: 4480: 4479: 4476: 4473: 4470: 4467: 4466: 4463: 4460: 4457: 4454: 4453: 4450: 4447: 4444: 4441: 4440: 4437: 4434: 4431: 4428: 4427: 4423: 4420: 4417: 4414: 4413: 4410: 4408: 4404: 4402: 4398: 4390: 4387: 4385: 4383: 4364: 4361: 4356: 4351: 4348: 4347: 4343: 4340: 4335: 4330: 4327: 4326: 4318: 4311: 4308: 4305: 4302: 4301: 4298: 4280:UQ xmm1,xmm2, 4279: 4273: 4262: 4256: 4255: 4246: 4244: 4242: 4240: 4238: 4236: 4234: 4232: 4228: 4217: 4212: 4209: 4208: 4202: 4197: 4194: 4193: 4187: 4182: 4179: 4178: 4172: 4167: 4164: 4163: 4157: 4152: 4149: 4148: 4142: 4137: 4134: 4133: 4127: 4122: 4119: 4118: 4106: 4101: 4098: 4096: 4090: 4086: 4082: 4077: 4072: 4071: 4067: 4062: 4057: 4055:64-bit lanes 4053: 4049: 4044: 4039: 4038: 4034: 4029: 4024: 4022:32-bit lanes 4020: 4016: 4011: 4006: 4005: 4001: 3996: 3991: 3989:16-bit lanes 3987: 3983: 3978: 3973: 3972: 3965: 3960: 3955: 3950: 3945: 3941: 3937: 3934: 3929: 3924: 3919: 3916: 3913: 3912: 3911: 3902: 3898: 3892: 3887: 3884: 3883: 3871: 3864: 3861: 3859: 3854: 3850: 3844: 3837: 3832: 3831: 3825: 3820: 3817: 3816: 3810: 3805: 3802: 3801: 3795: 3790: 3787: 3786: 3780: 3775: 3772: 3771: 3765: 3760: 3757: 3756: 3750: 3745: 3742: 3741: 3735: 3730: 3727: 3726: 3720: 3715: 3712: 3711: 3699: 3694: 3691: 3689: 3685: 3677: 3673: 3667: 3662: 3659: 3658: 3652: 3647: 3644: 3643: 3631: 3626: 3623: 3621: 3616: 3612: 3606: 3601: 3596: 3595: 3589: 3584: 3581: 3580: 3574: 3569: 3566: 3565: 3559: 3554: 3551: 3550: 3544: 3539: 3536: 3535: 3529: 3524: 3521: 3520: 3514: 3509: 3506: 3505: 3499: 3494: 3491: 3490: 3484: 3479: 3476: 3475: 3469: 3464: 3461: 3460: 3454: 3449: 3446: 3445: 3433: 3428: 3425: 3423: 3418: 3414: 3408: 3403: 3400: 3399: 3393: 3388: 3385: 3384: 3378: 3371: 3368: 3367: 3361: 3356: 3353: 3352: 3346: 3341: 3338: 3337: 3331: 3326: 3323: 3322: 3316: 3311: 3308: 3307: 3295: 3290: 3287: 3282: 3279: 3276: 3274:4: EQ (equal) 3273: 3270: 3267: 3264: 3261: 3260: 3259: 3254: 3250: 3246: 3243: 3236: 3229: 3227: 3214: 3210: 3206: 3203: 3198: 3193: 3190: 3189: 3185: 3182: 3177: 3172: 3169: 3168: 3164: 3161: 3156: 3151: 3148: 3147: 3143: 3140: 3135: 3130: 3127: 3123: 3119: 3111: 3104: 3101: 3098: 3094: 3091: 3085: 3082: 3079: 3076: 3073: 3068: 3064: 3063: 3061: 3045: 3028: 3024: 3021: 3018: 3015: 3014: 3013: 3002: 2996: 2990: 2987: 2984: 2979: 2976: 2975: 2971: 2968: 2965: 2962: 2959: 2956: 2953: 2950: 2947: 2944: 2941: 2938: 2935: 2932: 2929: 2926: 2923: 2920: 2919: 2905: 2901: 2900: 2897: 2894: 2891: 2889: 2881: 2878: 2876: 2874: 2869: 2862: 2859: 2852: 2845: 2840: 2839: 2835: 2830: 2825: 2824: 2820: 2817: 2814: 2813: 2807: 2803: 2785: 2782: 2779: 2761: 2759: 2755: 2740: 2735: 2728: 2727: 2717: 2712: 2707: 2706: 2702:dst <- src 2700:dst <- src 2696: 2691: 2686: 2685: 2681: 2676: 2671: 2670: 2666: 2661: 2656: 2655: 2651: 2648: 2645: 2644: 2639: 2635: 2631: 2629: 2627: 2570: 2567: 2564: 2542: 2539: 2509: 2498: 2482: 2481: 2477: 2474: 2460: 2455: 2454: 2441: 2436: 2435: 2422: 2408: 2407: 2392: 2387: 2386: 2382: 2378: 2373: 2366: 2365: 2361: 2356: 2349: 2348: 2344: 2339: 2332: 2331: 2319: 2314: 2309: 2308: 2305: 2288: 2284: 2265: 2263: 2245: 2242: 2224: 2193: 2188: 2183: 2182: 2178: 2167: 2162: 2161: 2152: 2147: 2146: 2133: 2128: 2127: 2114: 2109: 2108: 2095: 2090: 2089: 2076: 2071: 2070: 2057: 2052: 2051: 2038: 2033: 2032: 2019: 2014: 2013: 2000: 1995: 1994: 1981: 1976: 1975: 1968: 1965: 1964: 1958: 1954: 1951: 1947: 1943: 1939: 1936: 1932: 1929: 1925: 1921: 1917: 1913: 1909: 1905: 1901: 1900: 1899: 1897: 1893: 1887: 1879: 1877: 1875: 1862: 1857: 1841: 1836: 1831: 1830: 1827:instruction. 1825: 1818: 1813: 1808: 1807: 1799: 1792: 1791: 1785: 1782:UMOV r8, r/m8 1780: 1779: 1773: 1768: 1767: 1758: 1755:UMOV r/m8, r8 1753: 1752: 1748: 1744: 1739: 1734: 1733: 1729: 1726: 1723: 1722: 1719: 1717: 1714: 1709: 1707: 1703: 1695: 1692: 1687: 1684: 1682: 1680: 1662: 1655: 1648: 1647: 1643: 1636: 1629: 1628: 1624: 1621: 1618: 1617: 1614: 1599: 1590: 1581: 1572: 1563: 1560: 1559: 1549: 1540: 1531: 1522: 1513: 1510: 1509: 1499: 1490: 1481: 1472: 1463: 1460: 1459: 1449: 1440: 1431: 1422: 1413: 1410: 1409: 1405: 1402: 1399: 1396: 1395: 1378:Basic opcode 1373: 1367: 1364: 1361: 1358: 1357: 1356: 1344: 1342: 1340: 1336: 1328: 1325: 1322: 1313: 1304: 1297: 1294: 1291: 1290: 1287: 1284: 1281: 1272: 1263: 1256: 1253: 1250: 1249: 1245: 1242: 1237: 1234: 1229: 1224: 1221: 1204: 1201: 1197: 1174: 1170: 1161: 1160: 1156: 1147: 1138: 1129: 1120: 1113: 1110: 1094: 1091: 1087: 1078: 1077: 1073: 1066: 1059: 1052: 1045: 1038: 1035: 1019: 1016: 1012: 1003: 1002: 999: 991: 987: 984: 981: 978: 977: 959:Basic opcode 949: 943: 940: 937: 934: 931: 930: 929: 926: 923: 919: 911: 906: 896: 887: 886: 885: 877: 872: 870: 865: 850: 842: 837: 830: 823: 808: 807: 803: 796: 781: 780: 776: 773: 770: 769: 766: 764: 759: 757: 749: 738: 733: 728: 727: 719: 714: 709: 708: 704: 701: 698: 697: 694: 684: 676: 588: 585: 571: 569: 565: 551: 549: 545: 535: 532: 518: 515: 506: 501: 496: 495: 491: 486: 481: 480: 476: 471: 466: 465: 457: 454:BNDMOV b/m, b 452: 451: 442: 438:BMDMOV b, b/m 435: 434: 430: 425: 420: 419: 415: 410: 405: 404: 401: 386: 381: 376: 375: 372: 368: 361: 356: 355: 351: 348: 345: 344: 341: 337: 335: 331: 325: 317: 306: 299: 298: 289: 280: 279: 275: 272: 269: 268: 265: 263: 254: 251: 244: 239: 234: 233: 230: 228: 222: 218: 212: 211:test register 208: 203: 196: 195: 191: 186: 181: 180: 177: 175: 170: 155: 148: 141: 140: 136: 133: 130: 127: 126: 123: 117: 114: 109: 106: 104: 102: 90: 85: 83: 78: 76: 71: 70: 68: 67: 61: 58: 55: 54:Cryptographic 52: 49: 46: 43: 40: 37: 34: 33: 32: 31: 28: 24: 20: 19: 16: 9389:Machine code 9374:Disassembler 9265: 9238: 9221: 9208: 9191: 9174: 9162: 9149: 9132: 9120: 9107: 9090: 9078: 9065: 9048: 9032: 8985: 8972: 8959: 8942: 8925: 8908: 8885: 8874:. Retrieved 8864: 8859:, p. 765-766 8852: 8814: 8809:, p. 360-361 8802: 8789: 8772: 8763:, sep 2000. 8737: 8726:. Retrieved 8722:the original 8712: 8701:. Retrieved 8694:the original 8685: 8673: 8662:. Retrieved 8655:the original 8646: 8634: 8622:. Retrieved 8615:the original 8601: 8584: 8559: 8534: 8517: 8500: 8488:. Retrieved 8484:the original 8479: 8455: 8441: 8424: 8395: 8378: 8361: 8344: 8335: 8289: 8256: 8239: 8221: 8187: 8174: 8157: 8152:, 7 Aug 2024 8144: 8131:R. Singhal, 8127: 8098: 8054: 7964: 7873:Intel 387SL 7853:Intel 287XL 7848: 7845: 7835: 7832: 7814:Description 7808:Instruction 7801: 7708:Description 7691: 7335:Description 7313: 7276:Description 7262: 7237: 7224: 7179: 7109: 7092:PMVZB mm,m64 6913:Description 6888: 6790: 6779: 6776:instructions 6720: 6704: 6681: 6654: 6588: 6552: 6524: 6512: 6503: 6406: 6403: 6400: 6394: 6373:Description 6367:Instruction 6352: 5893: 5841: 5815: 5796: 5673: 5651: 5618: 5588: 5499: 5468: 5430: 5397: 5379: 5375: 5205: 5202: 5171:Description 5165:Instruction 5157: 5152:NEC V-series 5090: 5059: 5026: 5007: 4991:Description 4985:Instruction 4978: 4963: 4944: 4840:BLCS reg,r/m 4780:BLCI reg,r/m 4736: 4717:Description 4711:Instruction 4703: 4696: 4405: 4394: 4391:instructions 4370: 4296: 4277: 4260: 4093: 3953:8-bit lanes 3948: 3905: 3857: 3686: 3680: 3619: 3421: 3257: 3217: 3191:Scalar FP64 3170:Scalar FP32 3149:Packed FP64 3128:Packed FP32 3089: 3083: 3074: 3022: 3011: 2895: 2892: 2885: 2882:instructions 2870: 2866: 2796:instruction. 2784: 2773: 2607:PREFETCHW m8 2591: 2569: 2554: 2541: 2476: 2270: 2228: 2218: 1889: 1853: 1730:Description 1710: 1699: 1688:instructions 1668: 1625:Description 1619:Instruction 1611: 1353: 1162:Exponential 927: 915: 873: 866: 846: 777:Description 771:Instruction 765:processors. 760: 753: 705:Description 680: 587: 534: 517: 483:BNDSTX mib,b 468:BNDLDX b,mib 422:BNDCN b, r/m 407:BNDCU b, r/m 388: 378:BNDCL b, r/m 370: 352:Description 338: 327: 276:Description 270:Instruction 258: 255:instructions 224: 171: 160: 121: 118:instructions 110:instructions 98: 60:Discontinued 59: 15: 9468:Programming 8914:"nec v55sc" 8624:11 December 8490:22 February 7783:D6 FA 03 02 7767:D6 C8 03 A0 7752:D6 CA 03 A0 7702:Instruction 7329:Instruction 7270:Instruction 6907:Instruction 6560:WRSHR r/m32 6539:RDSHR r/m32 6137:QHOUT imm16 6104:0F 96 ib ib 5933:MOV DS2,r/m 5921:MOV DS3,r/m 5909:MOV r/m,DS2 5883:MOV r/m,DS3 5513:0F 39 /0 ib 5508:INS r8,imm8 5482:0F 3B /0 ib 5477:EXT r8,imm8 5358:0F 1F /0 ib 5354:0F 1E /0 ib 5315:0F 1D /0 ib 5311:0F 1C /0 ib 5272:0F 1B /0 ib 5268:0F 1A /0 ib 5229:0F 19 /0 ib 5225:0F 18 /0 ib 5021:XOP.9 12 /1 5002:XOP.9 12 /0 4925:XOP.9 01 /4 4905:XOP.9 01 /7 4885:XOP.9 01 /6 4865:XOP.9 01 /2 4845:XOP.9 01 /3 4833:x ^ (x + 1) 4825:XOP.9 02 /1 4805:XOP.9 01 /5 4785:XOP.9 02 /6 4765:XOP.9 01 /1 4415:Instruction 4219:XOP.9 97 /r 4204:XOP.9 96 /r 4189:XOP.9 95 /r 4174:XOP.9 94 /r 4159:XOP.9 9B /r 4144:XOP.9 9A /r 4129:XOP.9 99 /r 4108:XOP.9 98 /r 4064:XOP.9 93 /r 4031:XOP.9 92 /r 3998:XOP.9 91 /r 3962:XOP.9 90 /r 3669:XOP.9 E3 /r 3654:XOP.9 E2 /r 3633:XOP.9 E1 /r 3608:XOP.9 DB /r 3591:XOP.9 D7 /r 3576:XOP.9 D6 /r 3561:XOP.9 D3 /r 3546:XOP.9 D2 /r 3531:XOP.9 D1 /r 3516:XOP.9 CB /r 3501:XOP.9 C7 /r 3486:XOP.9 C6 /r 3471:XOP.9 C3 /r 3456:XOP.9 C2 /r 3435:XOP.9 C1 /r 3200:XOP.9 83 /r 3179:XOP.9 82 /r 3158:XOP.9 81 /r 3137:XOP.9 80 /r 2848:0F 0F /r 87 2832:0F 0F /r 86 2815:Instruction 2737:0F 0F /r 8E 2714:0F 0F /r 8A 2693:0F 0F /r BB 2678:0F 0F /r 0C 2663:0F 0F /r 1C 2646:Instruction 2595:PREFETCH m8 2545:The 3DNow! 2443:0F 0F /r BF 2424:0F 0F /r B7 2394:0F 0F /r AE 2375:0F 0F /r B6 2358:0F 0F /r A7 2341:0F 0F /r A6 2316:0F 0F /r 97 2190:0F 0F /r 96 2170:0F 0F /r 0D 2154:0F 0F /r 1D 2135:0F 0F /r A0 2116:0F 0F /r 90 2097:0F 0F /r B0 2078:0F 0F /r 94 2059:0F 0F /r A4 2040:0F 0F /r B4 2021:0F 0F /r AA 2002:0F 0F /r 9A 1983:0F 0F /r 9E 1966:Instruction 1876:processor. 1844:Similar to 1724:Instruction 1681:YongFeng). 488:NP 0F 1B /r 473:NP 0F 1A /r 460:66 0F 1B /r 444:66 0F 1A /r 427:F2 0F 1B /r 412:F2 0F 1A /r 383:F3 0F 1A /r 364:F3 0F 1B /r 346:Instruction 334:Coffee Lake 236:MOV TRx,r32 221:Quark X1000 199:MOV r32,TRx 183:IBTS r/m, r 174:VIA PadLock 144:XBTS r, r/m 134:Description 128:Instruction 9559:Categories 9487:Carry flag 9477:Call stack 9409:Assemblers 9195:DM&P, 9127:, page 245 9052:Sandpile, 8876:2024-01-18 8728:2014-03-17 8703:2014-01-02 8664:2014-01-02 8573:VPERMIL2PS 8569:VPERMIL2PD 8548:VPERMIL2PS 8544:VPERMIL2PD 8356:, page 120 8090:References 7688:M6117 MCUs 6164:QTIN imm16 6152:QOUT imm16 6078:BSCH r/m16 5814:CPU Halt. 5767:MOVSPB r16 5663:RETXA imm8 5641:BRKXA imm8 5625:Intel 8080 5604:BRKEM imm8 5154:processors 4699:Piledriver 4377:VPERMIL2PS 4373:VPERMIL2PD 2873:VEX prefix 1902:AMD K6-2, 1856:IBM 386SLC 1375:Operation 951:Operation 756:Tiger Lake 358:BNDMK b, m 286:JMPE r/m32 282:JMPE r/m16 209:Move from 9544:Registers 9507:Zero flag 9178:Corexor, 8946:ZFMicro, 8889:Renesas, 8839:Renesas, 8060:FNSTSG AX 7880:FNSTSG AX 7860:FNSTDW AX 7342:SCALL r/m 6736:encoding. 6611:CPU_WRITE 6596:BB1_RESET 6575:BB0_RESET 6448:RSLDT m80 6431:SVLDT m80 6359:Cyrix III 6334:V60, V70 6074:BSCH r/m8 5896:real mode 5860:BRKN imm8 5831:BRKS imm8 5752:TSKSW r16 5707:BRKCS r16 5657:V33, V53 5613:Break to 5489:INS r8,r8 5458:EXT r8,r8 5439:ROR4 r/m8 5420:ROL4 r/m8 4966:Bulldozer 4397:Bulldozer 4249:For each 2626:Broadwell 2618:PREFETCHW 1957:Geode GX2 1942:Cyrix III 1920:Bulldozer 1716:microcode 1202:− 1092:− 1017:− 683:Intel TSX 646:0F 80..8F 627:(opcodes 613:(opcodes 599:(opcodes 330:"Skylake" 324:Intel MPX 9417:A86/A386 9306:, 1992, 9231:Archived 9201:Archived 9184:Archived 9142:Archived 9100:Archived 9058:Archived 9041:Archived 9010:Archived 8952:Archived 8935:Archived 8918:Archived 8901:Archived 8845:Archived 8823:Archived 8782:Archived 8765:Archived 8594:original 8577:Archived 8552:original 8527:Archived 8510:original 8434:Archived 8417:Archived 8413:PFRCPIT2 8409:PFRSQIT1 8405:PFRCPIT1 8388:Archived 8371:Archived 8328:Archived 8288:, 1994. 8267:Archived 8249:Archived 8214:Archived 8193:archived 8184:Archived 8167:Archived 8137:Archived 8078:See also 7686:DM&P 7349:0F 18 /0 7303:FE F0 ib 7282:LFEAT AX 7244:PMULHRWC 7240:PMULHRWA 7215:and the 7213:PMACHRIW 7161:0F 5C /r 7142:0F 5B /r 7123:0F 5A /r 7097:0F 58 /r 7074:0F 5E /r 7055:0F 5D /r 7034:0F 59 /r 7006:0F 55 /r 6984:0F 54 /r 6964:0F 52 /r 6945:0F 51 /r 6924:0F 50 /r 6786:MediaGXm 6748:For the 6732:for the 6730:SMINTOLD 6626:CPU_READ 6565:0F 37 /0 6544:0F 36 /0 6483:0F 7D /0 6478:RSTS m80 6468:0F 7C /0 6463:SVTS m80 6453:0F 7B /0 6437:0F 7A /0 6421:0F 79 /r 6389:0F 78 /r 6169:0F E2 iw 6157:0F E1 iw 6142:0F E0 iw 6087:0F 3D /0 6083:0F 3C /0 6025:0F 3E /r 6000:0F 36 /r 5969:PUSH DS2 5945:PUSH DS3 5848:Mask ROM 5772:0F 95 /7 5757:0F 94 /7 5712:0F 2D /0 5668:0F F0 ib 5646:0F E0 ib 5609:0F FF ib 5494:0F 31 /r 5463:0F 33 /r 5444:0F 2A /0 5425:0F 28 /0 5335:0F 17 /0 5331:0F 16 /0 5292:0F 15 /0 5288:0F 14 /0 5249:0F 13 /0 5245:0F 12 /0 5197:0F 11 /0 5193:0F 10 /0 4323:allowed 4316:allowed 4254:example: 3116:allowed 3109:allowed 3000:v̅v̅v̅v̅ 2890:onward. 2806:Geode GX 2613:0F 0D /1 2610:(opcode 2601:0F 0D /0 2598:(opcode 2561:PMULHRWC 2557:PMULHRWA 2528:PFRCPIT2 2524:PFRSQIT1 2520:PFRCPIT1 2493:PFRCPIT2 2489:PFRSQIT1 2485:PFRCPIT1 2215:PFRCPIT2 2211:PFRSQIT1 2207:PFRCPIT1 1802:0F 13 /r 1787:0F 12 /r 1775:0F 11 /r 1760:0F 10 /r 1675:0F 0D /2 918:Xeon Phi 849:Xeon Phi 730:XRELEASE 711:XACQUIRE 691:XRELEASE 687:XACQUIRE 336:" CPUs. 291:0F 00 /6 241:0F 26 /r 205:0F 24 /r 188:0F A7 /r 151:0F A6 /r 9111:Cyrix, 8686:amd.com 8647:amd.com 8563:Intel, 8538:Intel, 8188:C code 8178:Intel, 8161:Intel, 8035:FRINEAR 8020:FRICHOP 7966:FMUL4X4 7811:Opcode 7390:SVECTOR 7375:SRESUME 7234:PMULHRW 7230:PMULHRW 7209:PDISTIB 6370:Opcode 6329:NEC V60 5981:POP DS2 5957:POP DS3 5168:Opcode 4988:Opcode 4974:Spectre 4970:AMD Zen 4714:Opcode 4421:Meaning 4382:AMD Zen 4309:Opcode 3102:Opcode 3012:where: 2916:Byte 2 2911:Byte 1 2906:Byte 0 2551:PMULHRW 2547:PMULHRW 2516:PFRSQRT 2505:PFRSQRT 1937:2 and 3 1935:WinChip 1874:UMC U5S 1861:LOADALL 1824:LOADALL 1679:Zhaoxin 1622:Opcode 988:Scalar 985:Packed 982:Scalar 979:Packed 974:RC/SAE 956:subset 954:AVX-512 922:AVX-512 869:AVX-512 862:KORTEST 774:Opcode 273:Opcode 253:Itanium 217:Pentium 167:CMPXCHG 163:CMPXCHG 9519:Opcode 9470:issues 9460:(WASM) 9454:(TASM) 9448:(NASM) 9442:(MASM) 9424:(FASM) 9357:Topics 9310: 9212:Intel 8352: 8296: 8118:Intel 8102:Intel 8064:FNINIT 8005:FRINT2 7823:FRSTPM 7798:clones 7705:Opcode 7682:Nvidia 7555:RTLBLA 7540:RTLBPA 7332:Opcode 7273:Opcode 6910:Opcode 6782:6x86MX 6772:Cyrix 6758:ModR/M 6304:CNVTRP 6268:GETBIT 6256:SCHEOL 6220:COLTRP 6214:V55PI 6192:V55SC 5722:RETRBI 5685:MOVSPA 5131:LLWPCB 5127:SLWPCB 5123:SLWPCB 5119:LLWPCB 5115:SLWPCB 5111:LLWPCB 5087:LWPINS 5062:LWPINS 4705:mode. 4424:Notes 4418:Opcode 4321:(256b) 4251:VPCOM* 3114:(256b) 3027:ModR/M 2994:mmmmm 2977:Usage 2818:Opcode 2808:and LX 2794:PSWAPW 2790:PSWAPD 2649:Opcode 2634:Athlon 2604:) and 1969:Opcode 1946:VIA C3 1924:Bobcat 1904:K6-III 1886:3DNow! 1870:ICERET 1868:named 1727:Opcode 1295:4FMAPS 1254:4FMAPS 702:Opcode 641:70..7F 580:BNDSTX 576:BNDLDX 560:BNDSTX 556:BNDLDX 349:Opcode 131:Opcode 9482:Flags 9436:(HLA) 9430:(GAS) 9094:AMD, 9069:VIA, 9004:AMD, 8776:NEC, 8759:NEC, 8697:(PDF) 8682:(PDF) 8658:(PDF) 8643:(PDF) 8618:(PDF) 8611:(PDF) 8521:AMD, 8504:AMD, 8428:AMD, 8399:AMD, 8382:AMD, 8243:AMD, 8230:(PDF) 8068:0000h 8040:DF FC 8025:DD FC 8010:DB FC 7988:D9 E6 7983:FTSTP 7972:DB F1 7950:DB E9 7944:FSBP3 7934:DB EA 7929:FSBP2 7919:DB EB 7914:FSBP1 7901:DB E8 7896:FSBP0 7886:DF E2 7866:DF E1 7838:DB E5 7829:DB F4 7796:80387 7734:D6 E6 7729:RETPM 7714:BRKPM 7694:M6117 7665:0F FE 7660:WARFE 7650:0F FD 7635:0F FB 7630:RARFE 7620:0F FA 7615:RARF0 7605:0F F9 7590:0F F8 7575:0F F7 7560:0F F6 7545:0F F5 7530:0F F4 7515:0F F3 7500:0F F2 7485:0F F1 7470:0F F0 7455:0F 3E 7450:RARF3 7440:0F 3D 7435:RARF2 7425:0F 3C 7420:RARF1 7410:0F 1E 7395:0F 1B 7380:0F 1A 7365:0F 19 7323:are: 7287:FE F8 7185:PAVEB 6754:WRSHR 6750:RDSHR 6734:0F 7E 6711:with 6692:0F AA 6667:0F 3A 6646:0F 39 6641:DMINT 6631:0F 3D 6616:0F 3C 6601:0F 3B 6580:0F 3A 6532:0F 38 6516:0F 38 6513:Uses 6507:0F 7E 6504:Uses 6498:0F 7E 6493:SMINT 6347:Geode 6343:Cyrix 6309:0F 7A 6297:0F 7D 6292:MRDEC 6285:0F 7C 6280:MHDEC 6273:0F 79 6261:0F 78 6249:0F 97 6244:MRENC 6237:0F 93 6232:MHENC 6225:0F 9B 6207:0F 9A 6202:ALBIT 6185:0F 9F 6129:BTCLR 6059:IRAM: 5986:0F 7F 5974:0F 7E 5962:0F 77 5950:0F 76 5938:8E /7 5926:8E /6 5914:8C /7 5888:8C /6 5865:63 ib 5836:F1 ib 5810:0F 9E 5742:0F 92 5727:0F 91 5696:BRKCS 5690:0F 25 5591:D8-DF 5581:D8-DF 5575:67 /r 5571:66 /r 5543:REPNC 5410:0F 26 5405:CMP4S 5392:0F 22 5387:SUB4S 5370:0F 20 5365:ADD4S 5135:XSAVE 4950:BEXTR 4278:FALSE 4276:VPCOM 4259:VPCOM 3023:mmmmm 2921:Bits 2776:PF2IW 2770:PI2FW 2766:PF2IW 2638:K6-2+ 2622:65 nm 2583:FEMMS 2575:FEMMS 2512:PFRCP 2501:PFRCP 2462:0F 0E 2457:FEMMS 2275:with 2233:with 1866:0F 07 1838:0F 07 1815:0F 07 1694:Am386 897:APX: 888:KNC: 763:Zen 5 620:FF /2 606:FF /4 540:BNDMK 398:BNDCL 394:BNDCU 390:BNDCL 229:CPUs. 227:Cyrix 108:Intel 9308:ISBN 9153:The 8929:NEC 8626:2014 8571:and 8546:and 8492:2022 8411:and 8350:ISBN 8294:ISBN 8058:The 7994:FTST 7961:F4X4 7692:The 7645:WGPR 7600:RGPR 7585:SCFG 7570:LCFG 7465:LTLB 7405:EPIC 7360:SRET 7259:CPUs 7217:PMV* 7207:For 6895:arg2 6893:and 6891:arg1 6774:EMMI 6762:NASM 6752:and 6726:NASM 6709:RSDC 6349:CPUs 6345:and 6180:IDLE 6047:DS3: 6032:DS2: 6008:and 5903:V55 5871:BRKS 5805:STOP 5737:FINT 5615:8080 5566:FPO2 5558:SCAS 5554:CMPS 5535:SCAS 5531:CMPS 5520:REPC 5450:ROL4 5113:and 5060:The 4948:For 4389:FMA4 4375:and 4365:Yes 4344:Yes 4314:swap 4112:Yes 4068:Yes 4035:Yes 4002:Yes 3966:Yes 3906:For 3247:Yes 3165:Yes 3144:Yes 3107:swap 3075:vvvv 3041:and 2924:7:0 2861:SSE5 2788:The 2768:and 2764:The 2636:and 2579:EMMS 2573:The 2532:MOVQ 2526:and 2514:and 2491:and 2213:and 1940:VIA 1933:IDT 1926:and 1914:and 1896:FP32 1892:K6-2 1846:RES3 1833:RES4 1810:RES3 1706:Elan 1246:SAE 1157:SAE 1074:SAE 905:GPRs 860:and 858:KNOT 854:KMOV 689:and 663:IRET 659:LOOP 643:and 631:and 617:and 611:CALL 603:and 578:and 574:The 558:and 554:The 538:For 396:and 116:i386 42:SIMD 36:Main 8690:AMD 8651:AMD 7833:or 7678:ALi 7525:WCD 7510:RCD 7495:WCT 7480:RCT 6899:imp 6882:mm6 6877:mm7 6872:mm4 6867:mm5 6862:mm2 6857:mm3 6852:mm0 6847:mm1 6837:mm7 6832:mm6 6827:mm5 6822:mm4 6817:mm3 6812:mm2 6807:mm1 6802:mm0 6697:RSM 6687:RSM 6662:RDM 6131:). 6010:LES 6006:LDS 5818:HLT 5621:INT 5585:x87 5089:.) 4401:Zen 4384:.) 4362:Yes 4341:Yes 4319:L=1 4312:W=1 4115:No 4083:No 4050:No 4017:No 3984:No 3969:No 3938:No 3935:Yes 3880:No 3877:No 3708:No 3705:No 3640:No 3637:No 3442:No 3439:No 3304:No 3301:No 3244:Yes 3207:No 3186:No 3112:L=1 3105:W=1 3057:0Ah 3044:0Ah 3031:POP 3006:pp 2981:8Fh 2880:XOP 2285:1.0 2273:mm1 2262:ulp 2243:1.0 2231:mm0 2221:mm0 1950:SSE 1928:Zen 1916:K10 1747:DR7 1736:SMI 1713:ICE 1686:AMD 667:F2h 657:), 651:BND 637:Jcc 625:RET 623:), 609:), 597:JMP 593:BND 527:67h 523:67h 498:BND 101:x86 9561:: 9293:^ 9277:^ 9251:^ 9056:. 9017:^ 8997:^ 8843:. 8830:^ 8821:. 8750:^ 8688:. 8684:. 8649:. 8645:. 8478:. 8467:^ 8407:, 8307:^ 8292:, 8275:^ 8201:^ 8111:^ 7963:, 7719:F1 7211:, 7192:^ 6741:^ 6713:CS 6331:. 6323:63 6064:F1 6052:D6 6037:63 5850:. 5587:. 5560:. 5548:65 5537:. 5525:64 5102:^ 4261:EQ 4230:^ 3204:No 3183:No 3162:No 3141:No 3084:pp 3037:, 2991:B̅ 2988:X̅ 2985:R̅ 2972:0 2948:0 2757:^ 2628:. 2522:, 2487:, 2264:. 2209:, 1952:.) 1922:, 1912:K8 1910:, 1908:K7 1741:F1 1392:) 1390:C7 1385:) 1383:C6 1338:^ 1326:No 1323:No 1285:No 1282:No 1243:No 1235:No 1222:ER 1205:23 1111:ER 1095:28 1036:ER 1020:28 856:, 741:F3 735:F3 722:F2 716:F2 661:, 655:EB 633:C3 629:C2 615:E8 601:E9 567:^ 547:^ 503:F2 392:, 264:. 223:). 176:. 9344:e 9337:t 9330:v 8879:. 8731:. 8706:. 8667:. 8628:. 8494:. 8449:. 8300:. 8232:. 7684:/ 7680:/ 7023:, 6689:( 5556:/ 5533:/ 3053:9 3049:8 3039:9 3035:8 3003:L 2997:W 2969:1 2966:2 2963:3 2960:4 2957:5 2954:6 2951:7 2945:1 2942:2 2939:3 2936:4 2933:5 2930:6 2927:7 2534:. 2507:. 2503:/ 2413:, 2289:X 2246:X 1198:2 1175:x 1171:2 1088:2 1013:2 88:e 81:t 74:v

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Knowledge (XXG)

List of discontinued x86 instructions

Index