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conference. A more complete description was given at
Microprocessor Forum 2003 on 14 October 2003. The POWER5 was not sold openly and was used exclusively by IBM and their partners. Systems using the microprocessor were introduced in 2004. The POWER5 competed in the high-end enterprise server market,
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As many resources such as the register files are shared by two threads, they are increased in capacity in many cases to compensate for the loss of performance. The number of integer and floating-point registers is increased to 120 each, from 80 integer and 72 floating-point registers in the POWER4.
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to 10-way. The unified L3 cache was brought on-package instead of located externally in separate chips. Its capacity was increased to 36 MB. Like the POWER4, the cache is shared by the two cores. The cache is accessed via two unidirectional 128-bit buses operating at half the core frequency.
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The POWER5+ is an improved iteration of the POWER5 introduced on 4 October 2005. Improvements initially were lower power consumption, due to the newer process it was fabricated in. The POWER5+ chip uses a 90 nm fabrication process. This resulted in the die size decrease from 389 mm to
795:
The POWER5+ was packaged in the same packages as previous POWER5 microprocessors, but was also available in a quad-chip module (QCM) containing two POWER5+ dies and two L3 cache dies, one for each POWER5+ die. These QCM chips ran at a clock frequency of between 1.5 and 1.8 GHz.
721:, instruction buffer, group completion unit and store queue so that each thread may have its own. Most resources, such as the register files and execution units, are shared, although each thread sees its own set of registers. The POWER5 implements
791:
Clock frequency was not increased at launch and remained between at 1.5 to 1.9 GHz. On 14 February 2006, new versions raised the clock frequency to 2.2 GHz and then to 2.3 GHz on 25 July 2006.
768:(MCM). The DCM contains one POWER5 die and its associated L3 cache die. The MCM contains four POWER5 dies and four L3 cache dies, one for each POWER5 die, and measures 95 mm by 95 mm.
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757:
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The floating-point issue queue is also increased in capacity to 24 entries from 20. The capacity of the L2 unified cache was increased to 1.875 MB and the
828:, in its Escala servers, and Hitachi, in its SR11000 computers with up to 128 POWER5+ microprocessors, which have several installations featured in the 2007
981:, a comparison and analysis of the POWER5 and Montecito, that explains the major changes between the POWER4 to the POWER5, along with performance estimates
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storage server, and as embedded microprocessors in its high-end
Infoprint printers. DCM POWER5 microprocessors are used by IBM in its high-end
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725:(SMT), where two threads are executed simultaneously. The POWER5 can disable SMT to optimize for the current workload.
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The POWER5 contains 276 million transistors and has an area of 389 mm. It is fabricated by IBM in a 0.13 ÎĽm
722:
661:
536:
886:
270:
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Kalla, Ron; Sinharoy, Balaram; Tendler, Joel M. (2004). "IBM Power5 Chip: A Dual-Core
Multithreaded Processor".
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list of supercomputers. IBM uses the POWER5+ QCM in its System p5 510Q, 520Q, 550Q and 560Q servers.
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memory. It uses high-frequency serial buses to communicate with external buffers that interface the
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IBM System p5 Quad-Core Module Based on POWER5+ Technology: Technical
Overview and Introduction
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Clabes, Joachim et al. (2004). "Design and
Implementation of the POWER5 Microprocessor".
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Several POWER5 processors in high-end systems can be coupled together to act as a single
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A MCM containing four POWER5 dies and four 36 MB L3 cache dies. Measuring 3.75in x 3.75in
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and two logical threads, for a total of two physical threads and four logical threads.
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A High-Performance IBM Power5+ p5-575 Cluster 1600 and DDN S2A9550 Storage
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Technical details of the microprocessor were first presented at the 2003
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Glaskowsky, Peter N. (14 October 2003). "IBM Raises
Curtain on Power5".
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Proceedings of 2004 IEEE International Solid-State
Circuits Conference
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764:. The POWER5 die is packaged in either a dual chip module (DCM) or a
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Processor module from an IBM i5 system, containing a POWER5+ DCM
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Krewell, Kevin (22 December 2003). "Power5 Tops On
Bandwidth".
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workstation. Third-party users of POWER5 microprocessors are
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The on-die memory controller supports up to 64 GB of
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microprocessor, with each core supporting one physical
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2 way POWER5 CPU, heat-sink removed (damaged CPU die)
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660:. The principal improvements are support for
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8:
624:IBM POWER5+ 8-way MCM CPUs and cache chips.
19:
908:"IBM Previews Power5". (8 September 2003).
848:Glaskowsky, "IBM Raises Curtain on Power5".
709:The POWER5 is a further development of the
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953:IBM Journal of Research and Development
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758:complementary metal–oxide–semiconductor
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960:"IBM pumps Unix line full of Power5+"
200:NXP (formerly Freescale and Motorola)
16:2004 family of multiprocessors by IBM
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857:Krewell, "Power5 Tops On Bandwidth".
760:(CMOS) process with eight layers of
656:. It is an improved version of the
14:
979:Sizing up the Super Heavyweights
958:Vance, Ashlee (4 October 2005).
640:IBM POWER5+ 8-way MCM side view.
632:IBM POWER5+ 8-way MCM Interface.
779:(Virtual Vector Architecture).
749:(DIMMs) to the microprocessor.
109:Architecture and classification
808:POWER5 microprocessors in its
1:
822:IntelliStation POWER 285
652:developed and fabricated by
72:1.5 GHz to 2.3 GHz
723:simultaneous multithreading
662:simultaneous multithreading
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987:, Texas A&M University
747:dual inline memory modules
713:. The addition of two-way
887:IBM Power microprocessors
689:mostly against the Intel
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816:server families, in its
207:PowerPC e series (2006)
1006:PowerPC microprocessors
775:by a technology called
134:Physical specifications
1011:64-bit microprocessors
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340:PowerPC series (1992)
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927:Microprocessor Report
911:Microprocessor Report
804:IBM uses the DCM and
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104:36 MB/chip (off-chip)
754:silicon on insulator
664:(SMT) and an on-die
507:OpenPOWER Foundation
125:Instruction set
115:Technology node
1001:IBM microprocessors
762:copper interconnect
37:General information
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668:. The POWER5 is a
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560:historic in italic
388:RAD series (1997)
244:Qor series (2008)
766:multi-chip module
731:set-associativity
666:memory controller
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556:Cancelled in gray
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129:PowerPC 2.02
826:Groupe Bull
705:Description
160:Predecessor
58:Performance
50:Designed by
995:Categories
936:IEEE Micro
903:References
474:PWRficient
68:clock rate
31:POWER5 MCM
699:SPARC64 V
691:Itanium 2
686:Hot Chips
670:dual-core
527:Power.org
522:Blue Gene
193:Power ISA
170:Successor
876:See also
800:Products
450:Espresso
443:Broadway
101:L3 cache
93:L2 cache
42:Launched
892:PowerPC
783:POWER5+
680:History
547:AltiVec
404:RAD5500
393:RAD6000
377:(2010)
332:Power10
253:Qorivva
189:PowerPC
155:History
897:POWER6
830:TOP500
818:DS8000
756:(SOI)
711:POWER4
674:thread
658:POWER4
646:POWER5
420:(1996)
418:series
399:RAD750
327:POWER9
322:POWER8
317:POWER7
312:POWER6
306:POWER5
299:POWER4
292:POWER3
285:POWER2
278:POWER1
191:, and
174:POWER6
164:POWER4
20:POWER5
836:Notes
648:is a
484:Xenon
468:Titan
459:Other
436:Gekko
271:Power
248:QorIQ
236:e6500
231:e5500
185:POWER
140:Cores
84:cache
77:Cache
63:Max.
812:and
777:ViVA
743:DDR2
741:and
644:The
542:CHRP
537:PReP
532:PAPR
517:RISC
490:X704
479:Cell
416:RS64
362:74xx
226:e600
221:e500
216:e300
211:e200
45:2004
806:MCM
739:DDR
654:IBM
383:A2O
380:A2I
369:970
356:7xx
351:4xx
345:6xx
263:IBM
82:L1
65:CPU
53:IBM
997::
962:.
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375:A2
187:,
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948:.
939:.
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914:.
585:e
578:t
571:v
147:2
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