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Process design kit

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to their specific design styles and markets. The designers use the PDK to design, simulate, draw and verify the design before handing the design back to the foundry to produce chips. The data in the PDK is specific to the foundry's process variation and is chosen early in the design process, influenced by the market requirements for the chip. An accurate PDK will increase the chances of first-pass successful silicon.
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to model a fabrication process for the design tools used to design an integrated circuit. The PDK is created by the foundry defining a certain technology variation for their processes. It is then passed to their customers to use in the design process. The customers may enhance the PDK, tailoring it
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Different tools in the design flow have different input formats for the PDK data. The PDK engineers have to decide which tools they will support in the design flows and create the libraries and rule sets which support those flows.
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Ian Robertson, Nutapong Somjit, Mitchai Chongcheawchamnan, "Process design kits for RFIC and MMIC design", section 17.8.1 in,
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A PDK may also include standard cell libraries from the foundry, a library vendor or developed internally
28: 77: 67: 117: 218:, "Silicon photonics integrated circuit process design kit", section 4.8 in, Alan Willner (ed), 238: 223: 204: 189: 265: 308: 199:
Lukas Chrostowski, Michael Hochberg, "Process design kit (PDK)", section 10.1 in,
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Microwave and Millimetre-Wave Design for Wireless Communications
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Predictive Technology Model for Robust Nanoelectronic Design
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A user friendly representation of the process requirements
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Yu Cao, "Predictive process design kits", ch. 8 in,
120:of primitive devices (SPICE or SPICE derivatives) 188:, Springer Science & Business Media, 2011 289: 8: 296: 282: 90:Layers, layer names, layer/purpose pairs 264:This electronics-related article is a 7: 254: 252: 93:Colors, fills and display attributes 27:) is a set of files used within the 16:Tools for modelling chip fabrication 203:, Cambridge University Press, 2015 14: 78:Antenna and Electrical rule check 315:Semiconductor device fabrication 256: 220:Optical Fiber Telecommunications 157:format of abstracted layout data 237:, John Wiley & Sons, 2016 1: 268:. You can help Knowledge by 112:Tool dependent rule formats 48:A primitive device library 336: 251: 222:, vol. 11, Elsevier, 2019 201:Silicon Photonics Design 44:A typical PDK contains: 123:Transistors (typically 73:Layout Versus Schematic 29:semiconductor industry 163:Library (.lib) files 68:Design Rule Checking 64:Verification checks 141:Design Rule Manual 96:Process constraints 82:Physical Extraction 21:process design kit 320:Electronics stubs 277: 276: 118:Simulation models 54:Device parameters 327: 298: 291: 284: 260: 253: 99:Electrical rules 87:Technology data 335: 334: 330: 329: 328: 326: 325: 324: 305: 304: 303: 302: 249: 181: 179:Further reading 176: 38: 17: 12: 11: 5: 333: 331: 323: 322: 317: 307: 306: 301: 300: 293: 286: 278: 275: 274: 261: 247: 246: 231: 214:Michael Liehr 212: 197: 180: 177: 175: 172: 171: 170: 164: 161: 158: 148: 147: 146: 145: 139: 138: 137: 134: 131: 128: 115: 114: 113: 110: 102: 101: 100: 97: 94: 91: 85: 84: 83: 80: 75: 70: 62: 61: 60: 55: 52: 37: 34: 15: 13: 10: 9: 6: 4: 3: 2: 332: 321: 318: 316: 313: 312: 310: 299: 294: 292: 287: 285: 280: 279: 273: 271: 267: 262: 259: 255: 250: 244: 240: 236: 232: 229: 225: 221: 217: 213: 210: 206: 202: 198: 195: 191: 187: 183: 182: 178: 173: 168: 165: 162: 159: 156: 153: 152: 151: 143: 142: 140: 135: 132: 129: 126: 122: 121: 119: 116: 111: 109: 106: 105: 103: 98: 95: 92: 89: 88: 86: 81: 79: 76: 74: 71: 69: 66: 65: 63: 59: 56: 53: 50: 49: 47: 46: 45: 42: 35: 33: 30: 26: 22: 270:expanding it 263: 248: 234: 219: 215: 200: 185: 149: 43: 39: 24: 20: 18: 169:layout data 104:Rule files 36:Description 309:Categories 243:1118917219 228:0128165022 209:1107085454 194:1461404452 174:References 130:Capacitors 136:Inductors 133:Resistors 160:Symbols 51:Symbols 241:  226:  216:et al. 207:  192:  58:PCells 167:GDSII 125:SPICE 266:stub 239:ISBN 224:ISBN 205:ISBN 190:ISBN 155:LEF 108:LEF 25:PDK 311:: 19:A 297:e 290:t 283:v 272:. 245:. 230:. 211:. 196:. 127:) 23:(

Index

semiconductor industry
PCells
Design Rule Checking
Layout Versus Schematic
Antenna and Electrical rule check
LEF
Simulation models
SPICE
LEF
GDSII
ISBN
1461404452
ISBN
1107085454
ISBN
0128165022
ISBN
1118917219
Stub icon
stub
expanding it
v
t
e
Categories
Semiconductor device fabrication
Electronics stubs

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