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227:). In more complex instances of the architecture, separate QPI link pairs connect one or more processors and one or more IO hubs or routing hubs in a network on the motherboard, allowing all of the components to access other components via the network. As with HyperTransport, the QuickPath Architecture assumes that the processors will have integrated
254:
operate using 10+1 or even 5+1 remaining signals, even reassigning the clock to a data signal if the clock fails. The initial
Nehalem implementation used a full four-quadrant interface to achieve 25.6 GB/s (6.4GT/s Ă— 1 byte Ă— 4), which provides exactly double the theoretical bandwidth of Intel's 1600 MHz FSB used in the X48 chipset.
250:, which has 8 bits for error detection, 8 bits for "link-layer header", and 64 bits for data. One 80-bit flit is transferred in two clock cycles (four 20-bit transfers, two per clock tick.) QPI bandwidths are advertised by computing the transfer of 64 bits (8 bytes) of data every two clock cycles in each direction.
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The routing layer sends a 72-bit unit consisting of an 8-bit header and a 64-bit payload. The header contains the destination and the message type. When the routing layer receives a unit, it examines its routing tables to determine if the unit has reached its destination. If so it is delivered to the
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Intel describes the data throughput (in GB/s) by counting only the 64-bit data payload in each 80-bit flit. However, Intel then doubles the result because the unidirectional send and receive link pair can be simultaneously active. Thus, Intel describes a 20-lane QPI link pair (send and receive) with
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The transport layer is not needed and is not present in devices that are intended for only point-to-point connections. This includes the Core i7. The transport layer sends and receives data across the QPI network from its peers on other devices that may not be directly connected (i.e., the data may
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The link layer is responsible for sending and receiving 80-bit flits. Each flit is sent to the physical layer as four 20-bit phits. Each flit contains an 8-bit CRC generated by the link layer transmitter and a 72-bit payload. If the link layer receiver detects a CRC error, the receiver notifies the
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The physical layer comprises the actual wiring and the differential transmitters and receivers, plus the lowest-level logic that transmits and receives the physical-layer unit. The physical-layer unit is the 20-bit "phit." The physical layer transmits a 20-bit "phit" using a single clock edge on 20
329:
the QPI operates at a clock rate of 2.4 GHz, 2.93 GHz, 3.2 GHz, 3.6 GHz, 4.0 GHz or 4.8 GHz (3.6 GHz and 4.0 GHz frequencies were introduced with the Sandy Bridge-E/EP platform and 4.8 GHz with the
Haswell-E/EP platform). The clock rate for a particular
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Although the initial implementations use single four-quadrant links, the QPI specification permits other implementations. Each quadrant can be used independently. On high-reliability servers, a QPI link can operate in a degraded mode. If one or more of the 20+1 signals fails, the interface will
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using a credit/debit scheme to prevent the receiver's buffer from overflowing. The link layer supports six different classes of message to permit the higher layers to distinguish data flits from non-data messages primarily for maintenance of cache coherence. In complex implementations of the
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lanes when all 20 lanes are available, or on 10 or 5 lanes when the QPI is reconfigured due to a failure. Note that in addition to the data signals, a clock signal is forwarded from the transmitter to receiver (which simplifies clock recovery at the expense of additional pins).
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next-higher layer. If not, it is sent on the correct outbound QPI. On a device with only one QPI, the routing layer is minimal. For more complex implementations, the routing layer's routing tables are more complex, and are modified dynamically to avoid failed QPI links.
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link depends on the capabilities of the components at each end of the link and the signal characteristics of the signal path on the printed circuit board. The non-extreme Core i7 9xx processors are restricted to a 2.4 GHz frequency at stock reference clocks.
372:, with separate physical, link, routing, transport, and protocol layers. In devices intended only for point-to-point QPI use with no forwarding, such as the Core i7-9xx and Xeon DP processors, the transport layer is not present and the routing layer is minimal.
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a 3.2 GHz clock as having a data rate of 25.6 GB/s. A clock rate of 2.4 GHz yields a data rate of 19.2 GB/s. More generally, by this definition a two-link 20-lane QPI transfers eight bytes per clock cycle, four in each direction.
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QuickPath architecture, the link layer can be configured to maintain separate flows and flow control for the different classes. It is not clear if this is needed or implemented for single-processor and dual-processor implementations.
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The protocol layer sends and receives packets on behalf of the device. A typical packet is a memory cache row. The protocol layer also participates in maintenance of cache coherence by sending and receiving relevant
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processors (as it was on
Clarkdale, for example), the internal ring interconnect between on-die cores is also based on the principles behind QPI, at least as far as
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have been routed through an intervening device.) the transport layer verifies that the data is complete, and if not, it requests retransmission from its peer.
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Although some high-end Core i7 processors expose QPI, other "mainstream" Nehalem desktop and mobile processors intended for single-socket boards (e.g.
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Interfaces are listed by their speed in the (roughly) ascending order, so the interface at the end of each section should be the fastest.
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and successor families) do not expose QPI externally, because these processors are not intended to participate in multi-socket systems.
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and GPU, if present; the uncore may or may not be on the same die as the CPU core, for instance it is on a separate die in the
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Bit transfers occur on both the rising and the falling edges of the clock, so the transfer rate is double the clock rate.
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Thus, there is no need to incur the expense of exposing the (former) front-side bus interface via the processor socket.
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transmitter via a flit on the return link of the pair and the transmitter resends the flit. The link layer implements
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In post-2009 single-socket chips starting with
Lynnfield, Clarksfield, Clarkdale and Arrandale, the traditional
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799:"QPI, Integrated Memory, PCI Express, And LGA 1156 - Intel Core i5 And Core i7: Intel's Mainstream Magnum Opus"
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Although sometimes called a "bus", QPI is a point-to-point interconnect. It was designed to compete with
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773:"Intel Demonstrates Industry's First 32nm Chip and Next-Generation Nehalem Microprocessor Architecture"
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Transitioning the Intel® Next
Generation Microarchitectures (Nehalem and Westmere) into the Mainstream
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functions are integrated into these processors, which therefore communicate externally via the slower
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Development Group, which Intel had acquired from Compaq and HP and in turn originally came from
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SoftPedia: Intel Plans to
Replace Xeon with Its New Skylake-Based “Purley” Super Platform
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Please help update this article to reflect recent events or newly available information.
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Each QPI comprises two 20-lane point-to-point data links, one in each direction (
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in March 2009 and
Itanium processors in February 2010 (code named Tukwila).
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105:). Earlier incarnations were known as Yet Another Protocol (YAP) and YAP+.
856:"Intel Clarkdale 32nm CPU-and-GPU chip benchmarked (again) - CPU - Feature"
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However, QPI is used internally on these chips to communicate with the "
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Intel first delivered it for desktop processors in
November 2008 on the
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Although the core–uncore QPI link is not present in desktop and mobile
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881:"2nd Generation Intel Core Processor Family: Intel Core i7, i5 and i3"
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276:", which is part of the chip containing memory controllers, CPU-side
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590:"Everything You Need to Know About The QuickPath Interconnect (QPI)"
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The QPI is an element of a system architecture that Intel calls the
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Published on 25th
January 2010 by Richard Swinburne (2010-01-25).
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QPI 1.1 is a significantly revamped version introduced with
759:"Intel® Xeon® Processor Scalable Family Technical Overview"
155:(DEC). Its development had been reported as early as 2004.
662:"The Common System Interface: Intel's Future Interconnect"
981:
The Common System
Interface: Intel’s Future Interconnect
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Core i3, Core i5, and other Core i7 processors from the
516:"Intel CSI name revealed: Slow, slow, quick quick slow"
616:"Intel Intel gets knickers in a twist over Tanglewood"
471:"An Introduction to the Intel QuickPath Interconnect"
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An Introduction to the Intel QuickPath Interconnect
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622:. Archived from the original on September 3, 2010
968:First Look at Nehalem Microarchitecture: QPI Bus
688:"Intel's Whitefield takes four core IA-32 shape"
169:. It was released in Xeon processors code-named
1646:Coherent Accelerator Processor Interface (CAPI)
956:What you need to know about Intel’s Nehalem CPU
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821:"Feature - Intel GMA HD Graphics Performance"
522:. Archived from the original on June 10, 2012
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694:. Archived from the original on May 24, 2009
840:: CS1 maint: numeric names: authors list (
729:"Intel's Tukwila Confirmed to be Quad Core"
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1155:Advanced Programmable Interrupt Controller
1119:Intel Communication Streaming Architecture
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1197:High-bandwidth Digital Content Protection
63:Processor interconnect developed by Intel
977:, November 2, 2008, by Ilya Gavrichenkov
350:Ă— 16(20) (data bits/QPI link width)
614:Charlie Demerjian (December 13, 2005).
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1242:Platform Environment Control Interface
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943:Intel QuickPath Interconnect Overview
476:. Intel Corporation. January 30, 2009
7:
1227:Host Embedded Controller Interface
983:, August 28, 2007, by David Kanter
588:Gabriel Torres (August 25, 2008).
25:
340:The rate is computed as follows:
215:that implements what Intel calls
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660:David Kanter (August 28, 2007).
347:Ă— 2 bits/Hz (double data rate)
31:
925:, Hot Chips 21, August 24, 2009
686:Eva Glass (December 12, 2004).
964:, April 9, 2008, by Jon Stokes
1:
1641:Intel Ultra Path Interconnect
797:Chris Angelini (2009-09-07).
178:Intel Ultra Path Interconnect
153:Digital Equipment Corporation
127:-SP Xeon processors based on
121:Intel Ultra Path Interconnect
1619:Intel QuickPath Interconnect
1609:Direct Media Interface (DMI)
1185:Active Management Technology
1114:MultiProcessor Specification
914:Lily Looi, Stephan Jourdan,
727:David Kanter (May 5, 2006).
557:"Intel's Quick Path Evolved"
303:and PCI Express interfaces.
68:Intel QuickPath Interconnect
555:David Kanter (2011-07-20).
504:, retrieved August 21, 2007
2097:
1604:Compute Express Link (CXL)
879:Oded Lempel (2013-07-28).
514:Eva Glass (May 16, 2007).
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1841:IEEE-1284 (parallel port)
1756:logical device interface)
712:: CS1 maint: unfit URL (
640:: CS1 maint: unfit URL (
540:: CS1 maint: unfit URL (
439:List of device bandwidths
356:Ă· 8 (bits/byte)
233:non-uniform memory access
176:It was supplanted by the
40:This article needs to be
1222:Serial Digital Video Out
1212:Rapid Storage Technology
321:Frequency specifications
180:starting in 2017 on the
1267:Ultra Path Interconnect
1252:Platform Controller Hub
1180:Intel Management Engine
858:. HEXUS.net. 2009-09-25
370:five-layer architecture
99:Common System Interface
1403:List of bus bandwidths
1283:Silicon Photonics Link
1247:QuickPath Interconnect
368:QPI is specified as a
213:QuickPath architecture
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145:Advanced Micro Devices
143:that had been used by
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1257:System Management Bus
1202:High Definition Audio
1109:Common Building Block
424:Elastic interface bus
235:(NUMA) architecture.
203:component in Intel's
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1846:IEEE-1394 (FireWire)
1584:PCI Extended (PCI-X)
217:QuickPath technology
119:QPI was replaced by
1687:Parallel ATA (PATA)
559:. Realworldtech.com
327:synchronous circuit
85:which replaced the
1594:PCI Express (PCIe)
973:2016-05-14 at the
948:2014-02-02 at the
921:2020-08-02 at the
801:. Tomshardware.com
500:2013-10-17 at the
229:memory controllers
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1771:Apple Desktop Bus
1748:PCI Express (via
1707:Serial ATA (SATA)
1393:Network on a chip
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1124:Intel Inboard 386
244:differential pair
160:Intel Core i7-9xx
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2007:Multidrop bus
2005:
2004:
2002:
1998:
1992:
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1971:
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1914:External PCIe
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1894:Parallel SCSI
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1786:Commodore bus
1784:
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1734:Fibre Channel
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1401:
1399:
1398:Plug and play
1396:
1394:
1391:
1389:
1388:Bus mastering
1386:
1384:
1381:
1379:
1376:
1374:
1371:
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1366:
1364:
1363:Back-side bus
1361:
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920:
917:
911:
908:
897:on 2020-07-29
893:
889:
882:
875:
873:
869:
857:
851:
848:
843:
837:
822:
815:
812:
800:
793:
790:
779:on 2008-01-02
778:
774:
768:
765:
760:
754:
751:
743:September 13,
738:
734:
730:
723:
720:
715:
709:
698:September 13,
693:
689:
682:
679:
667:
663:
656:
654:
652:
648:
643:
637:
626:September 13,
621:
617:
610:
607:
595:
591:
584:
581:
578:
573:
570:
558:
551:
548:
543:
537:
526:September 13,
521:
517:
510:
507:
503:
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496:
491:
488:
472:
466:
464:
460:
454:
450:
447:
445:
442:
440:
437:
435:
432:
430:
427:
425:
422:
421:
417:
411:
408:
404:
401:
397:
395:Routing layer
394:
390:
385:
382:
378:
375:
374:
373:
371:
363:
358:
355:
352:
349:
346:
343:
342:
341:
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331:
328:
320:
318:
316:
312:
307:
304:
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298:
293:
291:
287:
283:
279:
275:
270:
268:
264:
260:
255:
251:
249:
245:
241:
236:
234:
230:
226:
222:
221:Intel Core i7
218:
214:
206:
202:
197:
190:
188:
186:
183:
179:
174:
172:
168:
165:
161:
156:
154:
150:
146:
142:
134:
132:
130:
126:
122:
117:
115:
111:
106:
104:
100:
96:
92:
88:
84:
81:developed by
80:
77:
73:
69:
55:
43:
38:
29:
28:
19:
2081:Serial buses
1618:
1539:TURBOchannel
1329:
1246:
1190:AMT versions
1102:Discontinued
961:Ars Technica
959:
910:
899:. Retrieved
892:the original
888:hotchips.org
887:
860:. Retrieved
850:
825:. Retrieved
814:
803:. Retrieved
792:
781:. Retrieved
777:the original
767:
753:
741:. Retrieved
737:the original
732:
722:
696:. Retrieved
692:The Inquirer
691:
681:
669:. Retrieved
665:
624:. Retrieved
620:The Inquirer
619:
609:
597:. Retrieved
593:
583:
572:
561:. Retrieved
550:
524:. Retrieved
520:The Inquirer
519:
509:
490:
478:. Retrieved
389:flow control
367:
339:
335:
332:
324:
311:Sandy Bridge
308:
305:
294:
271:
256:
252:
237:
216:
212:
210:
187:platforms.
175:
157:
138:
118:
107:
102:
98:
79:interconnect
71:
67:
65:
52:January 2014
49:
41:
2012:CoreConnect
1991:ExpressCard
1919:Thunderbolt
1909:Camera Link
1692:Bus and Tag
1378:Address bus
1373:Control bus
1368:Daisy chain
1262:Thunderbolt
599:January 23,
444:PCI Express
359:= 25.6 GB/s
297:northbridge
278:PCI Express
267:Clarksfield
240:full duplex
116:platform).
2065:Categories
1865:ACCESS.bus
1764:Peripheral
1564:InfiniBand
1559:HP GSC bus
1353:System bus
1129:Intel Play
1068:Skulltrail
1038:Centrino 2
1020:technology
901:2014-01-21
862:2014-01-21
827:2014-01-21
805:2014-01-21
783:2007-12-31
671:August 14,
563:2014-01-21
455:References
383:Link layer
199:QPI is an
185:Skylake-SP
135:Background
1826:Lightning
1776:Atari SIO
1651:SpaceWire
1484:Zorro III
1424:S-100 bus
1419:SS-50 bus
1412:Standards
1332:standards
1325:Technical
1237:Omni-Path
1217:SpeedStep
1063:Ultrabook
1026:Platforms
708:cite news
636:cite news
536:cite news
413:messages.
290:Arrandale
286:Clarkdale
263:Lynnfield
123:(UPI) in
89:(FSB) in
76:processor
2052:Category
2027:Wishbone
2000:Embedded
1979:Portable
1899:Profibus
1831:DMX512-A
1717:Parallel
1569:Ethernet
1479:Zorro II
1429:Multibus
1330:de facto
1276:Upcoming
1033:Centrino
971:Archived
946:Archived
919:Archived
836:cite web
498:Archived
480:June 14,
418:See also
325:Being a
282:Westmere
259:LGA 1156
131:socket.
129:LGA 3647
2032:SLIMbus
1986:PC Card
1970:TOSLINK
1660:Storage
1614:RapidIO
1494:FASTBUS
1449:STD Bus
1346:General
1148:Current
1078:Galileo
449:RapidIO
344:3.2 GHz
284:-based
205:Nehalem
171:Nehalem
167:chipset
125:Skylake
95:Itanium
42:updated
1965:S/PDIF
1856:1-Wire
1821:RS-485
1816:RS-423
1811:RS-422
1806:RS-232
1667:ST-506
1624:NVLink
1474:STEbus
1434:Unibus
1083:Edison
1053:Tablet
274:uncore
223:to an
201:uncore
114:Romley
1960:McASP
1928:Audio
1873:SMBus
1869:PMBus
1851:UNI/O
1791:HP-IL
1744:SATAe
1729:ESCON
1702:HIPPI
1534:NuBus
1489:CAMAC
1459:Q-Bus
1454:SMBus
1439:VAXBI
1336:wired
1139:MMC-2
1134:MMC-1
1088:Curie
1018:Intel
952:(PDF)
895:(PDF)
884:(PDF)
474:(PDF)
149:Alpha
83:Intel
2017:AMBA
1955:MADI
1940:AES3
1801:MIDI
1754:NVMe
1750:AHCI
1712:SCSI
1697:DSSI
1672:ESDI
1549:SBus
1509:EISA
1444:MBus
1334:for
1327:and
1170:vPro
1160:CNVi
1058:CULV
1043:Viiv
842:link
745:2013
714:link
700:2013
673:2014
642:link
628:2013
601:2017
542:link
528:2013
482:2011
248:flit
182:Xeon
162:and
91:Xeon
66:The
2021:AXI
1950:I²S
1904:USB
1889:D²B
1884:SPI
1879:I3C
1861:I²C
1796:HIL
1781:DCB
1752:or
1739:SSA
1722:SAS
1682:SMD
1677:IPI
1599:AGP
1589:PXI
1579:PCI
1574:UPA
1554:VLB
1544:MCA
1529:VPX
1524:VXS
1519:VXI
1514:VME
1499:LPC
1469:ISA
1093:Evo
1073:NUC
1048:MID
301:DMI
225:X58
164:X58
103:CSI
72:QPI
18:QPI
2067::
1871:,
1867:,
958:,
886:.
871:^
838:}}
834:{{
731:.
710:}}
706:{{
690:.
664:.
650:^
638:}}
634:{{
618:.
592:.
538:}}
534:{{
518:.
462:^
292:.
93:,
2023:)
2019:(
1875:)
1863:(
1317:e
1310:t
1303:v
1010:e
1003:t
996:v
904:.
865:.
844:)
830:.
808:.
786:.
761:.
747:.
716:)
702:.
675:.
644:)
630:.
603:.
566:.
544:)
530:.
484:.
288:/
265:/
112:(
101:(
70:(
54:)
50:(
44:.
20:)
Text is available under the Creative Commons Attribution-ShareAlike License. Additional terms may apply.
