857:. Ethernet is a robust approach to linking computers over large geographic areas, where network topology may change unexpectedly, the protocols used are in flux, and link latencies are large. To meet these challenges, systems based on Ethernet require significant amounts of processing power, software and memory throughout the network to implement protocols for flow control, data transfer, and packet routing. RapidIO is optimized for energy efficient, low latency, processor-to-processor communication in fault tolerant embedded systems that span geographic areas of less than one kilometer.
743:
and retreats, waiting for the "winning" host. The winning host completes enumeration, including seizing ownership of the losing host. Once enumeration is complete, the winning host releases ownership of the losing host. The losing host then discovers the system by reading the switch routing tables and registers on each endpoint to learn the system configuration. If the winning host does not complete enumeration in a known time period, the losing host determines that the winning host has failed and completes enumeration.
613:
Because the ackID is specific to a link, the ackID is not covered by CRC, but by protocol. This allows the ackID to change with each link it passes over, while the packet CRC can remain a constant end-to-end integrity check of the packet. When a packet is successfully received, it is acknowledged using the ackID of the packet. A transmitter must retain a packet until it has been successfully acknowledged by the link partner.
473:
sufficient for a given type of architecture need and requirement. Unfortunately, for next generation missions a more capable avionics architecture is desired; which is well beyond the capabilities levied by existing architectures. A viable option for the design and development of these next generation architectures is to leverage existing commercial protocols capable of accommodating high levels of data transfer.
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Torus unified fabric is routed as a torus ring configuration connecting up to 45 server cartridges. Hence, capable of providing 5Gbs per lane connections in each direction to its north, south, east and west neighbors. This allows the system to meet many unique HPC applications where efficient localized traffic is needed.
620:
The physical layer contribution to RapidIO packets is a 2-byte header at the beginning of each packet that includes the ackID and physical priority, and a final 2-byte CRC value to check the integrity of the packet. Packets larger than 80 bytes also have an intermediate CRC after the first 80 bytes.
616:
The second value is the packet's physical priority. The physical priority is composed of the
Virtual Channel (VC) identifier bit, the Priority bits, and the Critical Request Flow (CRF) bit. The VC bit determines if the Priority and CRF bits identify a Virtual Channel from 1 to 8, or are used as the
481:
78 called SpaceVPX or High
ReliabilityVPX. The NGSIS requirements committee developed extensive requirements criteria with 47 different elements for the NGSIS interconnect. Independent trade study results by NGSIS member companies demonstrated the superiority of RapidIO over other existing commercial
472:
The interconnect or "bus" is one of the critical technologies in the design and development of spacecraft avionic systems that dictate its architecture and level of complexity. There are a host of existing architectures that are still in use given their level of maturity. These existing systems are
729:
The Data
Streaming specification also defines Extended Header flow control packet formats and semantics to manage performance within a client-server system. Each client uses extended header flow control packets to inform the server of the amount of work that could be sent to the server. The server
725:
The Data
Streaming specification supports messaging with different packet formats and semantics than the Messaging specification. Data Streaming packet formats support the transfer of up to 64K of data, segmented over multiple packets. Each transfer is associated with a Class of Service and Stream
699:
The
Messaging specification defines Doorbells and Messages. Doorbells communicate a 16-bit event code. Messages transfer up to 4KiB of data, segmented into up to 16 packets each with a maximum payload of 256 bytes. Response packets must be sent for each Doorbell and Message request. The response
476:
In 2012, RapidIO was selected by the Next
Generation Spacecraft Interconnect Standard (NGSIS) working group to serve as the foundation for standard communication interconnects to be used in spacecraft. The NGSIS is an umbrella standards effort that includes RapidIO Version 3.1 development, and a box
754:
RapidIO supports high availability, fault tolerant system design, including hot swap. The error conditions that require detection, and standard registers to communicate status and error information, are defined. A configurable isolation mechanism is also defined so that when it is not possible to
849:
is targeted at the host to peripheral market, as opposed to embedded systems. Unlike RapidIO, PCIe is not optimized for peer-to-peer multi processor networks. PCIe is ideal for host to peripheral communication. PCIe does not scale as well in large multiprocessor peer-to-peer systems, as the basic
742:
Each system host recursively enumerates the RapidIO fabric, seizing ownership of devices, allocating device IDs to endpoints and updating switch routing tables. When a conflict for ownership occurs, the system host with the larger deviceID wins. The "losing" host releases ownership of its devices
633:
Control symbols are used to delimit packets (Start of Packet, End of Packet, Stomp), to acknowledge packets (Packet
Acknowledge, Packet Not Acknowledged), reset (Reset Device, Reset Port) and to distribute events within the RapidIO system (Multicast Event Control Symbol). Control symbols are also
612:
Every packet has two values that control the physical layer exchange of that packet. The first is an acknowledge ID (ackID), which is the link-specific, unique, 5-, 6-, or 12-bit value that is used to track packets exchanged on a link. Packets are transmitted with serially increasing ackID values.
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Data center and HPC analytics systems have been deployed using a RapidIO 2D Torus Mesh Fabric, that provides a high speed general purpose interface among the system cartridges. This allows for applications that benefit from high bandwidth to low latency node-to-node communication. The RapidIO 2D
450:
RapidIO fabrics are used in cellular infrastructure 3G, 4G and LTE networks with millions of RapidIO ports shipped into wireless base stations worldwide. RapidIO fabrics were originally designed to support connecting different types of processors from different manufacturers together in a single
408:
Structurally
Asymmetric Link behavioral definition and standard register interface. These structurally Asymmetric Links carry much more data in one direction than the other, for applications such as sensors or processing pipelines. Unlike dynamic asymmetric links, Structurally Asymmetric Links
738:
Systems with a known topology can be initialized in a system specific manner without affecting interoperability. The RapidIO system initialization specification supports system initialization when system topology is unknown or dynamic. System initialization algorithms support the presence of
708:
The Flow
Control specification defines packet formats and protocols for simple XON/XOFF flow control operations. Flow control packets can be originated by switches and endpoints. Reception of a XOFF flow control packet halts transmission of a flow or flows until an XON flow control packet is
700:
packet status value indicates done, error, or retry. A status of retry requests the originator of the request to send the packet again. The logical level retry response allows multiple senders to access a small number of shared reception resources, leading to high throughput with low power.
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RapidIO switches use the destID of received packets to determine the output port or ports that should forward the packet. Typically, the destID is used to index into an array of control values. The indexing operation is fast and low cost to implement. RapidIO switches support a standard
654:
Every RapidIO endpoint is uniquely identified by a Device
Identifier (deviceID). Each RapidIO packet contains two device IDs. The first is the destination ID (destID), which indicates where the packet should be routed. The second is the source ID (srcID), which indicates where the packet
637:
The error recovery procedure is very fast. When a receiver detects a transmission error in the received data stream, the receiver causes its associated transmitter to send a Packet Not Accepted control symbol. When the link partner receives a Packet Not Accepted control symbol, it stops
617:
priority within Virtual Channel 0. Virtual Channels are assigned guaranteed minimum bandwidths. Within Virtual Channel 0, packets of higher priority can pass packets of lower priority. Response packets must have a physical priority higher than requests in order to avoid deadlock.
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Also, using an open modular data center and compute platform, a heterogeneous HPC system has showcased the low latency attribute of RapidIO to enable real-time analytics. In March 2015 a top-of-rack switch was announced to drive RapidIO into mainstream data center applications.
451:
system. This flexibility has driven the widespread use of RapidIO in wireless infrastructure equipment where there is a need to combine heterogeneous, DSP, FPGA and communication processors together in a tightly coupled system with low latency and high reliability.
325:
The RapidIO specification revision 1.2, released in June 2002, defined a serial interconnection based on the XAUI physical layer. Devices based on this specification achieved significant commercial success within wireless baseband, imaging and military computing.
673:
The RapidIO transport layer enables hardware virtualization (for example, a RapidIO endpoint can support multiple device IDs). Portions of the destination ID of each packet can be used to identify specific pieces of virtual hardware within the endpoint.
314:) as a replacement for Mercury's RACEway proprietary bus and Freescale's PowerPC bus. The RapidIO Trade Association was formed in February 2000, and included telecommunications and storage OEMs as well as FPGA, processor, and switch companies.
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RapidIO control symbols can be sent at any time, including within a packet. This gives RapidIO the lowest possible in-band control path latency, enabling the protocol to achieve high throughput with smaller buffers than other protocols.
393:
The RapidIO specification revision 3.1, was released in October 2014. It was developed through a collaboration between the RapidIO Trade Association and NGSIS. Revision 3.1 has the following changes compared to the 3.0 specification:
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The logical I/O layer defines packet formats for read, write, write-with-response, and various atomic transactions. Examples of atomic transactions are set, clear, increment, decrement, swap, test-and-swap, and compare-and-swap.
398:
MECS Time Synchronization protocol for smaller embedded systems. MECS Time Synchronization supports redundant time sources. This protocol is lower cost than the Timestamp Synchronization Protocol introduced in revision
638:
transmitting new packets and sends a Link Request/Port Status control symbol. The Link Response control symbol indicates the ackID that should be used for the next packet transmitted. Packet transmission then resumes.
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allow implementers to remove lanes on boards and in silicon, saving size, weight, and power. Structurally asymmetric links also allow the use of alternative lanes in the case of a hardware failure on a multi-lane port.
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exchange packets on a link, packets can be discarded to avoid congestion and enable diagnosis and recovery activities. In-band (port-write packet) and out-of-band (interrupt) notification mechanisms are defined.
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The RapidIO specification does not discuss the subjects of form factors and connectors, leaving this to specific application-focussed communities. RapidIO is supported by the following form factors:
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protocols, such as InfiniBand, Fibre Channel, and 10G Ethernet. As a result, the group decided that RapidIO offered the best overall interconnect for the needs of next-generation spacecraft.
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The IDLE sequence is used during link initialization for signal quality optimization. It is also transmitted when the link does not have any control symbols or packets to send.
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responds with extended header flow control packets that use XON/XOFF, rate, or credit based protocols to control how quickly and how much work the client sends to the server.
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The RapidIO specification revision 2.0 (6xN Gen2), was released in March 2008. This added more port widths (2Ć, 8Ć, and 16Ć) and increased the maximum lane speed to 6.25
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originated. When an endpoint receives a RapidIO request packet that requires a response, the response packet is composed by swapping the srcID and destID of the request.
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The RapidIO specification revision 1.1 (3xN Gen1), released in March 2001, defined a wide, parallel bus. This specification did not achieve extensive commercial adoption.
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Based on industry-standard Ethernet 10GBASE-KR electrical specifications for short (20 cm + connector) and long (1 m + 2 connector) reach applications
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The Globally Shared Memory specification defines packet formats and protocols for operating a cache coherent shared memory system over a RapidIO network.
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The RapidIO logical layer is composed of several specifications, each providing packet formats and protocols for different transaction semantics.
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is a competing technology for more complex backplane (VPX) and backbone applications for space (launchers and human-rated integrated avionics).
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The RapidIO specification revision 4.0 (25xN Gen4) was released in June 2016. It had the following changes compared to the 3.x specifications:
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The RapidIO roadmap aligns with Ethernet PHY development. RapidIO specifications for 50 GBd and higher links are under investigation.
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Interfaces are listed by their speed in the (roughly) ascending order, so the interface at the end of each section should be the fastest.
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1232:"Next Generation Space Interconnect Standard (NGSIS): A Modular Open Standards Approach for High Performance Interconnects for Space"
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1177:"Prodrive Technologies announces its Datacenter - HPC system (DCCP-280) with RapidIO and 10 Gigabit Ethernet - Prodrive Technologies"
51:
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Every RapidIO processing element transmits and receives three kinds of information: Packets, control symbols, and an idle sequence.
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1195:"IDT, Orange Silicon Valley, NVIDIA Accelerate Computing Breakthrough With RapidIO-based Clusters Ideal for Gaming, Analytics"
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received or a timeout occurs. Flow Control packets can also be used as a generic mechanism for managing system resources.
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The RapidIO electrical specifications are based on industry-standard Ethernet and Optical Interconnect Forum standards:
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Support for 32-bit device IDs, increasing maximum system size and enabling innovative hardware virtualization support
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Space device profiles for endpoints and switches, which define what it means to be a space-compliant RapidIO device.
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The RapidIO specification revision 3.0 (10xN Gen3) released in October 2013. The following changes were made:
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The RapidIO transport layer supports any network topology, from simple trees and meshes to n-dimensional
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Directly leverages the Ethernet 10GBASE-KR DME training scheme for long-reach signal quality optimization
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used for flow control (Retry, Buffer Status, Virtual Output Queue Backpressure) and for error recovery.
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Support 25 Gbaud lane rate and physical layer specification, with associated programming model changes
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802.3-ap (long reach) and 802.3-ba (short reach) for lane speeds of 10.3125 GBd (9.85 Gbit/s)
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1213:"Prodrive Technologies Launches PRSB-760G2 for large RapidIO networks - Prodrive Technologies"
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Physical: Electrical specifications, PCS/PMA, link-level protocol for reliable packet exchange
294:, RapidIO can be used as a chip-to-chip, board-to-board, and chassis-to-chassis interconnect.
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Increased maximum packet size to 284 bytes in anticipation of Cache Coherency specification
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PCIe assumption of a "root complex" creates fault tolerance and system management issues.
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Dynamic asymmetric links to save power (for example, 4Ć in one direction, 1Ć in the other)
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Allow IDLE3 to be used with any Baud Rate Class, with specified IDLE sequence negotiation
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Support āError Free Transmissionā for high throughput isochronous information transfer
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redundant hosts, so system initialization need not have a single point of failure.
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With one exception a packet's CRC value(s) acts as an end-to-end integrity check.
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semantics. Based on industry-standard electrical specifications such as those for
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Revised routing table programming model simplifies network management software
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RapidIO is expanding into supercomputing, server, and storage applications.
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The RapidIO interconnect is used extensively in the following applications:
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1141:"Reader Forum: Cloud radio access and small cell networks based on RapidIO"
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programming model for the routing table, which simplifies system control.
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Extended error log to capture a series of errors for diagnostic purposes
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for lane speeds of 1.25, 2.5, and 3.125 GBd (1, 2, and 2.5 Gbit/s)
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The RapidIO specification revision 2.1 was released in September 2009.
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The RapidIO specification revision 3.2 was released in February 2016.
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System enumeration is supported in Linux by the RapidIO subsystem.
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6+ Gbit/s for lane speeds of 5.0 and 6.25 GBd (4 and 5 Gbit/s)
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Identifier, enabling thousands of unique flows between endpoints.
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The RapidIO PCS/PMA layer supports two forms of encoding/framing:
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The RapidIO specification revision 4.1 was released in July 2017.
329:
The RapidIO specification revision 1.3 was released in June 2005.
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Processor-agnostic RapidIO support is found in the Linux kernel.
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The RapidIO specification revision 2.2 was released in May 2011.
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RapidIO - the unified fabric for Performance Critical Computing
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670:, and more esoteric architectures such as entangled networks.
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The RapidIO protocol is defined in a 3-layered specification:
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SpaceFibre is a competing technology for space applications.
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A device that can originate and/or terminate RapidIO packets.
1318:
961:. Integrated Device Technology Inc. 6 June 2011. p. 4
817:, as well as radar, acoustic and image processing systems
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Addition of a time synchronization capability similar to
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Yes, Chip-Chip, Board-Board (Backplane), Chassis-Chassis
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Logical: Logical I/O, messaging, global shared memory (
39:
1263:. RapidIO Trade Association. 10 June 2012. p. 4
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Transport: Routing, multicast, and programming model
50:, and by adding encyclopedic content written from a
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768:Advanced Telecommunications Computing Architecture
355:Defines a 64b/67b encoding scheme (similar to the
286:technology. It supports messaging, read/write and
952:"Integrated Device Technology 2011 Annual Report"
405:test facilities and standard register interface.
302:The RapidIO protocol was originally designed by
1712:Coherent Accelerator Processor Interface (CAPI)
853:Another alternative interconnect technology is
1375:
1040:. RapidIO Trade Association. 10 November 2013
1014:. RapidIO Trade Association. 23 February 2005
834:Industrial control and data path applications
8:
1069:. RapidIO Trade Association. 13 October 2014
514:A device which has at least one RapidIO port
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900:Fuller, Sam (27 December 2004). "Preface".
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1237:. Reinventing Space Conference. p. 5
932:. RapidIO Trade Association. 26 June 2002
902:RapidIO: The Embedded System Interconnect
125:Learn how and when to remove this message
70:Learn how and when to remove this message
1159:"PayPal Finds Order from Chaos with HPC"
520:A device that can route RapidIO packets.
892:
190:Sizes of 256, 65,536, and 4,294,967,296
179:Port widths of 1, 2, 4, 8, and 16 lanes
1121:. RapidIO Trade Association. July 2017
1095:. RapidIO Trade Association. June 2016
477:level hardware standards effort under
389:Packet exchange protocol optimizations
380:, but much less expensive to implement
139:
31:contains content that is written like
7:
435:Support 16 physical layer priorities
1230:Patrick Collier (14 October 2013).
279:architecture is a high-performance
1201:(Press release). 18 November 2014.
137:High-speed interconnect technology
97:tone or style may not reflect the
14:
596:64b/67b, similar to that used by
225:: added 12.5 and 25.3125 Gigabaud
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2112:
982:"RapidIO Reaches for the Clouds"
980:Jag Bolaria (October 15, 2013).
107:guide to writing better articles
86:
20:
1115:"RapidIO Standard Revision 4.1"
1089:"RapidIO Standard Revision 4.0"
1060:"RapidIO Standard Revision 3.1"
1034:"RapidIO Standard Revision 3.0"
1008:"RapidIO Standard Revision 2.0"
926:"RapidIO Standard Revision 1.2"
547:System specifications include:
543:), flow control, data streaming
593:for lane speeds up to 6.25 GBd
184:
1:
1707:Intel Ultra Path Interconnect
1288:. STAR-Dundee. Archived from
904:. John Wiley & Sons Ltd.
600:for lane speeds over 6.25 GBd
367:interconnects and to improve
1685:Intel QuickPath Interconnect
1675:Direct Media Interface (DMI)
1334:(current ed.), RapidIO
213:: added 5 and 6.25 Gigabaud
198:Per lane (each direction):
163:; 24 years ago
2178:
1670:Compute Express Link (CXL)
502:One end of a RapidIO link.
359:standard) to support both
2106:
1907:IEEE-1284 (parallel port)
1822:logical device interface)
1217:prodrive-technologies.com
1181:prodrive-technologies.com
554:Error Management/Hot Swap
145:
304:Mercury Computer Systems
219:: added 10.3125 Gigabaud
864:Time Triggered Ethernet
813:Aerospace and Military
773:Advanced Mezzanine Card
446:Wireless infrastructure
101:used on Knowledge (XXG)
1469:List of bus bandwidths
815:single-board computers
810:Wireless base stations
105:See Knowledge (XXG)'s
1283:"SpaceFibre Overview"
734:System initialization
551:System Initialization
284:electrical connection
242:Hotplugging interface
52:neutral point of view
1912:IEEE-1394 (FireWire)
1650:PCI Extended (PCI-X)
1165:. 24 September 2014.
666:, multi-dimensional
369:bandwidth efficiency
2162:Local area networks
2157:Computer networking
1753:Parallel ATA (PATA)
1145:www.rcrwireless.com
986:www.linleygroup.com
842:Competing protocols
204:: 1.25, 2.5, 3.125
142:
44:promotional content
2152:Computer standards
1660:PCI Express (PCIe)
1295:on 22 October 2014
1183:. 30 January 2014.
1147:. 3 December 2012.
988:. The Linley Group
511:Processing Element
250:External interface
46:and inappropriate
2124:
2123:
2110:
1837:Apple Desktop Bus
1814:PCI Express (via
1773:Serial ATA (SATA)
1459:Network on a chip
1257:"RapidIO Roadmap"
525:Protocol overview
336:/ 5 Gbit/s.
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99:encyclopedic tone
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1530:Europe Card Bus
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1219:. 2 March 2015.
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281:packet-switched
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2142:Open standards
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2137:Computer buses
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2011:Intel HD Audio
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2001:ADAT Lightpipe
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1451:
1449:Bus contention
1446:
1441:
1436:
1431:
1426:
1424:Front-side bus
1421:
1415:
1413:
1409:
1408:
1405:computer buses
1389:
1387:
1386:
1379:
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1364:
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1331:Specifications
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1312:External links
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826:Supercomputing
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115:September 2022
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60:September 2019
48:external links
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2073:Multidrop bus
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1852:Commodore bus
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1800:Fibre Channel
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1464:Plug and play
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1454:Bus mastering
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1429:Back-side bus
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911:0-470-09291-2
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694:
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685:
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678:Logical layer
677:
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660:
656:
649:
647:
642:IDLE sequence
641:
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176:Width in bits
174:
160:
156:
149:
144:
129:
126:
118:
108:
102:
100:
93:
84:
83:
74:
71:
63:
53:
49:
45:
41:
35:
34:
29:This article
27:
18:
17:
2147:Serial buses
1679:
1605:TURBOchannel
1395:
1354:, Open cores
1350:
1330:
1319:
1297:. Retrieved
1290:the original
1277:
1265:. Retrieved
1260:
1251:
1239:. Retrieved
1225:
1216:
1207:
1198:
1189:
1180:
1171:
1162:
1153:
1144:
1135:
1123:. Retrieved
1118:
1109:
1097:. Retrieved
1092:
1083:
1071:. Retrieved
1066:
1054:
1042:. Retrieved
1037:
1028:
1016:. Retrieved
1011:
1002:
990:. Retrieved
985:
975:
963:. Retrieved
958:
946:
934:. Retrieved
929:
920:
901:
895:
862:
859:
852:
845:
837:
805:
802:Applications
797:
762:
759:Form factors
753:
745:
741:
737:
728:
724:
716:
707:
704:Flow control
698:
689:
681:
672:
661:
657:
653:
645:
636:
632:
628:
619:
615:
611:
603:
585:
562:
546:
528:
499:Link Partner
489:
475:
471:
462:
458:
455:Data centers
449:
441:
421:
418:
392:
344:
341:
338:
331:
328:
324:
321:
301:
276:
274:
222:
216:
210:
201:
158:Year created
121:
112:
96:
66:
57:
42:by removing
38:Please help
30:
2078:CoreConnect
2057:ExpressCard
1985:Thunderbolt
1975:Camera Link
1758:Bus and Tag
1444:Address bus
1439:Control bus
1434:Daisy chain
1163:hpcwire.com
959:www.idt.com
881:PCI Express
847:PCI Express
686:Logical I/O
494:Terminology
486:PHY roadmap
2131:Categories
1931:ACCESS.bus
1830:Peripheral
1630:InfiniBand
1625:HP GSC bus
1419:System bus
1299:21 October
1073:18 October
887:References
664:hypercubes
598:Interlaken
580:10GBASE-KR
357:Interlaken
187:of devices
40:improve it
1892:Lightning
1842:Atari SIO
1717:SpaceWire
1550:Zorro III
1490:S-100 bus
1485:SS-50 bus
1478:Standards
1398:standards
1391:Technical
1267:9 October
1241:9 October
1125:11 August
1099:15 August
1044:9 October
1018:9 October
992:9 October
965:9 October
936:9 October
695:Messaging
468:Aerospace
378:IEEE 1588
312:Freescale
2118:Category
2093:Wishbone
2066:Embedded
2045:Portable
1965:Profibus
1897:DMX512-A
1783:Parallel
1635:Ethernet
1545:Zorro II
1495:Multibus
1396:de facto
1119:vita.com
870:See also
855:Ethernet
794:Software
505:Endpoint
318:Releases
308:Motorola
292:Ethernet
265:.rapidio
206:Gigabaud
2098:SLIMbus
2052:PC Card
2036:TOSLINK
1726:Storage
1680:RapidIO
1560:FASTBUS
1515:STD Bus
1412:General
1351:RapidIO
1340:RapidIO
1320:RapidIO
823:Storage
783:OpenVPX
713:CC-NUMA
668:toroids
608:Packets
574:OIF CEI
541:CC-NUMA
365:optical
298:History
277:RapidIO
258:Website
166: (
141:RapidIO
2031:S/PDIF
1922:1-Wire
1887:RS-485
1882:RS-423
1877:RS-422
1872:RS-232
1733:ST-506
1690:NVLink
1540:STEbus
1500:Unibus
1344:GitHub
1323:(home)
908:
591:8b/10b
517:Switch
361:copper
236:Serial
2026:McASP
1994:Audio
1939:SMBus
1935:PMBus
1917:UNI/O
1857:HP-IL
1810:SATAe
1795:ESCON
1768:HIPPI
1600:NuBus
1555:CAMAC
1525:Q-Bus
1520:SMBus
1505:VAXBI
1402:wired
1293:(PDF)
1286:(PDF)
1235:(PDF)
1063:(PDF)
955:(PDF)
820:Video
232:Style
195:Speed
2083:AMBA
2021:MADI
2006:AES3
1867:MIDI
1820:NVMe
1816:AHCI
1778:SCSI
1763:DSSI
1738:ESDI
1615:SBus
1575:EISA
1510:MBus
1400:for
1393:and
1301:2014
1269:2014
1243:2014
1127:2019
1101:2016
1075:2014
1046:2014
1020:2014
994:2014
967:2014
938:2014
906:ISBN
568:XAUI
479:VITA
403:PRBS
363:and
306:and
275:The
267:.org
168:2000
161:2000
2087:AXI
2016:IĀ²S
1970:USB
1955:DĀ²B
1950:SPI
1945:I3C
1927:IĀ²C
1862:HIL
1847:DCB
1818:or
1805:SSA
1788:SAS
1748:SMD
1743:IPI
1665:AGP
1655:PXI
1645:PCI
1640:UPA
1620:VLB
1610:MCA
1595:VPX
1590:VXS
1585:VXI
1580:VME
1565:LPC
1535:ISA
1342:on
788:VXS
778:XMC
399:3.0
334:GBd
263:www
245:Yes
223:4.x
217:3.x
211:2.x
202:1.x
185:No.
2133::
1937:,
1933:,
1259:.
1215:.
1197:.
1179:.
1161:.
1143:.
1117:.
1091:.
1065:.
1036:.
1010:.
984:.
957:.
928:.
2089:)
2085:(
1941:)
1929:(
1383:e
1376:t
1369:v
1356:.
1336:.
1325:.
1303:.
1271:.
1245:.
1129:.
1103:.
1077:.
1048:.
1022:.
996:.
969:.
940:.
914:.
310:(
170:)
128:)
122:(
117:)
113:(
103:.
73:)
67:(
62:)
58:(
54:.
36:.
Text is available under the Creative Commons Attribution-ShareAlike License. Additional terms may apply.
