642:(Transfer A to B) the zero page then moves to the new location. A significant use of this feature is to allow small routines that can fit within the 256 bytes of a page to use zero-page addressing (now known as base page addressing) which makes the code smaller because addresses no longer have a second byte, which also makes the code run faster because the second byte does not have to be fetched from memory.
833:
discarded and re-read to feed it into the decoder. This wastes a cycle. Although this led to a number of instructions being slower than they could have been, this "feature" was retained in the 65C02, although whether this was in order to retain its pipeline's simplicity or its cycle timing is not explained in available sources.
878:
755:, thereby making the code more obvious, removing two bytes of instructions, and removing the need for the lost cycles fetching and running the branch. However, as it still uses relative addressing, the relative address has to be calculated from the label by the programmer or assembler when converting to machine code.
836:
Maintaining cycle compatibility was not a requirement for the 65CE02, and new fabrication processes made the extra circuitry in the pipeline a non-issue, so the pipeline was re-arranged to correctly handle one-byte instructions in a single cycle. These improvements allow the 65CE02 to execute code up
731:
In addition, the CE added 16-bit addressing, or "word relative", to all of the existing branch instructions. Previously, the branches could only move backward 128 locations or forward 127, based on a signed 8-bit value, the "relative address". In the 65CE02, these could be -32768 or +32767 locations,
661:
instructions, the stack pointer becomes a true 16-bit value. The value in SPH is added to the value in the original SP, now known as SPL for Stack
Pointer Low, to produce a 16-bit pointer to the bottom of the stack. This allows the stack to grow much larger than the original 256 bytes, which was too
647:
The 65CE02 also extends the stack from the original 256-bytes of page one to, in theory, the entire address space. It does this by adding another 8-bit register, SPH, for Stack
Pointer High. Normally this works like B, offsetting the base address of the stack from page one to any selected page. It
667:
This means there are two types of stacks, a 256-byte one that can be anywhere, or a 16-bit one spanning memory. While the latter is more flexible, it does mean that accesses into the stack have to construct a 16-bit address from the two registers, taking an extra cycle, and thus slowing overall
844:
is added to a base address, and then applies the instruction to the resulting address. In the original 6502, if the addition of the two values crossed a page boundary, every 256 locations, an extra cycle was needed to produce the final address value. The 65CE02 removed this limitation, thereby
832:
If the instruction required only one byte, the processor still read the following byte as it decoded the first. In this case the next byte was the following instruction, but it had no way to feed that back into the first stage of the pipeline to decode it. The fetched instruction was instead
828:
system; the next byte from memory was fetched while the operation was being decoded, meaning the next byte was fetched no matter what. For most instructions, this byte would be part (or whole) of an operand, which could then be immediately fed into the now-decoded instruction.
681:, works just like it does in the 65C02 where the same instruction means store-zero-to-memory. This allows unmodified 65C02 code to run on the 65CE02. A number of other instructions are added or modified to allow access to the Z register. Among these are the
637:
The 65CE02 adds an 8-bit B register, for Base Page, that offsets the zero page to any location in memory. B is set to zero on power-up or reset, so the 65CE02 initially works exactly like the 6502. If a value is placed into the B register using
806:
instruction was added for future expansion. Although the data-sheet is not clear on its ultimate purpose, it appears to be a placeholder intended to allow instructions to be passed to co-processor units, like a
172:, Z, along with the addition and modification of a number of instructions to use this register. The zero-page, the first 256 bytes of memory that were used as pseudo-registers, could now be moved to any page in
632:
The 65CE02 is a further improved version of the 65C02 which expands the memory model to make it more suitable for a system with large amounts of main memory. To do this, it adds the following new features:
611:
By the 1980s, these assumptions were no longer valid, many machines based on these processors now shipped with the maximum 64 kB that the 6502 could address, using the far less expensive and denser
736:
to the 16-bit target and then branch over those three bytes when you didn't want to do it. For instance, if one wanted to branch to address $ 1234 if the accumulator is zero, one would do a
840:
A further improvement addresses an issue involving addressing instructions that add values to produce a final address. Examples include "indexed indirect" where the value in one of the
157:
technology, making the chip smaller (and thus less expensive) as well as using much less power. In addition to changes made in the 65C02, the 65CE02 also included improvements to the
596:. For both of these reasons, the ability to handle "large" amounts of memory was not required, and many processors had operating modes that worked with small portions of a larger
648:
otherwise continues to work as before, having a maximum size of one page, 256 bytes. Like B, on startup or reset, SPH is set to 01 so that it works exactly like the 65C02.
797:
off anything the routine added while it ran. The system also added a new addressing mode that used a base address on the stack as the basis for indirect addressing.
161:
to allow one-byte instructions to complete in 1 cycle, rather than the 6502's (and most variants) minimum of 2 cycles. It also removed 1 cycle delays when crossing
180:
was widened from 8 to 16-bits using a similar page register, SPH (stack pointer high), allowing the stack to be moved out of page one and to grow to larger sizes.
616:. The speed advantages of the zero page addressing mode remained, but now existing within a memory space that was dramatically larger. Likewise, the single-page
1393:
714:
that used branch-style 8-bit relative address instead of an absolute 16-bit address. For unknown reasons, the 65CE02 changed the mnemonic to
1336:
1181:
497:
793:(ReTurn from Subroutine) that returns to an address offset into the stack instead of at the top, avoiding the need to explicitly
760:
Another addition to the system were a number of "word" instructions that carried out operations on 16-bit data. This included
1398:
1388:
1311:
940:
132:
60:
94:
1111:
862:
545:
6502 that used 10 to 20 times less power, but it also included a number of new instructions to help improve the
945:
732:
by following the branch with a 16-bit value. Previously to perform a "long branch" one normally had to use a
554:
76:
897:
808:
522:
162:
158:
153:
Like the 65C02, the 65CE02 was built on a 2 µm CMOS process instead of the original 6502's 8 µm
1249:
1174:
585:
518:
147:
1139:
1031:
777:
to perform an arithmetic (signed) right shift (the 6502 only had logical, or unsigned right shift), a
866:
825:
463:
116:
1331:
1287:
1232:
1226:
1221:
1216:
1211:
1205:
1128:
782:
621:
136:
1144:
1018:"US patent 5088035: System for accelerating execution of program instructions by a microprocessor"
1149:
890:
581:
521:(WDC) to provide 6502-based design services. Around 1981, the main licensees of the 6502 design,
604:, or "zero page", to provide faster access, and the second page, "page one", to hold a 256-byte
886:
677:, Z. This is set to zero on startup or reset, meaning that its store-Z-to-memory instruction,
577:
1167:
184:
654:
600:
in order to offer higher performance. Such was the case in the 6502, which used the first
566:
1154:
722:
instruction, Branch to SubRoutine, which uses the same relative addressing mode with the
995:
1295:
1196:
1069:
950:
912:
841:
674:
593:
510:
468:
177:
169:
165:
boundaries. These changes improved performance as much as 25% at the same clock speed.
1382:
597:
573:
450:
1367:
908:
901:
546:
191:
17:
1097:
1362:
1052:
924:
668:
performance. Using the smaller stack, where possible, offers better performance.
613:
601:
514:
195:
173:
900:
to expand the address space to 20 bit (1 megabyte). It is housed in an 84-pin
1346:
1341:
1322:
1283:
1272:
1267:
1262:
1017:
858:
617:
605:
589:
576:
existed, when microprocessors were used as the basis for simpler systems like
542:
478:
458:
154:
79:
1257:
534:
530:
473:
445:
143:
824:
still took two cycles to complete. This allowed for simplifications in the
569:. The 65C02 also fixed a number of minor bugs in the original 6502 design.
1083:
624:
that made prodigious use of stack space could not easily run on the 6502.
588:
systems. This was also an era when memory devices were generally based on
893:
820:
A major oddity of the original 6502 was that one-byte instructions like
496:
857:
technology, allowing for lower power operation compared to previous
768:
to perform an
Arithmetic Shift (left) Word or ROtate (left) Word.
1159:
928:
877:
876:
495:
199:
854:
538:
140:
1163:
526:
1032:"Commodore Semiconductor Group CSG65CE02 Technical Reference"
1155:
Profile of Victor F. Andrade (principal 65CE02 LSI engineer)
1140:
751:
zero. In the 65CE02 this can be reduced to something like
845:
improving the performance of these commonly used modes.
865:
versions of the 65xx family. It is housed in a 40-pin
533:, began a redesign effort with Mensch that led to the
1355:
1320:
1304:
1282:
1248:
1195:
803:
549:in certain applications. New instructions included
108:
103:
93:
88:
74:
69:
53:
45:
37:
32:
764:to increment and decrement a value in memory, and
689:to transfer the value to or from the accumulator,
620:was now a pittance within the overall memory, and
572:The original 6502 was designed in the era before
1129:List of books about 65xx microprocessor families
202:computer. It appears to have seen no other use.
1145:65CE02 Microprocessor (Preliminary) (Nov. 1988)
701:to compare the value in Z to a value in memory.
168:Other changes included the addition of a third
889:(SiP) variant of the 65CE02 that includes two
718:(Branch Unconditionally). They also added the
1175:
1112:"Big Book of Amiga Hardware: Commodore A2232"
8:
1070:"Commodore Knowledge Base: The Commodore 65"
565:which was a jump with a branch-style 1-byte
27:
1012:
1010:
1008:
923:The 65CE02 was used in the Commodore A2232
773:More minor changes include the addition of
740:, meaning you want to skip over the 3-byte
513:team that designed the 6502 had broken up.
131:is an 8/16-bit microprocessor developed by
1182:
1168:
1160:
1064:
1062:
990:
988:
986:
561:to write a zero to a memory location, and
194:. The 65CE02 was later used for the A2232
984:
982:
980:
978:
976:
974:
972:
970:
968:
966:
837:to 25% faster than previous 65xx models.
710:, Branch Always, which was essentially a
653:When the new "stack extend" bit in the
962:
592:, which was very expensive and had low
996:"MOS 65CE02 Microprocessor Data Sheet"
869:that is pin compatible with the 6502.
209:
190:that was developed for the unreleased
26:
7:
907:The 4510 was used in the unreleased
517:had moved to Arizona and set up the
176:using the B(ase page) register. The
1229:(and 6510T, 6512, 6513, 6514, 6515)
1098:"Amiga Stuff: 65CE02 Hardware Info"
1084:"Amiga Hardware Database: CDTV II"
911:home computer and the unreleased
25:
1053:"Amiga Stuff: 4510 Hardware Info"
853:It is fabricated using 2 µm
785:negation on the accumulator, and
697:for increment and decrement, and
693:to push and pull Z to the stack,
183:The 65CE02 was the basis for the
509:By the late 1970s, the original
685:to load the value from memory,
662:small for high-level languages.
553:to increment and decrement the
541:implementation of the original
135:in 1988. It is a member of the
89:Architecture and classification
1394:MOS Technology microprocessors
1:
1312:Interrupts in 65xx processors
1150:65CE02 package and die images
941:Interrupts in 65xx processors
781:instruction which performs a
133:Commodore Semiconductor Group
61:Commodore Semiconductor Group
1208:(and 6501, 6503, 6504, 6505)
802:Finally, the new four-byte
738:CMP #$ 00/BNE +3/JMP $ 1234
673:The 65CE02 also adds a new
139:family, developed from the
1415:
1126:
434:
419:
412:
331:
310:
1034:. zimmers.net. 2009-08-18
896:controllers and a custom
441:
401:
398:
383:
380:
369:
366:
355:
352:
341:
338:
320:
317:
84:2 MHz to 10 MHz
946:List of 6502 assemblers
915:cost-reduced revision.
104:Physical specifications
1235:(and 7501, 8500, 8501)
882:
809:memory management unit
747:if the accumulator is
657:is set, using the new
523:Rockwell Semiconductor
501:
1399:8-bit microprocessors
1250:Western Design Center
880:
816:Pipeline improvements
726:, Jump to SubRoutine.
586:industrial controller
519:Western Design Center
499:
148:Western Design Center
1389:65xx microprocessors
753:CMP #$ 00/BEQ $ 0123
622:high-level languages
537:. This was mainly a
214:CSG 65CE02 registers
95:Instruction set
584:and many different
582:desktop calculators
137:MOS Technology 6502
54:Common manufacturer
33:General information
29:
18:MOS Technology 4510
883:
502:
500:CSG 65CE02 pin-out
159:processor pipeline
1376:
1375:
887:system in package
789:, a variation on
494:
493:
490:
489:
125:
124:
16:(Redirected from
1406:
1184:
1177:
1170:
1161:
1116:
1115:
1108:
1102:
1101:
1094:
1088:
1087:
1080:
1074:
1073:
1066:
1057:
1056:
1049:
1043:
1042:
1040:
1039:
1028:
1022:
1021:
1014:
1003:
1002:
1000:
992:
849:Physical details
823:
805:
796:
792:
788:
783:two's complement
780:
776:
767:
763:
754:
746:
739:
735:
725:
721:
717:
713:
709:
706:The 65C02 added
700:
696:
692:
688:
684:
680:
660:
641:
567:relative address
564:
560:
552:
221:
220:
210:
185:system on a chip
146:released by the
30:
21:
1414:
1413:
1409:
1408:
1407:
1405:
1404:
1403:
1379:
1378:
1377:
1372:
1351:
1316:
1300:
1278:
1244:
1191:
1190:65xx-based CPUs
1188:
1136:
1131:
1125:
1123:Further reading
1120:
1119:
1110:
1109:
1105:
1096:
1095:
1091:
1082:
1081:
1077:
1068:
1067:
1060:
1051:
1050:
1046:
1037:
1035:
1030:
1029:
1025:
1016:
1015:
1006:
998:
994:
993:
964:
959:
937:
921:
875:
851:
842:index registers
821:
818:
794:
790:
786:
778:
774:
765:
761:
752:
741:
737:
733:
723:
719:
715:
711:
707:
698:
694:
690:
686:
682:
678:
658:
655:status register
639:
630:
578:smart terminals
562:
558:
550:
507:
486:rocessor flags
436:Status register
414:Program counter
333:Index registers
301:
296:
291:
286:
281:
276:
271:
266:
261:
256:
251:
246:
241:
236:
231:
226:
208:
121:
65:
23:
22:
15:
12:
11:
5:
1412:
1410:
1402:
1401:
1396:
1391:
1381:
1380:
1374:
1373:
1371:
1370:
1365:
1359:
1357:
1353:
1352:
1350:
1349:
1344:
1339:
1334:
1332:Hudson HuC6280
1328:
1326:
1318:
1317:
1315:
1314:
1308:
1306:
1302:
1301:
1299:
1298:
1292:
1290:
1280:
1279:
1277:
1276:
1270:
1265:
1260:
1254:
1252:
1246:
1245:
1243:
1242:
1236:
1230:
1224:
1219:
1214:
1209:
1202:
1200:
1197:MOS Technology
1193:
1192:
1189:
1187:
1186:
1179:
1172:
1164:
1158:
1157:
1152:
1147:
1142:
1135:
1134:External links
1132:
1124:
1121:
1118:
1117:
1103:
1089:
1075:
1058:
1044:
1023:
1004:
961:
960:
958:
955:
954:
953:
951:Megahertz myth
948:
943:
936:
933:
920:
917:
913:Commodore CDTV
885:The 4510 is a
874:
871:
850:
847:
817:
814:
813:
812:
799:
798:
770:
769:
757:
756:
728:
727:
703:
702:
675:index register
670:
669:
664:
663:
650:
649:
644:
643:
629:
626:
594:memory density
574:microcomputers
511:MOS Technology
506:
503:
492:
491:
488:
487:
481:
476:
471:
466:
461:
456:
453:
448:
443:
439:
438:
432:
431:
421:
417:
416:
410:
409:
403:
400:
396:
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385:
382:
378:
377:
371:
368:
364:
363:
357:
354:
350:
349:
343:
340:
336:
335:
329:
328:
322:
319:
315:
314:
312:Main registers
308:
307:
305:(bit position)
302:
299:
297:
294:
292:
289:
287:
284:
282:
279:
277:
274:
272:
269:
267:
264:
262:
259:
257:
254:
252:
249:
247:
244:
242:
239:
237:
234:
232:
229:
227:
224:
217:
216:
207:
204:
178:stack register
170:index register
123:
122:
120:
119:
112:
110:
106:
105:
101:
100:
97:
91:
90:
86:
85:
82:
72:
71:
67:
66:
64:
63:
57:
55:
51:
50:
47:
43:
42:
39:
35:
34:
24:
14:
13:
10:
9:
6:
4:
3:
2:
1411:
1400:
1397:
1395:
1392:
1390:
1387:
1386:
1384:
1369:
1366:
1364:
1361:
1360:
1358:
1354:
1348:
1345:
1343:
1340:
1338:
1337:Nintendo SA-1
1335:
1333:
1330:
1329:
1327:
1324:
1319:
1313:
1310:
1309:
1307:
1303:
1297:
1294:
1293:
1291:
1289:
1285:
1281:
1274:
1271:
1269:
1266:
1264:
1261:
1259:
1256:
1255:
1253:
1251:
1247:
1240:
1237:
1234:
1231:
1228:
1225:
1223:
1220:
1218:
1215:
1213:
1210:
1207:
1204:
1203:
1201:
1198:
1194:
1185:
1180:
1178:
1173:
1171:
1166:
1165:
1162:
1156:
1153:
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1148:
1146:
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1141:
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1133:
1130:
1122:
1113:
1107:
1104:
1099:
1093:
1090:
1085:
1079:
1076:
1071:
1065:
1063:
1059:
1054:
1048:
1045:
1033:
1027:
1024:
1019:
1013:
1011:
1009:
1005:
997:
991:
989:
987:
985:
983:
981:
979:
977:
975:
973:
971:
969:
967:
963:
956:
952:
949:
947:
944:
942:
939:
938:
934:
932:
930:
927:card for the
926:
918:
916:
914:
910:
905:
903:
899:
895:
892:
888:
879:
872:
870:
868:
864:
860:
856:
848:
846:
843:
838:
834:
830:
827:
815:
810:
801:
800:
784:
772:
771:
759:
758:
750:
745:
730:
729:
705:
704:
676:
672:
671:
666:
665:
656:
652:
651:
646:
645:
636:
635:
634:
627:
625:
623:
619:
615:
609:
607:
603:
599:
598:address space
595:
591:
587:
583:
579:
575:
570:
568:
556:
548:
544:
540:
536:
532:
528:
524:
520:
516:
512:
504:
498:
485:
482:
480:
477:
475:
472:
470:
467:
465:
462:
460:
457:
454:
452:
449:
447:
444:
440:
437:
433:
429:
425:
422:
418:
415:
411:
407:
404:
397:
393:
389:
386:
379:
375:
372:
365:
361:
358:
351:
347:
344:
337:
334:
330:
326:
323:
316:
313:
309:
306:
303:
298:
293:
288:
283:
278:
273:
268:
263:
258:
253:
248:
243:
238:
233:
228:
223:
222:
219:
218:
215:
212:
211:
205:
203:
201:
198:card for the
197:
193:
189:
186:
181:
179:
175:
171:
166:
164:
160:
156:
151:
149:
145:
142:
138:
134:
130:
118:
114:
113:
111:
107:
102:
98:
96:
92:
87:
83:
81:
78:
73:
68:
62:
59:
58:
56:
52:
48:
44:
40:
36:
31:
19:
1368:Chuck Peddle
1305:Architecture
1275:(and 65C802)
1238:
1106:
1092:
1078:
1047:
1036:. Retrieved
1026:
922:
919:Applications
909:Commodore 65
906:
884:
852:
839:
835:
831:
819:
748:
743:
631:
628:New features
610:
571:
547:code density
508:
483:
435:
427:
426:rogram
423:
413:
405:
391:
387:
373:
359:
345:
332:
324:
311:
304:
213:
192:Commodore 65
187:
182:
167:
152:
128:
126:
46:Discontinued
1363:Bill Mensch
925:serial port
614:dynamic RAM
602:memory page
555:accumulator
515:Bill Mensch
327:ccumulator
206:Description
196:serial port
174:main memory
70:Performance
1383:Categories
1347:Ricoh 5A22
1342:Ricoh 2A03
1296:740 family
1284:Mitsubishi
1241:(and 4510)
1127:See also:
1038:2013-06-21
957:References
931:computer.
618:call stack
590:static RAM
505:Background
390:tack
129:CSG 65CE02
80:clock rate
28:CSG 65CE02
1356:Designers
535:WDC 65C02
531:Signetics
408:ase Page
150:in 1983.
144:WDC 65C02
1325:machines
935:See also
894:I/O port
891:6526 CIA
881:CSG 4510
873:CSG 4510
826:pipeline
188:CSG 4510
38:Launched
1288:Renesas
766:ASW/ROW
762:INW/DEW
695:INZ/DEZ
691:PHZ/PLZ
687:TZA/TAZ
659:CLE/SEE
551:INA/DEA
442:
430:ounter
402:
394:ointer
367:
353:
339:
318:
115:40-pin
109:Package
1273:65C816
1268:65C265
1263:65C134
1239:65CE02
376:index
362:index
348:index
1258:65C02
1199:, CSG
999:(PDF)
929:Amiga
779:NEG A
606:stack
200:Amiga
75:Max.
1323:game
1321:For
1233:8502
1227:6510
1222:6509
1217:6508
1212:6507
1206:6502
902:PLCC
863:HMOS
861:and
859:NMOS
855:CMOS
744:addr
742:JMP
543:NMOS
539:CMOS
529:and
384:SPL
381:SPH
163:page
155:NMOS
141:CMOS
127:The
99:6502
49:1988
41:1988
898:MMU
867:DIP
822:INX
804:AUG
795:POP
791:RTS
787:RTN
775:ASR
749:not
734:JMP
724:JSR
720:BSR
716:BRU
712:JMP
708:BRA
699:CPZ
683:LDZ
679:STZ
640:TAB
563:BRA
559:STZ
527:GTE
420:PC
117:DIP
77:CPU
1385::
1286:,
1061:^
1007:^
965:^
904:.
608:.
580:,
557:,
525:,
455:E
399:B
370:Z
356:Y
342:X
321:A
1183:e
1176:t
1169:v
1114:.
1100:.
1086:.
1072:.
1055:.
1041:.
1020:.
1001:.
811:.
484:P
479:C
474:Z
469:I
464:D
459:B
451:V
446:N
428:C
424:P
406:B
392:P
388:S
374:Z
360:Y
346:X
325:A
300:0
295:1
290:2
285:3
280:4
275:5
270:6
265:7
260:8
255:9
250:0
245:1
240:2
235:3
230:4
225:5
20:)
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