Knowledge (XXG)

Microarchitecture simulation

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highly reproducible, it also requires a very large storage space. On the other hand, an execution-driven simulation reads a program and simulates the execution of machine instructions on the fly. A program file is typically several magnitudes smaller than a trace file. However, the execution-driven simulation is much slower than the trace-driven simulation because it has to process each instruction one-by-one and update all statuses of the microarchitecture components involved. Thus, the selection of input types for simulation is a trade-off between space and time. In particular, a very detailed trace for a highly accurate simulation requires a very large storage space, whereas a very accurate execution-driven simulation takes a very long time to execute all instructions in the program.
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levels of cache memory incurs very little cost when comparing with the fabrication of a prototyping chip. The researchers can also play with several configurations of the cache hierarchy using different cache models in the simulator instead of having to fabricate a new chip every time they want to test something different.
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Microarchitecture simulators are deployed for a variety of purposes. It allows researchers to evaluate their ideas without the need to fabricate a real microprocessor chip, which is both expensive and time consuming. For instance, simulating a microprocessor with thousand of cores along with multiple
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A trace-driven simulation reads a fixed sequence of trace records from a file as an input. These trace records usually represent memory references, branch outcomes, or specific machine instructions, among others. While a trace-driven simulation is known to be comparatively fast and its results are
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only models the execution of a program on a microprocessor through the eyes of an instruction scheduler along with a coarse timing of instruction execution. Most computer science classes in computer architecture with hand-on experiences adopt the instruction set simulators as tools for teaching,
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Another usage of the microarchitecture simulator is in education. Given that a course in computer architecture teaches students many different microprocessor's features and its architectures, the microarchitecture simulator is ideal for modeling and experimenting with different features and
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Microarchitecture simulation can be classified into multiple categories according to input types and level of details. Specifically, the input can be a trace collected from an execution of program on a real microprocessor (so called trace-driven simulation) or a program itself (so called
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architectures over the course of a semester. For example, students may start with a microarchitecture simulator that models a simple microprocessor design at the beginning of a semester. As the semester progresses, additional features, such as
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Apart from input types, the level of details can also be used to classify the simulation. In particular, a piece of software that simulates a microprocessor executing a program on a cycle-by-cycle basis is known as
124:, can be modeled and added to the simulator as they are introduced in the classroom. Microarchitecture simulator provides the flexibility of reconfiguration and testing with minimal costs. 268:
Tullsen, D. M. (1996). Simulation and Modeling of a Simultaneous Multithreading Processor. In Proceedings of the 22nd Annual Computer Measurement Group Conference.
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Skadron, K. (1996). A Microprocessor Survey Course for Learning Advanced Computer Architecture. In Proceedings of the 2002 ACM SIGCSE Conference, 152-156.
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whereas the cycle-accurate simulators are deployed mostly for research projects due to both complexities and resource consumption.
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Austin, T., Larson, E., & Ernst, D. (2002). SimpleScalar: An Infrastructure for Computer System Modeling.
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Cmelik, R. F., & Keppel, D. (1994). Shade: A Fast Instruction-Set Simulator for Execution Profiling.
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Uhlig, R. A., & Mudge, T. N. (2004). Trace-Driven Memory Simulation: A Survey.
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Burger, D., & Austin, T. M. (1997). The Simplescalar Tool Set Version 2.0.
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For system-level simulation of computer hardware, please refer to the
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D. Burger and T. M. Austin. The SimpleScalar Tool Set, Version 2.0.
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education. It is a tool for modeling the design and behavior of a
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Computer Organization and Design: The Hardware/Software Interface
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SimpleScalar (execution-driven, cycle-accurate simulator)
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SMTSIM (execution-driven, cycle-accurate simulator)
255:Patterson, D. A., & Hennessy, J. L. (2011). 133:Shade (trace-driven, instruction set simulator) 142:(execution-driven, instruction set simulator) 8: 218:ACM SIGMETRICS Performance Evaluation Review 174: 7: 292:The SMTSIM Multithreading Simulator 14: 282:The Official SimpleScalar Website 164:(2007), derived from SimpleScalar 34:and its components, such as the 74:execution-driven simulation). 1: 22:is an important technique in 244:http://www.simplescalar.com 328: 196:Computer Architecture News 287:The Official SPIM Website 88:instruction set simulator 84:cycle-accurate simulator 231:IEEE Computer Magazine 118:out-of-order execution 106:instruction pipelining 63:full system simulation 307:Computer architecture 183:ACM Computing Surveys 24:computer architecture 114:reservation stations 312:Simulation software 259:, Morgan Kaufmann. 220:, 22(1), 128-137. 185:, 29(2), 128-170. 110:register renaming 48:branch predictors 18:Microarchitecture 319: 269: 266: 260: 253: 247: 240: 234: 227: 221: 214: 208: 205: 199: 192: 186: 179: 163: 28:computer science 327: 326: 322: 321: 320: 318: 317: 316: 297: 296: 278: 273: 272: 267: 263: 254: 250: 241: 237: 233:, 35(2), 59-67. 228: 224: 215: 211: 206: 202: 198:, 25(3), 13-25. 193: 189: 180: 176: 171: 157: 130: 97: 71: 52:re-order buffer 12: 11: 5: 325: 323: 315: 314: 309: 299: 298: 295: 294: 289: 284: 277: 276:External links 274: 271: 270: 261: 248: 235: 222: 209: 200: 187: 173: 172: 170: 167: 166: 165: 152: 146: 143: 137: 134: 129: 126: 96: 93: 70: 69:Classification 67: 32:microprocessor 13: 10: 9: 6: 4: 3: 2: 324: 313: 310: 308: 305: 304: 302: 293: 290: 288: 285: 283: 280: 279: 275: 265: 262: 258: 252: 249: 245: 239: 236: 232: 226: 223: 219: 213: 210: 204: 201: 197: 191: 188: 184: 178: 175: 168: 161: 156: 153: 150: 147: 144: 141: 138: 135: 132: 131: 127: 125: 123: 122:scoreboarding 119: 115: 111: 107: 101: 94: 92: 89: 85: 79: 75: 68: 66: 64: 59: 57: 53: 49: 45: 41: 37: 33: 29: 26:research and 25: 21: 19: 264: 256: 251: 238: 230: 225: 217: 212: 203: 195: 190: 182: 177: 102: 98: 80: 76: 72: 60: 44:control unit 40:cache memory 16: 15: 158: [ 56:trace cache 301:Categories 169:References 86:, whereas 20:simulation 155:GPGPU-Sim 149:Multi2Sim 128:Examples 246:, 1997. 151:(2007) 120:, and 95:Usages 54:, and 162:] 140:SPIM 36:ALU 303:: 160:de 116:, 112:, 108:, 65:. 50:, 42:, 38:,

Index

Microarchitecture
computer architecture
computer science
microprocessor
ALU
cache memory
control unit
branch predictors
re-order buffer
trace cache
full system simulation
cycle-accurate simulator
instruction set simulator
instruction pipelining
register renaming
reservation stations
out-of-order execution
scoreboarding
SPIM
Multi2Sim
GPGPU-Sim
de
http://www.simplescalar.com
The Official SimpleScalar Website
The Official SPIM Website
The SMTSIM Multithreading Simulator
Categories
Computer architecture
Simulation software

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