118:
233:
22:
63:
368:
dedicated path around the device's boundary (hence the name). The path creates a virtual access capability that circumvents the normal inputs and provides direct control of the device and detailed visibility at its outputs. The contents of the boundary scan are usually described by the manufacturer using a part-specific
460:
Such commercial systems are used by board test professionals and will often cost several thousand dollars for a fully-fledged system. They can include diagnostic options to accurately pin-point faults such as open circuits and shorts and may also offer schematic or layout viewers to depict the fault
319:
between on-chip logical design blocks, with JTAG instructions which operate on those internal scan chains instead of the BSR. This can allow those integrated components to be tested as if they were separate chips on a board. On-chip debugging solutions are heavy users of such internal scan chains.
334:
For normal operation, the added boundary scan latch cells are set so that they have no effect on the circuit, and are therefore effectively invisible. However, when the circuit is set into a test mode, the latches enable a data stream to be shifted from one latch into the next. Once a complete data
367:
Devices communicate to the world via a set of input and output pins. By themselves, these pins provide limited visibility into the workings of the device. However, devices that support boundary scan contain a shift-register cell for each signal pin of the device. These registers are connected in a
347:
By adopting this technique, it is possible for a test system to gain test access to a board. As most of today's boards are very densely populated with components and tracks, it is very difficult for test systems to physically access the relevant areas of the board to enable them to test the board.
295:
on the board; the cell at the destination of the board trace can then be read, verifying that the board trace properly connects the two pins. If the trace is shorted to another signal or if the trace is open, the correct signal value does not show up at the destination pin, indicating a fault.
430:
During testing, I/O signals enter and leave the chip through the boundary-scan cells. Testing involves a number of test vectors, each of which drives some signals and then verifies that the responses are as expected. The boundary-scan cells can be configured to support external testing for
375:
Among other things, a BSDL file will describe each digital signal exposed through pin or ball (depending on the chip packaging) exposed in the boundary scan, as part of its definition of the
Boundary Scan Register (BSR). A description for two balls might look like this:
659:
266:(BSDL) was added which describes the boundary-scan logic content of IEEE Std 1149.1 compliant devices. Since then, this standard has been adopted by electronic device companies all over the world. Boundary scan is now mostly synonymous with JTAG.
439:
Typically high-end commercial JTAG testing systems allow the import of design 'netlists' from CAD/EDA systems plus the BSDL models of boundary scan/JTAG compliant devices to automatically generate test applications. Common types of test include
678:
290:
that is connected to each pin of the device and that can selectively override the functionality of that pin. Each test cell may be programmed via the JTAG scan chain to drive a signal onto a pin and thus across an individual
423:
package), each of which has three components in the BSR: a control configuring the ball (as input, output, what drive level, pullups, pulldowns, and so on); one type of output signal; and one type of input signal.
343:
As the cells can be used to force data into the board, they can set up test conditions. The relevant states can then be fed back into the test system by clocking the data word back so that it can be analyzed.
335:
word has been shifted into the circuit under test, it can be latched into place so it drives external signals. Shifting the word also generally returns the input values from the signals configured as inputs.
457:
When used during manufacturing, such systems also support non-test but affiliated applications such as in-system programming of various types of flash memory: NOR, NAND, and serial (I2C or SPI).
81:
461:
in a graphical manner. Tests developed with such tools are frequently combined with other test systems such as in-circuit testers (ICTs) or functional board test systems.
251:. Boundary scan is also widely used as a debugging method to watch integrated circuit pin states, measure voltage, or analyze sub-blocks inside an integrated circuit.
726:
308:
for each of the external traces. These cells are then connected together to form the external boundary scan shift register (BSR), and combined with
620:
Williams, M. J. Y.; Angel, J. B. (January 1973), "Enhancing
Testability of Large Scale Integrated Circuits via Test Points and Additional Logic",
570:
331:
libraries. Overhead for this additional logic is minimal, and generally is well worth the price to enable efficient testing at the board level.
716:
527:
369:
263:
219:
201:
99:
49:
139:
135:
35:
596:
182:
154:
510:
700:
431:
interconnection between chips (EXTEST instruction) or internal testing for logic within the chip (INTEST instruction).
497:
312:
Test Access Port (TAP) controller support comprising four (or sometimes more) additional pins plus control circuitry.
355:
is a significant issue, and one common design artifact is a set of boundary scan test vectors, possibly delivered in
161:
657:, Eichelberger, Edward, "Method of Level Sensitive Testing a Functional Logic System", issued 9/25/1973
516:
128:
721:
168:
304:
To provide the boundary scan capability, IC vendors add additional logic to each of their devices, including
255:
427:
There are JTAG instructions to SAMPLE the data in that boundary scan register, or PRELOAD it with values.
150:
419:
That shows two balls on a mid-size chip (the boundary scan includes about 620 such lines, in a 361-ball
244:
673:
654:
356:
474:
580:
637:
531:
470:
248:
41:
258:(JTAG) developed a specification for boundary scan testing that was standardized in 1990 as the
575:
703:
Boundary scan JTAG (TAP) architecture and the problems it solves to create high test coverage
676:, Dasgupta, Sumit, "Level sensitive scan design (LSSD) system", issued 10/06/1981
274:
The boundary scan architecture provides a means to test interconnects (including clusters of
629:
175:
522:
478:
420:
352:
279:
482:
710:
641:
556:
292:
559:
Chapter 3 covers boundary scan with JTAG, and other chapters are also informative.
117:
405:"545 (bc_1, GPIO50_ATACS0, output3, X, 544, 1, Z),"
387:"542 (bc_1, GPIO51_ATACS1, output3, X, 541, 1, Z),"
316:
283:
275:
633:
348:
Boundary scan makes access possible without always needing physical probes.
450:
Boundary-scan pin to memory device or device cluster (SRAM, DRAM, DDR etc.)
262:
Std. 1149.1-1990. In 1994, a supplement that contains a description of the
232:
695:
469:
The boundary scan architecture also provides functionality which helps
324:
447:
Boundary-scan device pin to boundary-scan device pin 'interconnect'
231:
537:
493:
James B. Angell at
Stanford University proposed serial testing.
328:
309:
259:
481:. A JTAG Test Access Port (TAP) can be turned into a low-speed
111:
56:
15:
411:"546 (bc_1, GPIO50_ATACS0, input, X),"
399:"544 (bc_1, *, control, 1),"
393:"543 (bc_1, GPIO51_ATACS1, input, X),"
381:"541 (bc_1, *, control, 1),"
696:
Official IEEE 1149.1 Standards
Development Group Website
77:
243:
is a method for testing interconnects (wire lines) on
701:
IEEE 1149.1 JTAG and
Boundary Scan Tutorial - e-Book
142:. Unsourced material may be challenged and removed.
72:
may be too technical for most readers to understand
286:; this involves the addition of at least one
8:
50:Learn how and when to remove these messages
571:"The Embedded Plan For JTAG Boundary Scan"
557:IEEE Std 1149.1 (JTAG) Testability Primer
220:Learn how and when to remove this message
202:Learn how and when to remove this message
100:Learn how and when to remove this message
84:, without removing the technical details.
569:Frenzel, Louis E. (September 11, 2008).
549:
444:Scan-path 'infrastructure' or integrity
359:(SVF) or a similar interchange format.
82:make it understandable to non-experts
7:
140:adding citations to reliable sources
727:Printed circuit board manufacturing
264:Boundary Scan Description Language
14:
585:presents an overview, circa 2008.
351:In modern chip and board design,
31:This article has multiple issues.
595:Oshana, Rob (October 29, 2002).
477:during development stages of an
116:
61:
20:
453:Arbitrary logic cluster testing
323:These designs are part of most
282:, etc.) without using physical
127:needs additional citations for
39:or discuss these issues on the
622:IEEE Transactions on Computers
1:
315:Some TAP controllers support
511:Automated optical inspection
498:level-sensitive scan design
743:
517:Automated x-ray inspection
717:Electronics manufacturing
435:Board test infrastructure
378:
247:or sub-blocks inside an
634:10.1109/T-C.1973.223600
601:Embedded Systems Design
256:Joint Test Action Group
597:"Introduction to JTAG"
300:On-chip infrastructure
245:printed circuit boards
236:
235:
363:JTAG test operations
357:Serial Vector Format
136:improve this article
532:Acceptance testing
528:Functional testing
249:integrated circuit
237:
576:Electronic Design
230:
229:
222:
212:
211:
204:
186:
110:
109:
102:
54:
734:
722:Hardware testing
683:
682:
681:
677:
670:
664:
663:
662:
658:
651:
645:
644:
617:
611:
610:
608:
607:
592:
586:
584:
579:. Archived from
566:
560:
554:
415:
412:
409:
406:
403:
400:
397:
394:
391:
388:
385:
382:
225:
218:
207:
200:
196:
193:
187:
185:
144:
120:
112:
105:
98:
94:
91:
85:
65:
64:
57:
46:
24:
23:
16:
742:
741:
737:
736:
735:
733:
732:
731:
707:
706:
692:
687:
686:
679:
672:
671:
667:
660:
653:
652:
648:
619:
618:
614:
605:
603:
594:
593:
589:
568:
567:
563:
555:
551:
546:
523:In-circuit test
506:
491:
479:embedded system
467:
437:
417:
416:
413:
410:
407:
404:
401:
398:
395:
392:
389:
386:
383:
380:
365:
353:Design For Test
341:
302:
272:
239:
226:
215:
214:
213:
208:
197:
191:
188:
151:"Boundary scan"
145:
143:
133:
121:
106:
95:
89:
86:
78:help improve it
75:
66:
62:
25:
21:
12:
11:
5:
740:
738:
730:
729:
724:
719:
709:
708:
705:
704:
698:
691:
690:External links
688:
685:
684:
665:
646:
612:
587:
583:on 2008-12-01.
561:
548:
547:
545:
542:
541:
540:
535:
525:
519:
513:
505:
502:
496:IBM developed
490:
487:
483:logic analyzer
466:
463:
455:
454:
451:
448:
445:
436:
433:
379:
364:
361:
340:
339:Test mechanism
337:
301:
298:
271:
268:
228:
227:
210:
209:
124:
122:
115:
108:
107:
69:
67:
60:
55:
29:
28:
26:
19:
13:
10:
9:
6:
4:
3:
2:
739:
728:
725:
723:
720:
718:
715:
714:
712:
702:
699:
697:
694:
693:
689:
675:
669:
666:
656:
650:
647:
643:
639:
635:
631:
627:
623:
616:
613:
602:
598:
591:
588:
582:
578:
577:
572:
565:
562:
558:
553:
550:
543:
539:
536:
533:
529:
526:
524:
520:
518:
514:
512:
508:
507:
503:
501:
499:
494:
488:
486:
484:
480:
476:
472:
464:
462:
458:
452:
449:
446:
443:
442:
441:
434:
432:
428:
425:
422:
377:
373:
371:
362:
360:
358:
354:
349:
345:
338:
336:
332:
330:
326:
321:
318:
313:
311:
307:
299:
297:
294:
289:
285:
281:
277:
269:
267:
265:
261:
257:
252:
250:
246:
242:
241:Boundary scan
234:
224:
221:
206:
203:
195:
184:
181:
177:
174:
170:
167:
163:
160:
156:
153: –
152:
148:
147:Find sources:
141:
137:
131:
130:
125:This article
123:
119:
114:
113:
104:
101:
93:
83:
79:
73:
70:This article
68:
59:
58:
53:
51:
44:
43:
38:
37:
32:
27:
18:
17:
668:
649:
628:(1): 46–60,
625:
621:
615:
604:. Retrieved
600:
590:
581:the original
574:
564:
552:
495:
492:
468:
459:
456:
438:
429:
426:
418:
374:
366:
350:
346:
342:
333:
322:
314:
305:
303:
287:
273:
253:
240:
238:
216:
198:
189:
179:
172:
165:
158:
146:
134:Please help
129:verification
126:
96:
87:
71:
47:
40:
34:
33:Please help
30:
317:scan chains
284:test probes
711:Categories
674:US 4293919
655:US 3761695
606:2007-04-05
544:References
471:developers
306:scan cells
192:April 2024
162:newspapers
90:April 2024
36:improve it
475:engineers
465:Debugging
288:test cell
42:talk page
504:See also
500:(LSSD).
280:memories
642:5427856
489:History
325:Verilog
270:Testing
176:scholar
76:Please
680:
661:
640:
372:file.
178:
171:
164:
157:
149:
638:S2CID
530:(see
414:&
408:&
402:&
396:&
390:&
384:&
293:trace
276:logic
183:JSTOR
169:books
626:C-22
538:JTAG
521:ICT
515:AXI
509:AOI
473:and
370:BSDL
329:VHDL
310:JTAG
260:IEEE
254:The
155:news
630:doi
421:BGA
327:or
138:by
80:to
713::
636:,
624:,
599:.
573:.
485:.
278:,
45:.
632::
609:.
534:)
223:)
217:(
205:)
199:(
194:)
190:(
180:·
173:·
166:·
159:·
132:.
103:)
97:(
92:)
88:(
74:.
52:)
48:(
Text is available under the Creative Commons Attribution-ShareAlike License. Additional terms may apply.
