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comparison and moving of non-word aligned 6-bit character data. The Cyber-73 could be configured with either one or two CPUs. The dual CPU version replaced the CDC 6500. As was the case with the CDC 6200, CDC also offered a Cyber-72. The Cyber-72 had identical hardware to a Cyber-73, but added additional clock cycles to each instruction to slow it down. This allowed CDC to offer a lower performance version at a lower price point without the need to develop new hardware. It could also be delivered with dual CPUs. The Cyber 74 was an updated version of the CDC 6600. The Cyber 76 was essentially a renamed
196:
284:(A0 through A7), eight 18-bit index registers (B0 through B7), and eight 60-bit operand registers (X0 through X7). Seven of the A registers are tied to their corresponding X register. Setting A1 through A5 reads that address and fetches it into the corresponding X1 through X5 register. Likewise, setting register A6 or A7 writes the corresponding X6 or X7 register to central memory at the address written to the A register. A0 is effectively a scratch register.
324:
use 30 bits, but its alignment requires 60 bits to be used). The instructions are: move a short string, move a long string, compare strings, and compare a collated string. They operate on six-bit fields (numbered 1 through 10) in central memory. For example, a single instruction can specify "move the 72 character string starting at word 1000 character 3 to location 2000 character 9". The CMU hardware is not included in the higher-end Cyber CPUs, because
779:
94:
727:. The Bell Operating Companies purchased large numbers of these systems in the mid-to-late 1980s for data communications. In the late 1980s the XN10 was released with an improved processor (a direct memory access instruction was added) as well as a size reduction from two cabinets to one. The XN20 was an improved version of the XN10 with a much smaller footprint. The Line Termination Sub-System was redesigned to use the improved
748:
78:
117:(CDC) during the 1970s and 1980s. In their day, they were the computer architecture of choice for scientific and mathematically intensive computing. They were used for modeling fluid flow, material science stress analysis, electrochemical machining analysis, probabilistic analysis, energy and academic computing, radiation shielding modeling, and other applications. The lineup also included the Cyber 18 and Cyber 1000
258:. In CDC lingo, the term "byte" referred to 12-bit entities (which coincided with the word size used by the peripheral processors). Characters were six bits, operation codes were six bits, and central memory addresses were 18 bits. Central processor instructions were either 15 bits or 30 bits. The 18-bit addressing inherent to the Cyber 170 series imposed a limit of 262,144 (256K) words of main memory, which is
204:
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273:. Due to the relatively slow memory reference times of the CPU (in some models, memory reference instructions were slower than floating-point divides), the higher-end CPUs (e.g., Cyber-74, Cyber-76, Cyber-175, and Cyber-176) are equipped with eight or twelve words of high-speed memory used as an instruction cache. Any loop that fit into the cache (which is usually called
335:(Network Operating System). Version 1 of NOS continued to be updated until about 1981; NOS version 2 was released early 1982, with the final version of 2.8.7 PSR 871, delivered in December 1997, which continues to have minor unofficial bug fixes, Y2K mitigation, etc in support of DtCyber. Besides NOS, the only other operating systems commonly used on the 170 series was
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707:
crypto-analysis work. The MP32 had the
Fortran math runtime library package built into its microcode. The Soviet Union tried to buy several of these systems and they were being built when the U.S. Government cancelled the order. The parts for the MP32 were absorbed into the Cyber 18 production. One of the uses of the Cyber 18 was monitoring the Alaskan Pipeline.
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to run both EI plus NOS and the customer's existing 170-mode software. To hide this process from the customer, earlier in the 1980s CDC had ceased distribution of the source code for its
Deadstart Diagnostic Sequence (DDS) package and turned it into the proprietary Common Tests & Initialization (CTI) package.
489:. The new name kept with their new branding, and perhaps to distance itself from the STAR's failure. The Cyber 203 contains redesigned scalar processing and loosely coupled I/O design, but retains the STAR's vector pipeline. Best estimates claim that two Cyber 203s were delivered or upgraded from STAR-100s.
432:
The peripheral processors in the true 180s are always 16-bit machines with the sign bit determining whether a 16/64 bit or 12/60 bit PP instruction is being executed. The single word I/O instructions in the PPs are always 16-bit instructions, so at deadstart the PPs can set up the proper environment
366:
Cyber 180 development began in the
Advanced Systems Laboratory, a joint CDC/NCR development venture started in 1973 and located in Escondido, California. The machine family was originally called Integrated Product Line (IPL) and was intended to be a virtual memory replacement for the NCR 6150 and CDC
323:
A feature of the lower Cyber CPUs is the
Compare Move Unit (CMU). It provides four additional instructions intended to aid text processing applications. In an unusual departure from the rest of the 15- and 30-bit instructions, these are 60-bit instructions (three actually use all 60 bits, the other
671:
and Cyber 70/Cyber 170 mainframes. The 2550 was a product of CDC's
Communications Systems Division, in Santa Ana, California (STAOPS). STAOPS also produced another communication processor (CP), used in networks hosted by IBM mainframes. This M1000 CP, later renamed C1000, came from an acquisition
436:
The initial 170/800 lineup was: 170/825 (P1), 170/835 (P2), 170/855 (P3), 170/865 and 170/875. The 825 was released initially after some delay loops had been added to its microcode; it seemed the design folks in
Toronto had done a little too well and it was too close to the P2 in performance. The
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channels and all of the system's central memory (CM) in addition to the PP's own memory. The PP instruction set lacks, for example, extensive arithmetic capabilities and does not run user code; the peripheral processor subsystem's purpose is to process I/O and thereby free the more powerful central
357:
which was in common use up until 1975 or so. Due to the strong dependency of developed applications on the particular installation's character set, many installations chose to run the older operating systems rather than convert their applications. Other installations would patch newer versions of
428:
The 180s were initially marketed as 170/8xx machines with no mention of the new 8/64-bit system inside. However, the primary control program is a 180-mode program known as
Environmental Interface (EI). The 170 operating system (NOS) used a single, large, fixed page within the main memory. There
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data from central memory well before that data is needed. By interleaving independent instructions between the memory fetch instruction and the instructions manipulating the fetched operand, the time occupied by the memory fetch can be used for other computation. With this technique, coupled with
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series and therefore shared almost all of the earlier architecture's characteristics. The Cyber-70 series is a minor upgrade from the earlier systems. The Cyber-73 was largely the same hardware as the CDC 6400 - with the addition of a
Compare and Move Unit (CMU). The CMU instructions speeded up
590:
installations were operational in 1986. These parallel processing systems include from 1 to 256 Cyberplus processors providing 250 MFLOPS each, which are connected to an existing Cyber system via a direct memory interconnect architecture (MIA), this was available on NOS 2.2 for the Cyber 170/835,
473:
pipe, which supports vector lengths of up to 65,536 elements. The latencies of the vector pipeline are very long, so peak speed is approached only when very long vectors are used. The scalar processor was deliberately simplified to provide room for the vector processor and is relatively slow in
444:
A year or two after the initial release, CDC announced the 800-series' true capabilities to its customers, and the true 180s were relabeled as the 180/825 (P1), 180/835 (P2), and 180/855 (P3). At some point, the model 815 was introduced with the delayed microcode and the faster microcode was
409:
The true 180-mode machines are microcoded processors that can support both instruction sets simultaneously. Their hardware is completely different from the earlier 6000/70/170 machines. The small 170-mode exchange package was mapped into the much larger 180-mode exchange package; within the
578:
Each
Cyberplus (aka Advanced Flexible Processor, AFP) is a 16-bit processor with optional 64-bit floating point capabilities and has 256 K or 512 K words of 64-bit memory. The AFP was the successor to the Flexible Processor (FP), whose design development started in 1972 under black-project
706:
processors with up to 128K words of memory, four additional general registers, and an enhanced instruction set. The Cyber 18-30 had dual processors. A special version of the Cyber 18, known as the MP32, that was 32-bit instead of 16-bit was created for the
National Security Agency for
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in 1983 when the Cyber 205 Series 600 was introduced. The Series 600 differs in memory technology and packaging but is otherwise the same. A single four-pipe Cyber 205 was installed. All other sites appear to be two-pipe installations with final count to be determined.
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microprocessor (the Buffer Controller card, Programmable Line Controller card and two Communication Line Interface cards were incorporated on to a single card). The XN20 was in pre-production stage when the Communication Systems Division was shut down in 1992.
277:) runs very fast, without referencing main memory for instruction fetch. The lower-end models do not contain an instruction stack. However, since up to four instructions are packed into each 60-bit word, some degree of prefetching is inherent in the design.
379:. The joint venture was abandoned in 1976, with CDC continuing system development and renaming the Cyber 80 as Cyber 180. The first machines of the series were announced in 1982 and the product announcement for the NOS/VE operating system occurred in 1983.
650:
A fully configured 256 processor Cyberplus system would have a theoretical performance of 64 GFLOPS, and weigh around 256 tonnes. A nine-unit system was reputedly capable of performing comparative analysis (including pre-processing convolutions) on 1
425:. The P1 was a novel air-cooled, 60-board cabinet designed by a group in Mississauga; the P1 ran on 60 Hz current (no motor-generator sets needed). A fourth high-end 180 model 990 (codenamed THETA) was also under development in Arden Hills.
715:
The M1000 / C1000, later renamed Cyber 1000, was used as a message store and forward system used by the Federal Reserve System. A version of the Cyber 1000 with its hard drive removed was used by Bell Telephone. This was a RISC processor
429:
were a few clues that an alert user could pick up on, such as the "building page tables" message that flashed on the operator's console at startup and deadstart panels with 16 (instead of 12) toggle switches per PP word on the P2 and P3.
583:, with four mask registers and a condition-hold register; three bits in the microinstruction format select among nearly 50 conditions for determining execution, including result sign and overflow, I/O conditions, and loop control.
515:. Cyber 205 systems were available with two or four vector pipelines, with the four-pipe version theoretically delivering 400 64-bit MFLOPs and 800 32-bit MFLOPs. These speeds are rarely seen in practice other than by handcrafted
437:
865 and 875 models were revamped 170/760 heads (one or two processors with 6600/7600-style parallel functional units) with larger memories. The 865 used normal 170 memory; the 875 took its faster main processor memory from the
410:
180-mode exchange package, there is a virtual machine identifier (VMID) that determines whether the 8/16/64-bit two's complement 180 instruction set or the 12/60-bit ones' complement 170 instruction set is executed.
291:(e.g., shift, increment, floating add) which allowed some degree of parallel execution of instructions. This parallelism allows assembly programmers to minimize the effects of the system's slow memory fetch time by
247:. The 172, 173, and 174 use integrated circuits and semiconductor memory whereas the 175 uses high-speed discrete transistors. The Cyber-170/700 series is a late-1970s refresh of the Cyber-170 line.
375:-like language, was developed for the project with the intent that all languages and the operating system (IPLOS) were going to be written in SWL. SWL was later renamed PASCAL-X and eventually became
303:
to share the execution unit; each PP had its own memory and registers, but the processor (the slot) itself executed one instruction from each PP in turn (the barrel). This is a crude form of hardware
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in September 1983. A final development was the Cyber 250, which was scheduled for release in 1987 priced at $ 20 million; it was later renamed the ETA30 after ETA Systems was absorbed back into CDC.
504:, England was the first customer and they received their Cyber 205 in 1981. The Cyber 205 replaces the STAR vector pipeline with redesigned vector pipelines: both scalar and vector units utilized
296:
the handcrafting of tight loops that fit within the instruction stack, a skilled Cyber assembly programmer can write extremely efficient code that makes the most of the power of the hardware.
527:(very complex instruction set) among modern processors. Many specialized operations facilitate hardware searches, matrix mathematics, and special instructions that enable decryption.
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Physically, each Cyberplus processor unit was of typical mainframe module size, similar to the Cyber 180 systems, with the exact width dependent on whether the optional
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size, CDC customers started pushing for the Cyber machines to do the same. The result was a new series of systems that could operate in both 60- and 64-bit modes. The
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that run at either 25 or 40 MHz, and is equipped with 10, 14, 17, or 20 peripheral processors (PP), and up to 24 high-performance channels for high-speed
1434:
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minicomputer. It was mostly used in real-time environments. One noteworthy application is as the basis of the 2550—a communications processor used by
183:
Primarily aimed at large office applications instead of the traditional supercomputer tasks, some of the Cyber machines nevertheless included basic
702:"Cyber 18-17" was just a new name for the System 17, based on the 1784 processor. Other Cyber 18s (Cyber 18-05, 18-10, 18-20, and 18-30) had
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were also available. Operating systems included RTOS (Real-Time Operating System), MSOS 5 (Mass Storage Operating System), and TIMESHARE 3 (
413:
There were three true 180s in the initial lineup, codenamed P1, P2, P3. P2 and P3 were larger water-cooled designs. The P2 was designed in
930:
1138:
1045:
Allen, G. (1982). "A Reconfigurable Architecture for Arrays of Microprogrammable Processor". In Fu, K. S.; Ichikawa, Tadao (eds.).
869:(7). Department of Mathematics and School of Biomedical Engineering, Indian Institute of Technology Powai, Bombay, India: 687–697.
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memory in this series. The central processor has no I/O instructions, relying upon the peripheral processor (PP) units to do I/O.
717:
524:
307:. The peripheral processors have 4096 bytes of 12-bit memory words and an 18-bit accumulator register. Each PP has access to all
51:
319:
CDC documentation came in single sheets punched for three-ring- or twenty-two-ring binders, so updates were easily accomplished.
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It appeared that all of the problems in the STAR were solvable. In the late 1970s, CDC addressed some of these issues with the
735:
Jack Ralph was the chief architect of the Cyber 1000-2, XN-10 and XN-20 systems. Dan Nay was the chief engineer of the XN-20.
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circumstances targeted at processing radar and photo image data. The FP control unit had a hardware network for
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instructions added for high performance on a certain class of math tasks. The STAR's vector pipeline is a
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networks being tuned by hand-crafted coax length adjustment. The instruction set would be considered V-
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Dongarra, J. J.; Duff, I. S.; UKAEA Harwell Lab (UK) Computer Science and Systems Div.) (1989-09-01).
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244:
236:
232:
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Lincoln, N. R. (1982). "Technology and Design Tradeoffs in the Creation of a Modern Supercomputer".
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126:
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Cyber 70 product lines. The IPL system was also called the Cyber 80 in development documents. The
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720:). An improved version known as the Cyber 1000-2 with the Line Termination Sub-System added 256
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of Marshall MDM Communications. A three-board set was added to the Cyber 18 to create the 2550.
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Rajani R. Joshi (9 June 1998). "A new heuristic algorithm for probabilistic optimization".
478:. As such, the original STAR proved to be a great disappointment when it was released (see
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the operating system to use the older character set to maintain application compatibility.
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The 180 series developed by a team in Canada—released in the 1980s (after the 200 series)
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406:, could run in a special address space for compatibility with the older systems.
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1087:"Usenet post to "Re: 11! CDC/Cyberplus [1]" thread, 24th December 1991"
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As with predecessor systems, the Cyber 170 series has eight 18-bit address
347:, a product of CDC's Sunnyvale division. These operating systems provide
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1, 2, 4, 8 or 16 million 64-bit words with 25.6 or 51.2 Gigabits/second
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restored to the model 825. Eventually the THETA was released as the
403:
391:
387:
337:
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482:). Best estimates claim that three STAR-100 systems were delivered.
663:
The Cyber 18 is a 16-bit minicomputer which was a successor to the
398:
capabilities of the hardware. The older 60-bit operating systems,
351:
of batch and interactive applications. The predecessor to NOS was
166:
1404:
1319:
1309:
777:
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The Cyber 70 and 170 architectures were successors to the earlier
194:
92:
84:
76:
519:. The ECL gate array ICs contain 168 logic gates each, with the
383:
1134:
228:. Neither the Cyber-74 nor the Cyber-76 had CMU instructions.
956:
Parallel Computers 2: Architecture, Programming and Algorithms
742:
461:
architecture. The STAR is an entirely new 64-bit design with
308:
270:
29:
812:
Compared to the tightly coupled I/O used on previous designs.
328:
loops could run as fast or faster than the CMU instructions.
299:
The peripheral processor subsystem uses a technique known as
137:
The Cyber line included five different series of computers:
254:(CPU) and central memory (CM) operated in units of 60-bit
199:
Hardware architecture of the CDC Cyber 170 series computer
913:. OECD Nuclear Energy Agency, Issy-les-Moulineaux, France
891:"A History of Supercomputing at Florida State University"
231:
The Cyber-170 series represented CDCs move from discrete
911:"Abstract for SAMSY – Shielding Analysis Modular System"
759:
141:
The 70 and 170 series based on the architecture of the
1047:
Special Computer Architectures for Pattern Processing
795:—contains several predecessors to the Cyber 70 series
1049:. Boca Raton, Florida: CRC Press. pp. 157–189.
382:
As the computing world standardized to an eight-bit
1390:
1364:
1287:
1251:
1198:
1168:
43:It has been suggested that this article should be
606:Software that was bundled with the Cyberplus was:
265:A Cyber 170-series system consists of one or two
312:processor unit(s) to running user computations.
187:for added performance in traditional CDC roles.
958:. Philadelphia: Adam Hilger. pp. 155–185.
655:images at a rate of one image pair per second.
643:and the Gesellschaft für Trendanalysen (GfTA) (
569:8 I/O ports with up to 16 200 Mbits/second each
574:Cyberplus or Advanced Flexible Processor (AFP)
1146:
492:In 1980, the successor to the Cyber 203, the
8:
1440:Control Data Corporation mainframe computers
538:The Cyber 205 architecture evolved into the
598:was installed, and weighed approximately 1
1248:
1153:
1139:
1131:
617:MICA (Machine Instruction Cross Assembler)
287:The higher-end CPUs consisted of multiple
839:. Oxford University Press. Archived from
675:The Cyber 18 was generally programmed in
563:Up to 800 Mflops FP32 ans 400 Mflops FP64
954:Hockney, R. W.; Jesshope, C. R. (1988).
639:Some sites using the Cyberplus were the
207:Module of the CDC Cyber 175 operated at
202:
1072:"CDC Advanced Flexible Processor (AFP)"
824:
805:
27:Range of mainframe-class supercomputers
581:conditional microinstruction execution
530:The original Cyber 205 was renamed to
7:
169:or Advanced Flexible Processor (AFP)
863:Computers & Operations Research
81:A CDC Cyber 170 Computer room, 1986
837:IMA Journal of Applied Mathematics
331:Later systems typically run CDC's
25:
1435:Control Data Corporation hardware
542:as the design team spun off into
125:, they were unusual in using the
1189:
1070:Mark Smotherman (October 2009).
746:
718:reduced instruction set computer
34:
1016:Advanced architecture computers
645:Association for Trend Analyses
121:. Like their predecessor, the
1:
875:10.1016/S0305-0548(96)00056-1
591:845, 855 and 180/990 models.
113:were the primary products of
558:20 ns cycle time (or 50 MHz)
555:Architecture: ECL/LSI logic
457:In 1974, CDC introduced the
390:operating system was called
155:The 200 series based on the
1121:, December 1, 1986, page 4)
1461:
944:, November 19, 1975, p. 47
833:"(search for Cyber terms)"
369:Software Writer's Language
49:into a new article titled
1332:Chippewa Operating System
1187:
620:Load File Builder Utility
97:A CDC Cyber 70/74 console
1162:Control Data Corporation
511:ICs and are cooled with
115:Control Data Corporation
1382:PLATO (computer system)
993:10.1109/TC.1982.1676013
879:(requires subscription)
191:Cyber 70 and 170 series
159:—released in the 1970s.
129:binary representation.
1115:CDC IBM front end bows
783:
614:FORTRAN cross compiler
586:At least 21 Cyberplus
496:was announced. The UK
423:Arden Hills, Minnesota
320:
212:
209:RWTH Aachen University
200:
98:
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82:
1377:Storage Module Device
781:
641:University of Georgia
632:Dump analyzer utility
498:Meteorological Office
318:
233:electronic components
206:
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80:
1391:Affiliated companies
635:Maintenance software
532:Cyber 205 Series 400
394:, and supported the
371:(SWL), a high-level
245:semiconductor memory
1125:Cyber documentation
889:Jeff Bauer (1991).
341:or its predecessor
241:integrated circuits
185:vector instructions
981:IEEE Trans. Comput
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758:. You can help by
474:comparison to the
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1085:Ahrendt, Gunter.
800:Explanatory notes
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704:microprogrammable
681:assembly language
623:ECHOS (simulator)
517:assembly language
467:vector processing
89:A CDC Cyber 70/74
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16:(Redirected from
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1037:
1006:
987:(5): 349–362.
971:
964:
946:
934:
923:
902:
881:
853:
823:
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815:
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803:
801:
798:
797:
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788:
785:
782:CDC Cyber 2000
774:
773:
753:
751:
740:
737:
712:
709:
660:
657:
647:) in Germany.
637:
636:
633:
630:
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626:Debug facility
624:
621:
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612:
608:
607:
588:multiprocessor
575:
572:
571:
570:
567:
564:
561:
560:
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551:
548:
463:virtual memory
454:
451:
396:virtual memory
363:
360:
192:
189:
181:
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170:
163:
160:
153:
152:, respectively
150:supercomputers
134:
131:
111:supercomputers
73:
72:
42:
40:
33:
26:
24:
14:
13:
10:
9:
6:
4:
3:
2:
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1266:CDC Cyber 200
1264:
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1123:
1120:
1119:Network World
1116:
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994:
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986:
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942:Computerworld
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868:
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843:on 2013-04-15
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828:
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809:
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754:This section
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584:
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557:
556:
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550:CDC CYBER 205
549:
547:
545:
541:
536:
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528:
526:
522:
518:
514:
510:
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503:
499:
495:
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317:
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297:
294:
290:
285:
283:
278:
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272:
268:
263:
261:
260:semiconductor
257:
253:
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246:
242:
238:
234:
229:
227:
222:
218:
210:
205:
197:
190:
188:
186:
179:
176:based on the
175:
172:The Cyber 18
171:
168:
164:
161:
158:
154:
151:
148:
144:
140:
139:
138:
132:
130:
128:
124:
120:
119:minicomputers
116:
112:
108:
104:
95:
87:
79:
69:
66:November 2021
60:
56:
55:
54:
53:CDC Cyber 200
48:
47:
41:
32:
31:
19:
18:CDC Cyber 200
1393:and products
1278:
1261:CDC STAR-100
1181:Seymour Cray
1118:
1117:(Article in
1095:. Retrieved
1090:
1080:
1065:
1046:
1040:
1009:
984:
980:
974:
955:
949:
937:
926:
915:. Retrieved
905:
894:. Retrieved
884:
866:
862:
856:
845:. Retrieved
841:the original
836:
827:
808:
764:
760:adding to it
755:
734:
714:
701:
697:time-sharing
674:
662:
649:
644:
638:
629:Dump utility
593:
585:
577:
537:
531:
529:
493:
491:
486:
484:
480:Amdahl's Law
470:
456:
446:
443:
438:
435:
431:
427:
412:
408:
381:
365:
352:
349:time-sharing
342:
336:
330:
322:
300:
298:
293:pre-fetching
292:
286:
279:
274:
264:
250:The central
249:
230:
214:
211:, about 1985
182:
174:minicomputer
157:CDC STAR-100
136:
102:
100:
63:
52:
50:
44:
1400:ETA Systems
1301:Languages:
544:ETA Systems
415:Mississauga
237:core memory
1429:Categories
1337:CDC Kronos
1169:Key people
1097:6 February
1056:0849361001
1018:(Report).
965:0852748116
917:2008-07-01
896:2008-07-01
847:2008-07-01
820:References
739:Cyber 2000
711:Cyber 1000
521:clock tree
509:gate array
326:hand coded
1414:Cray Inc.
1354:CDC SCOPE
1279:CDC Cyber
1199:Computers
767:June 2021
722:Zilog Z80
699:system).
653:megapixel
502:Bracknell
494:Cyber 205
487:Cyber 203
447:Cyber 990
439:Cyber 205
282:registers
252:processor
167:Cyberplus
107:mainframe
105:range of
103:CDC Cyber
1372:CDC Wren
1288:Software
1243:CDC 8600
1238:CDC 7600
1231:CDC 6600
1216:CDC 1700
1206:CDC 1604
1001:14047755
787:See also
665:CDC 1700
659:Cyber 18
476:CDC 7600
275:in-stack
226:CDC 7600
221:CDC 7600
217:CDC 6600
178:CDC 1700
147:CDC 7600
143:CDC 6600
123:CDC 6600
1305:COMPASS
1032:5702408
685:FORTRAN
419:Ontario
109:-class
59:discuss
1347:NOS/VE
1253:Vector
1053:
1030:
999:
962:
693:RPG II
691:, and
677:Pascal
441:line.
404:NOS/BE
392:NOS/VE
388:64-bit
373:Pascal
354:Kronos
338:NOS/BE
133:Models
1405:ETA10
1320:MIMIC
1315:Cybil
1310:SYMPL
997:S2CID
689:BASIC
600:tonne
540:ETA10
513:Freon
377:Cybil
344:SCOPE
256:words
46:split
1328:OS:
1099:2014
1051:ISBN
1028:OSTI
985:C-31
960:ISBN
729:Z180
679:and
525:CISC
465:and
459:STAR
402:and
384:byte
267:CPUs
243:and
235:and
219:and
165:The
145:and
101:The
1342:NOS
1295:026
1020:doi
989:doi
871:doi
762:.
596:FPU
506:ECL
500:at
400:NOS
333:NOS
309:I/O
271:I/O
239:to
61:)
57:. (
1431::
1089:.
1026:.
995:.
983:.
867:24
865:.
835:.
687:,
683:;
602:.
449:.
417:,
1154:e
1147:t
1140:v
1101:.
1074:.
1059:.
1034:.
1022::
1003:.
991::
968:.
920:.
899:.
877:.
873::
850:.
769:)
765:(
716:(
68:)
64:(
20:)
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