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78:, whereas the majority of microprocessors use SRAM for their internal caches. This was the first microprocessor to use one-transistor DRAM for cache. DEC chose to use DRAM for the cache to reduce the area of the cache array. The designers concluded that to implement this cache with four-transistor DRAM cells or six-transistor SRAM cells would have taken 2.4 to 3 times more area. The internal cache is located in a narrow strip along the left side of the
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executing addition, subtraction and logic instructions. Although the E-Box contains a dedicated shifter, the ALU also features a shifter, a less powerful one, for the purpose of executing integer multiply and divide instructions. The design of the register file permits these execution units to achieve higher performance by permitting more instances of simultaneous access to the registers.
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The microprocessor is microprogrammed and partially pipelined and consists of six major functional units, the I-Box, E-Box, M-box, bus interface unit (BIU), cache, and control store and microsequencer. The I-Box fetches VAX instructions from the cache and decodes them (parses) into macroinstructions.
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The M-Box is the memory management unit. It has a 28-entry fully associative translation look-aside buffer (TLB) to translate virtual addresses into physical address. In addition to the TLB, it has registers that determine the memory address to read or write to. The M-Box works closely with the BIU,
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referred to a microprocessor which contained the CVAX 78034, CFPA, clock chip, and an 8 KB second level cache on a single die. Operating at 25 or 28.5 MHz, it was introduced in 1990 and used in entry-level servers, workstations, VXT-2000 X terminals, and as an embedded microprocessor in DEC's
105:
The control store and microsequencer provides the means of controls of the operation of the other functional units with microcode. The control store has a ROM containing 1,600 41-bit words. Each 41-bit word is divided into two, a 28-bit field that controls the functional units, and a 13-bit field
97:
The E-Box consists of a register file, a 32-bit program counter, a constant generator, a shifter and an arithmetic logic unit (ALU). The register file contains 31 single-read-port/single-write-port registers and eight dual-read-port/single-write port registers. The ALU is 32-bit and is capable of
145:
referred to an optical shrink of the original CVAX fabricated in DEC's second-generation CMOS process, CMOS-2, a 1.5 μm process with two levels of wiring. The original design team shrunk the CVAX 78034, CFPA and CMCTL, with the other chips left unchanged. The shrunk 78034 was known as the
54:
The CVAX 78034, also known as the MicroVAX 78034, is a second-generation single-chip VAX microprocessor. Systems featuring the CVAX chip set became available in late 1987. It is clocked at frequencies of 12.5 MHz (80 ns) in higher-end systems such as the
46:(ISA). The chipset consisted of the CVAX 78034 CPU, CFPA floating-point accelerator, CVAX clock chip, and the associated support chips, the CVAX System Support Chip (CSSC), CVAX Memory Controller (CMCTL), and CVAX Q-Bus Interface Chip (CQBIC).
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that controls the microsequencer. Unlike the MicroVAX 78032, which uses X-shaped cells, the 78034 uses conventional H-shaped cells. The microsequencer's purpose is to supply microaddresses to the control store.
85:
The 78034 contains 134,000 transistors on a die measuring 9.7 by 7.4 mm (71.78 mm). It is fabricated in DEC's first-generation CMOS process, CMOS-1, a 2.0 μm CMOS process with two layers of
117:
The CFPA contains 65,000 transistors on a die measuring 7.3 by 9.1 mm (66.43 mm). It is fabricated in DEC's first-generation CMOS process, CMOS-1, a 2.0 μm process with two layers of
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The 78034 was the first VAX microprocessor to have internal caches, a 1 KB combined instruction and data stream cache. The cache is quite unusual as it is implemented with one-transistor
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high-end printers and terminals. It was fabricated in DEC's third-generation CMOS process, CMOS-3, a 1.0 μm process with three levels of wiring.
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The CVAX+ started to ship in late 1988, as upgrades to all entry-level CVAX-based systems and were also provided as an upgrade to the
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A CVAX system card with the CVAX CPU on the right, the CFPA floating-point unit on the left, and the CVAX clock chip above the CFPA.
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which controls access to the internal cache and interfaces the microprocessor to the 32-bit address data multiplexed external bus.
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taped out in
November 1987. The CVAX+ operated at 16.67 MHz, but power requirements was unchanged.
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Thomas F. Fox; Paul E. Cronowski; Anil K. Jain; Burton M. Leary; Daniel G. Miner (August 1988).
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The CFPA (CVAX Floating Point
Accelerator) is a floating point coprocessor for the CVAX 78034.
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The I-Box has an IROM (Instruction decode ROM) that holds the information required to do so.
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Edward J. McLellan; Gilbert M. Wolrich; Robert AJ Wodlowski (August 1988).
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and at 11.11 MHz (90 ns) in lower-end systems such as the
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246:. No. 7. Digital Equipment Corporation. pp. 109–120.
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224:. No. 7. Digital Equipment Corporation. pp. 95–106.
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1001:Mass Storage Control Protocol
297:Digital Equipment Corporation
165:was delayed by yield issues.
37:Digital Equipment Corporation
1091:Digital Federal Credit Union
313:(founder and CEO, 1957–1992)
70:DEC CVAX+ 78034 CPU die shot
44:instruction set architecture
1135:Sequence and Batch Language
1096:Dynamic debugging technique
39:(DEC) that implemented the
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1126:Record Management Services
912:Standard Disk Interconnect
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1160:The Ultimate Entrepreneur
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244:Digital Technical Journal
222:Digital Technical Journal
177:DEC CVAX SOC CPU die shot
161:when the introduction of
823:DIGITAL Command Language
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1149:Systems Research Center
1144:System Reference Manual
1235:32-bit microprocessors
1116:On-line Debugging Tool
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61:MicroVAX 3500 and 3600
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304:Key people
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429:Mariah
372:LSI-11
365:PDP-11
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1139:Sixel
1131:ReGIS
1101:FX!32
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446:Alpha
424:Rigel
240:(PDF)
218:(PDF)
163:Rigel
143:CVAX+
130:CVAX+
31:is a
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1021:RL02
1016:RK05
1011:RA90
763:MICA
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