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interconnects were subject to restrictions; were made to run in straight lines aligned east–west or north–south. To allow easy routing, alternate levels of interconnect ran in the same alignment, so that changes in direction were achieved by connecting to a lower or upper level of interconnect though a via. Local interconnects, especially the lowest level (usually polysilicon) could assume a more arbitrary combination of routing options to attain the a higher packing density.
459:. The bottom-most metal layers of the chip, closest to the transistors, have thin, narrow, tightly-packed wires, used only for local interconnect. Adding layers can potentially improve performance, but adding layers also reduces yield and increases manufacturing costs. ICs with a single metal layer typically use the polysilicon layer to "jump across" when one signal needs to cross another signal.
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to ensure the whole IC has an acceptable variation in interconnect density. This is because the rate at which CMP removes material depends on the material's properties, and great variations in interconnect density can result in large areas of dielectric which can dish, resulting in poor planarity. To
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The AR is an important factor. In technologies that form interconnect structures with conventional processes, the AR is limited to ensure that the etch creating the interconnect, and the dielectric deposition that fills the voids in between interconnects with dielectric, can be done successfully. In
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Before the introduction of CMP for planarizing IC layers, interconnects had design rules that specified larger minimum widths and spaces than the lower level to ensure that the underlying layer's rough topology did not cause breaks in the interconnect formed on top. The introduction of CMP has made
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IC with complex circuits require multiple levels of interconnect to form circuits that have minimal area. As of 2018, the most complex ICs may have over 15 layers of interconnect. Each level of interconnect is separated from each other by a layer of dielectric. To make vertical connections between
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Historically, interconnects were routed in straight lines, and could change direction by using sections aligned 45° away from the direction of travel. As IC structure geometries became smaller, to obtain acceptable yields, restrictions were imposed on interconnect direction. Initially, only global
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interconnects depending on the signal propagation distance it is able to support. The width and thickness of the interconnect, as well as the material from which it is made, are some of the significant factors that determine the distance a signal may propagate. Local interconnects connect circuit
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The geometric properties of an interconnect are width, thickness, spacing (the distance between an interconnect and another on the same level), pitch (the sum of the width and spacing), and aspect ratio, or AR, (the thickness divided by width). The width, spacing, AR, and ultimately, pitch, are
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between the levels of interconnect is necessary, otherwise barrier layers are needed. Suitability for fabrication is also required; some chemistries and processes prevent the integration of materials and unit processes into a larger technology (recipe) for IC fabrication. In fabrication,
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elements that are very close together, such as transistors separated by ten or so other contiguously laid out transistors. Global interconnects can transmit further, such as over large-area sub-circuits. Consequently, local interconnects may be formed from materials with relatively high
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pockets (air gap dielectric). These materials often have low mechanical strength and are restricted to the lowest level or levels of interconnect as a result. The high density of interconnects at the lower levels, along with the minimal spacing, helps support the upper layers.
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ICs, the most commonly used semiconductor in ICs, the first interconnects were made of aluminum. Aluminum was an ideal material for interconnects due to its ease of deposition and good adherence to silicon and silicon dioxide. Al interconnects are deposited by
421:, were introduced during the late 1990s and early 2000s for this purpose. As of January 2019, the most advanced materials reduce the dielectric constant to very low levels through highly porous structures, or through the creation of substantial air or
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that ensure the interconnect (and thus the IC) can be fabricated by the selected technology with a reasonable yield. Width is constrained to ensure minimum width interconnects do not suffer breaks, and maximum width interconnects can be planarized by
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are structures that connect two or more circuit elements (such as transistors) together electrically. The design and layout of interconnects on an IC is vital to its proper function, performance, power efficiency, reliability, and
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those that form interconnect structures with damascene processes, the AR must permit successful etch of the trenches, deposition of the barrier metal (if needed) and interconnect material.
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are used. The top-most layers of a chip have the thickest and widest and most widely separated metal layers, which make the wires on those layers have the least resistance and smallest
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288:. To extend the distance an interconnect may reach, various circuits such as buffers or restorers may be inserted at various points along a long interconnect.
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Interconnect layout are further restrained by design rules that apply to collections of interconnects. For a given area, technologies that rely on CMP have
413:, the dielectric material used to insulate adjacent interconnects, and interconnects on different levels (the inter-level dielectric ), should have a
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Initially, pure aluminum was used but by the 1970s, substrate compatibility, junction spiking and reliability concerns (mostly concerning
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553:. 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. Atlanta, USA. pp. 133–36.
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capacitors creates a rough and hilly surface, which makes it difficult to add metal interconnect layers and still maintain good yield.
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In 1998, state-of-the-art DRAM processes had four metal layers, while state-of-the-art logic processes had seven metal layers.
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Gbit DRAM typically had three layers of metal interconnect; tungsten for the first layer and aluminum for the upper layers.
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downscaling, resulted in prohibitively high resistance in interconnect structures. This forced aluminum's replacement by
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yield. The material interconnects are made from depends on many factors. Chemical and mechanical compatibility with the
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Shwartz, Geraldine Cogin (2006). Shwartz, Geraldine C.; Srikrishnan, Kris V. (eds.).
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397:) different to those of silicon, the predominant material used for interconnects is
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Structures that connect circuit elements in an integrated circuit
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In 2002, five or six layers of metal interconnect was common.
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that is as close to 1 as possible. A class of such materials,
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after the fabrication of the transistors on the substrate.
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CMOS VLSI Design: A Circuits and
Systems Perspective
297:constrained in their minimum and maximum values by
144:. Unsourced material may be challenged and removed.
673:Handbook of Semiconductor Interconnect Technology
597:Jacob, Bruce; Ng, Spencer; Wang, David (2007).
8:
549:Kim, Yong-Bin; Chen, Tom W. (15 May 1996).
355:methods. They were originally patterned by
64:Learn how and when to remove these messages
652:Harris, David Money; Weste, Neil (2011).
222:Learn how and when to remove this message
204:Learn how and when to remove this message
525:
153:"Interconnect" integrated circuits
551:Assessing Merged DRAM/Logic Technology
409:To reduce the delay penalty caused by
628:"Battle commences in 50nm DRAM arena"
430:introduced air-gap dielectric in its
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256:interconnects are formed during the
142:adding citations to reliable sources
574:"Introduction to the IC technology"
447:interconnects on different levels,
370:) forced the use of aluminum-based
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603:Memory systems: cache, DRAM, disk
499:Carbon nanotubes in interconnects
455:, so they are used for power and
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45:This article has multiple issues.
605:. Morgan Kaufmann. p. 376.
263:Interconnects are classified as
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129:needs additional citations for
53:or discuss these issues on the
656:(4 ed.). Addison Wesley.
535:"The Incredible Shrinking CPU"
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322:maintain acceptable density,
304:chemical mechanical polishing
457:clock distribution networks
310:finer geometries possible.
717:
675:(2 ed.). CRC Press.
559:10.1109/ISCAS.1996.541917
462:The process used to form
442:Multi-level interconnects
353:chemical vapor deposition
349:physical vapor deposition
405:Performance enhancements
395:monolithic microwave ICs
284:to extend its range) or
504:Interconnect bottleneck
359:, and later by various
292:Interconnect properties
278:polycrystalline silicon
274:electrical resistivity
18:Aluminium interconnect
533:DeMone, Paul (2004).
411:parasitic capacitance
626:Choi, Young (2009).
514:Parasitic extraction
509:Optical interconnect
438:technology in 2014.
384:copper interconnects
374:containing silicon,
138:improve this article
95:rewrite this article
701:Integrated circuits
415:dielectric constant
324:dummy interconnects
236:integrated circuits
586:on April 26, 2012.
572:Rencz, M. (2002).
251:substrate and the
419:Low-κ dielectrics
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194:October 2023
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136:Please help
131:verification
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103:October 2023
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93:Please help
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494:Bonding pad
361:dry etching
357:wet etching
328:dummy wires
280:(sometimes
245:fabrication
638:2019-01-08
520:References
475:In 2009, 1
253:dielectric
164:newspapers
50:improve it
338:Materials
282:silicided
56:talk page
695:Category
483:See also
286:tungsten
276:such as
344:silicon
238:(ICs),
178:scholar
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547:1998.
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376:copper
372:alloys
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428:Intel
265:local
185:JSTOR
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464:DRAM
449:vias
399:gold
326:(or
157:news
555:doi
389:In
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