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Unlike in other RISC architectures supporting both 16 and 32-bit instructions, such as ARM/Thumb or MIPS/MIPS-16, 16 and 32-bit instructions in the eSi-RISC architecture can be freely intermixed, rather than having different modes where either all 16-bit instructions or all 32-bit instructions are
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executed. This improves code density without compromising performance. The 16-bit instructions support two register operands in the lower 16 registers, whereas the 32-bit instructions support three register operands and access to all 32 registers.
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architecture. It is available in five implementations: the eSi-1600, eSi-1650, eSi-3200, eSi-3250 and eSi-3264. The eSi-1600 and eSi-1650 feature a
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data-paths, and the eSi-3264 features a mixed 32/64-bit datapath. Each of these processors is licensed as soft
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Configurable instruction set including support for integer, floating-point and fixed-point arithmetic.
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8, 16 or 32 general purpose registers, that are either 16 or 32-bits wide.
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0, 8, 16 or 32 vector registers, that are either 32 or 64-bits wide.
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supporting both memory protection and dynamic address translation.
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Up to 32 external, vectored, nested and prioritizable interrupts.
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The eSi-RISC toolchain is based on combination of a port of the
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Optional caches (Configurable size and associativity).
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The main features of the eSi-RISC architecture are:
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Configurable 16-bit, 32-bit or 32/64-bit data-path.
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51:. Unsourced material may be challenged and removed.
331:Instructions are encoded in either 16 or 32-bits.
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385:While there are many different 16 or 32-bit
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432:– Assembler, linker and binary utilities.
111:Learn how and when to remove this message
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235:data-path, while the eSi-32x0s feature
218:8/16/32 General Purpose, 8/16/32 Vector
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444:– Integrated Development Environment.
243:, suitable for integrating into both
188:Compare and branch and condition code
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514:eSi-RISC eSi-3250 Technical Overview
492:Electronics Weekly, 17 November 2009
49:adding citations to reliable sources
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625:Reduced instruction set computer
368:AXI, AHB and APB bus interfaces.
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36:needs additional citations for
396:eSi-RISC includes support for
325:-like load/store architecture.
278:format but may read better as
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16:Configurable CPU architecture
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503:EE Times, 17 November 2009
565:Electronics Weekly, 2010,
317:eSi-3250 SoC architecture
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206:User-defined instructions
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536:Design & Reuse, 2011
525:Electronics Weekly, 2013
178:Intermixed 16 and 32-bit
452:and the C++ library is
287:converting this section
576:Cambridge Network 2013
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882:Soft microprocessors
627:(RISC) architectures
45:improve this article
387:Soft microprocessor
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371:Memory mapped I/O.
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289:, if appropriate.
227:is a configurable
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589:eSi-RISC homepage
448:The C library is
426:– C/C++ compiler.
419:. This includes:
374:5-stage pipeline.
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140:16-bit/32-bit
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101:December 2009
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62: –
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56:Find sources:
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34:This article
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23:
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19:
787:Apollo PRISM
770:Discontinued
694:LatticeMico8
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474:Phoenix-RTOS
462:MicroC/OS-II
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291:Editing help
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255:Architecture
224:
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43:Please help
38:verification
35:
18:
782:AMD Am29000
438:– Debugger.
349:operations.
820:Intel i860
757:MicroBlaze
479:References
203:Extensions
194:Endianness
167:Load–store
145:Introduced
71:newspapers
60:"ESi-RISC"
815:DEC PRISM
761:PicoBlaze
713:Power ISA
456:. Ported
454:Libstdc++
404:Toolchain
377:Hardware
358:Optional
212:Registers
184:Branching
876:Category
708:OpenRISC
689:eSi-RISC
669:Blackfin
548:Archived
466:FreeRTOS
460:include
430:Binutils
412:and the
299:May 2019
241:IP cores
225:eSi-RISC
174:Encoding
132:eSi-RISC
129:Designer
124:eSi-RISC
857:PowerPC
848:PA-RISC
800:Clipper
749:Unicore
718:Renesas
640:IBM 801
633:Origins
442:Eclipse
414:Eclipse
85:scholar
843:M·CORE
834:MIPS-X
754:Xilinx
744:Sunway
734:RISC-V
725:SuperH
659:Active
458:RTOSes
450:Newlib
381:debug.
274:is in
237:32-bit
233:16-bit
154:Design
87:
80:
73:
66:
58:
853:POWER
810:CRISP
795:AVR32
792:Atmel
777:Alpha
739:SPARC
280:prose
249:FPGAs
245:ASICs
92:JSTOR
78:books
861:ROMP
829:META
824:i960
805:CR16
729:V850
721:M32R
703:MIPS
472:and
379:JTAG
366:AMBA
347:SIMD
323:RISC
276:list
247:and
163:Type
158:RISC
148:2009
137:Bits
64:news
684:AVR
679:ARM
674:ARC
436:GDB
424:GCC
417:IDE
360:MMU
229:CPU
47:by
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41:.
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