722:
A few VEX-encoded AVX blending instructions have 4 operands. To accommodate this, VEX has IS4 addressing mode, which encodes 4th operand (a vector register) in bits Imm8 of the immediate constant. Similar EVEX-encoded blend instructions have their 4th operand in a mask register. No EVEX-encoded
118:
where {k1} modifier next to the destination operand encodes the use of opmask register k1 for conditional processing and updates to destination, and {z} modifier (encoded by EVEX.z) provides the two types of masking (merging and zeroing), with merging as default when no modifier is attached.
62:
EVEX coding can address 8 operand mask registers, 16 general-purpose registers and 32 vector registers in 64-bit mode (otherwise, 8 general-purpose and 8 vector), and can support up to 4 operands.
108:
Compressed displacement (Disp8 × N), new memory addressing mode to improve encoding density of instruction byte stream; the scale factor N depends on vector length and broadcast mode.
99:
Broadcasting from source to destination for instructions that take memory vector as a source operand: the second operand is broadcast before being used in the actual operation;
65:
Like the VEX coding scheme, the EVEX prefix unifies existing opcode prefixes and escape codes, memory addressing and operand length modifiers of the x86 instruction set.
1662:
735:
introduce several new variants of the 3-byte payload in the EVEX prefix, which are used to encode
Extended GPR registers R16-R31 and new conditional instructions.
223:
Four bits R̅, X̅, B̅ and W from the VEX prefix, stored in inverted form. W expands the operand size to 64 bits or serves as an additional opcode, R expands
200:
fields, specifying either a register or a location in memory. Base-plus-index and scale-plus-index addressing require the SIB byte, which encodes 2-bit
274:
Opcode maps 5 and 6 are now supported, where the m bits are set to 101 or 110 respectively. These are used by many of the AVX512-FP16 instructions.
1688:
509:
The following table lists possible register addressing combinations (bit 4 is always zero when encoding the 16 general purpose registers):
212:
registers. Depending on the addressing mode, Disp8/Disp16/Disp32 field may follow with displacement that needs to be added to the address.
131:; the first byte is always 62h and derives from an unused opcode of the 32-bit BOUND instruction, which is not supported in 64-bit mode.
1636:
When the new EGPR registers and operand destinations can be encoded by both extended EVEX and REX2 prefixes, the latter is preferred.
259:
Three of the m bits for selecting opcode maps. Maps 1, 2, and 3 replace the existing escape codes 0Fh, 0F 38h and 0F 3Ah.
96:
Operand mask encoding: 8 new 64-bit opmask registers k0–k7 for conditional execution and merging of destination operands;
1423:
NF is status flags update suppression ("no flags") for several BMI instructions (ANDN, BEXTR, BLSI, BLSMSK, BLSR, BZHI).
102:
Direct embedded rounding control for instructions that operate on floating-point SIMD registers with rounding semantics;
29:
72:
Direct encoding of three SIMD registers (XMM, YMM, or ZMM) as source operands (MMX or x87 registers are not supported);
1706:
1653:
1726:
1731:
1632:
OF, SF, ZF, CF are overflow, sign, zero, and carry flags to test (there is no encoding for the parity flag).
47:
instruction set and allows addressing new 512-bit ZMM registers and new 64-bit operand mask registers.
1679:
1426:
ND is new data destination (NDD) flag. When ND = 1, EGPR register index is encoded by v̅ bits.
78:
Compacted SIMD prefix (66h, F2h, F3h), escape opcode (0Fh) and two-byte escape (0F38h, 0F3Ah);
256:
Two bits named p to replace operand size prefixes and operand type prefixes (66h, F2h, F3h).
305:
Bit L’ for specifying 512-bit vector length, or rounding control mode when combined with L.
20:(enhanced vector extension) and corresponding coding scheme is an extension to the 32-bit
302:
Bit b for source broadcast, rounding control (combined with L’L), or suppress exceptions.
296:
Three bits named a, specifying the operand mask register (k0–k7) for vector instructions.
112:
For example, the EVEX encoding scheme allows conditional vector addition in the form of
105:
Embedded exceptions control for floating-point instructions without rounding semantics;
997:
bits are used to encode the 32 EGPR registers. Stored in inverted form, except for B4.
1720:
1004:
specifies additional source register index, which can encode the 32 EGPR registers.
271:
along with bit B when the SIB byte is not present, which allows 32 SIMD registers.
32:. EVEX is based on, but should not be confused with the MVEX prefix used by the
1681:
Intel® Advanced
Performance Extensions (Intel® APX) Architecture Specification
216:
40:
54:, the Extended EVEX prefix redefines the semantics of several payload bits.
1655:
Intel® Xeon Phi™ Coprocessor
Instruction Set Architecture Reference Manual
982:
bits. These are the same as R̅, X̅ and B̅ bits from VEX and EVEX prefixes.
33:
44:
1707:"Intel Architecture Instruction Set Extensions Programming Reference"
185:
25:
1007:
z, m, b, L, p, a bits are the same as in the legacy EVEX prefix.
128:
90:
732:
68:
The following features are carried over from the VEX scheme:
51:
21:
81:
Less strict memory alignment requirements for memory operand
250:
specifies a second non-destructive source register operand.
89:
Extended SIMD register encoding: a total of 32 new 512-bit
127:
The EVEX coding scheme uses a code prefix consisting of 4
1687:(2 ed.). August 2023. p. 21. 355828-002US.
513:
Register addressing in 64-bit mode using EVEX prefix
188:
byte specifies one operand (always a register) with
85:
EVEX also extends VEX with additional capabilities:
299:Bit z for specifying merging mode (merge or zero).
215:The EVEX prefix retains fields introduced in the
723:instruction uses IS4 addressing mode encoding.
309:The encoding of the EVEX prefix is as follows:
192:field, and the second operand is encoded with
135:EVEX prefix in the AVX-512 instruction format
1000:Five bits named v̅, stored in inverted form.
246:Four bits named v̅, stored in inverted form.
39:The EVEX scheme is a 4-byte extension to the
8:
1430:EVEX prefix for conditional CMP and TEST:
970:bits are inversions of the REX2 prefix's R
653:Base + vectorindex × scale memory address
1629:SC bits are source condition code (SCC).
1432:
1223:
1221:EVEX extension for legacy instructions:
1013:
740:
511:
311:
133:
1661:. Sep 7, 2012. p. 42. 327364-001.
1645:
253:Bit L specifying 256-bit vector length.
263:New functions of the existing fields:
738:EVEX extension of EVEX instructions:
289:Bit V̅’ in inverted form; V’ expands
282:Bit R̅’ in inverted form; R’ expands
75:Compacted REX prefix for 64-bit mode;
7:
1011:EVEX extension of VEX instructions:
633:Base + index × scale memory address
613:Base + index × scale memory address
93:registers ZMM0–ZMM31 in 64-bit mode;
1694:from the original on Sep 10, 2023.
278:There are several new bit fields:
14:
1668:from the original on Aug 4, 2021.
1705:Intel Corporation (March 2024).
115:VADDPS zmm1 {k1}{z}, zmm2, zmm3
733:Advanced Performance Extensions
52:Advanced Performance Extensions
1:
30:instruction set architecture
1748:
43:scheme which supports the
663:
593:Register memory address
204:factor as well as 3-bit
550:General purpose, vector
716:Mask register operand
235:, and X and B expand
123:Technical description
727:Extended EVEX prefix
558:RM (if ModRM.mod=11)
514:
136:
24:(IA-32) and 64-bit
512:
267:Bit X now expands
134:
1626:
1625:
1420:
1419:
1219:
1218:
955:
954:
720:
719:
685:Register operand
573:Register operand
553:Register operand
507:
506:
182:
181:
1739:
1727:X86 instructions
1711:
1710:
1702:
1696:
1695:
1693:
1686:
1676:
1670:
1669:
1667:
1660:
1650:
1433:
1224:
1014:
741:
515:
312:
243:in the SIB byte.
137:
1747:
1746:
1742:
1741:
1740:
1738:
1737:
1736:
1717:
1716:
1715:
1714:
1704:
1703:
1699:
1691:
1684:
1678:
1677:
1673:
1665:
1658:
1652:
1651:
1647:
1642:
1619:
1613:
1607:
1601:
1575:
1569:
1563:
1525:
1519:
1513:
1507:
1501:
1404:
1378:
1372:
1366:
1360:
1354:
1348:
1342:
1316:
1310:
1304:
1298:
1292:
1203:
1177:
1171:
1165:
1159:
1153:
1147:
1141:
1124:
1118:
1112:
1106:
1100:
1094:
1088:
1082:
996:
992:
988:
981:
977:
973:
969:
965:
961:
948:
942:
936:
930:
904:
898:
892:
886:
880:
874:
868:
851:
845:
839:
833:
827:
821:
815:
809:
729:
710:
706:
702:
679:
675:
671:
667:
518:Addressing mode
500:
494:
488:
459:
453:
444:
438:
432:
426:
409:
403:
397:
125:
116:
60:
12:
11:
5:
1745:
1743:
1735:
1734:
1732:SIMD computing
1729:
1719:
1718:
1713:
1712:
1697:
1671:
1644:
1643:
1641:
1638:
1634:
1633:
1630:
1624:
1623:
1620:
1617:
1614:
1611:
1608:
1605:
1602:
1599:
1596:
1593:
1590:
1587:
1584:
1580:
1579:
1576:
1573:
1570:
1567:
1564:
1561:
1558:
1555:
1552:
1549:
1546:
1543:
1539:
1538:
1535:
1532:
1529:
1526:
1523:
1520:
1517:
1514:
1511:
1508:
1505:
1502:
1499:
1496:
1492:
1491:
1489:
1486:
1483:
1480:
1477:
1474:
1471:
1468:
1465:
1461:
1460:
1457:
1454:
1451:
1448:
1445:
1442:
1439:
1436:
1428:
1427:
1424:
1418:
1417:
1414:
1411:
1408:
1405:
1402:
1399:
1396:
1393:
1390:
1387:
1383:
1382:
1379:
1376:
1373:
1370:
1367:
1364:
1361:
1358:
1355:
1352:
1349:
1346:
1343:
1340:
1337:
1334:
1330:
1329:
1326:
1323:
1320:
1317:
1314:
1311:
1308:
1305:
1302:
1299:
1296:
1293:
1290:
1287:
1283:
1282:
1280:
1277:
1274:
1271:
1268:
1265:
1262:
1259:
1256:
1252:
1251:
1248:
1245:
1242:
1239:
1236:
1233:
1230:
1227:
1217:
1216:
1213:
1210:
1207:
1204:
1201:
1198:
1195:
1192:
1189:
1186:
1182:
1181:
1178:
1175:
1172:
1169:
1166:
1163:
1160:
1157:
1154:
1151:
1148:
1145:
1142:
1139:
1136:
1133:
1129:
1128:
1125:
1122:
1119:
1116:
1113:
1110:
1107:
1104:
1101:
1098:
1095:
1092:
1089:
1086:
1083:
1080:
1077:
1073:
1072:
1070:
1067:
1064:
1061:
1058:
1055:
1052:
1049:
1046:
1042:
1041:
1038:
1035:
1032:
1029:
1026:
1023:
1020:
1017:
1009:
1008:
1005:
998:
994:
990:
986:
983:
979:
975:
971:
967:
963:
959:
953:
952:
949:
946:
943:
940:
937:
934:
931:
928:
925:
922:
919:
916:
913:
909:
908:
905:
902:
899:
896:
893:
890:
887:
884:
881:
878:
875:
872:
869:
866:
863:
860:
856:
855:
852:
849:
846:
843:
840:
837:
834:
831:
828:
825:
822:
819:
816:
813:
810:
807:
804:
800:
799:
797:
794:
791:
788:
785:
782:
779:
776:
773:
769:
768:
765:
762:
759:
756:
753:
750:
747:
744:
728:
725:
718:
717:
714:
711:
708:
704:
700:
697:
694:
691:
687:
686:
683:
680:
677:
673:
669:
665:
662:
659:
655:
654:
651:
648:
645:
642:
639:
635:
634:
631:
628:
625:
622:
619:
615:
614:
611:
608:
605:
602:
599:
595:
594:
591:
588:
585:
582:
579:
575:
574:
571:
568:
565:
562:
559:
555:
554:
551:
548:
545:
542:
539:
535:
534:
531:
528:
525:
522:
519:
505:
504:
501:
498:
495:
492:
489:
486:
483:
480:
477:
474:
471:
468:
464:
463:
460:
457:
454:
451:
448:
445:
442:
439:
436:
433:
430:
427:
424:
421:
418:
414:
413:
410:
407:
404:
401:
398:
395:
392:
389:
386:
383:
380:
377:
373:
372:
370:
367:
364:
361:
358:
355:
352:
349:
346:
342:
341:
339:
336:
333:
330:
327:
324:
321:
318:
315:
307:
306:
303:
300:
297:
294:
287:
276:
275:
272:
261:
260:
257:
254:
251:
244:
180:
179:
177:
174:
172:
169:
166:
163:
160:
159:
156:
153:
150:
147:
144:
141:
124:
121:
114:
110:
109:
106:
103:
100:
97:
94:
83:
82:
79:
76:
73:
59:
56:
34:Knights Corner
13:
10:
9:
6:
4:
3:
2:
1744:
1733:
1730:
1728:
1725:
1724:
1722:
1708:
1701:
1698:
1690:
1683:
1682:
1675:
1672:
1664:
1657:
1656:
1649:
1646:
1639:
1637:
1631:
1628:
1627:
1621:
1615:
1609:
1603:
1597:
1594:
1591:
1588:
1585:
1582:
1581:
1577:
1571:
1565:
1559:
1556:
1553:
1550:
1547:
1544:
1541:
1540:
1536:
1533:
1530:
1527:
1521:
1515:
1509:
1503:
1497:
1494:
1493:
1490:
1487:
1484:
1481:
1478:
1475:
1472:
1469:
1466:
1464:Byte 0 (62h)
1463:
1462:
1458:
1455:
1452:
1449:
1446:
1443:
1440:
1437:
1435:
1434:
1431:
1425:
1422:
1421:
1415:
1412:
1409:
1406:
1400:
1397:
1394:
1391:
1388:
1385:
1384:
1380:
1374:
1368:
1362:
1356:
1350:
1344:
1338:
1335:
1332:
1331:
1327:
1324:
1321:
1318:
1312:
1306:
1300:
1294:
1288:
1285:
1284:
1281:
1278:
1275:
1272:
1269:
1266:
1263:
1260:
1257:
1255:Byte 0 (62h)
1254:
1253:
1249:
1246:
1243:
1240:
1237:
1234:
1231:
1228:
1226:
1225:
1222:
1214:
1211:
1208:
1205:
1199:
1196:
1193:
1190:
1187:
1184:
1183:
1179:
1173:
1167:
1161:
1155:
1149:
1143:
1137:
1134:
1131:
1130:
1126:
1120:
1114:
1108:
1102:
1096:
1090:
1084:
1078:
1075:
1074:
1071:
1068:
1065:
1062:
1059:
1056:
1053:
1050:
1047:
1045:Byte 0 (62h)
1044:
1043:
1039:
1036:
1033:
1030:
1027:
1024:
1021:
1018:
1016:
1015:
1012:
1006:
1003:
999:
984:
957:
956:
950:
944:
938:
932:
926:
923:
920:
917:
914:
911:
910:
906:
900:
894:
888:
882:
876:
870:
864:
861:
858:
857:
853:
847:
841:
835:
829:
823:
817:
811:
805:
802:
801:
798:
795:
792:
789:
786:
783:
780:
777:
774:
772:Byte 0 (62h)
771:
770:
766:
763:
760:
757:
754:
751:
748:
745:
743:
742:
739:
736:
734:
726:
724:
715:
712:
698:
695:
692:
689:
688:
684:
681:
660:
657:
656:
652:
649:
646:
643:
640:
637:
636:
632:
629:
626:
623:
620:
617:
616:
612:
609:
606:
603:
600:
597:
596:
592:
589:
586:
583:
580:
577:
576:
572:
569:
566:
563:
560:
557:
556:
552:
549:
546:
543:
540:
537:
536:
533:Common usage
532:
530:Register type
529:
526:
523:
520:
517:
516:
510:
502:
496:
490:
484:
481:
478:
475:
472:
469:
466:
465:
461:
455:
449:
446:
440:
434:
428:
422:
419:
416:
415:
411:
405:
399:
393:
390:
387:
384:
381:
378:
375:
374:
371:
368:
365:
362:
359:
356:
353:
350:
347:
345:Byte 0 (62h)
344:
343:
340:
337:
334:
331:
328:
325:
322:
319:
316:
314:
313:
310:
304:
301:
298:
295:
292:
288:
285:
281:
280:
279:
273:
270:
266:
265:
264:
258:
255:
252:
249:
245:
242:
238:
234:
230:
226:
222:
221:
220:
218:
213:
211:
207:
203:
199:
195:
191:
187:
178:
175:
173:
170:
167:
164:
162:
161:
157:
154:
151:
148:
145:
142:
139:
138:
132:
130:
122:
120:
113:
107:
104:
101:
98:
95:
92:
88:
87:
86:
80:
77:
74:
71:
70:
69:
66:
63:
57:
55:
53:
48:
46:
42:
37:
35:
31:
27:
23:
19:
1700:
1680:
1674:
1654:
1648:
1635:
1583:Byte 3 (P2)
1542:Byte 2 (P1)
1495:Byte 1 (P0)
1429:
1386:Byte 3 (P2)
1333:Byte 2 (P1)
1286:Byte 1 (P0)
1220:
1185:Byte 3 (P2)
1132:Byte 2 (P1)
1076:Byte 1 (P0)
1010:
1001:
912:Byte 3 (P2)
859:Byte 2 (P1)
803:Byte 1 (P0)
737:
730:
721:
508:
467:Byte 3 (P2)
417:Byte 2 (P1)
376:Byte 1 (P0)
308:
290:
283:
277:
268:
262:
247:
240:
236:
232:
228:
227:, B expands
224:
214:
209:
205:
201:
197:
193:
189:
183:
126:
117:
111:
84:
67:
64:
61:
49:
38:
17:
15:
682:GPR, vector
570:GPR, vector
140:# of bytes
36:processor.
18:EVEX prefix
1721:Categories
1640:References
217:VEX prefix
208:and 3-bit
647:SIB.index
627:SIB.index
587:ModRM.r/m
567:ModRM.r/m
547:ModRM.reg
1689:Archived
1663:Archived
607:SIB.base
58:Features
28:(AMD64)
661:EVEX.V’
658:NDS/NDD
641:EVEX.V’
541:EVEX.R’
45:AVX-512
966:and B̅
731:Intel
699:EVEX.a
664:EVEX.v
650:Vector
644:EVEX.X
624:EVEX.X
604:EVEX.B
584:EVEX.B
564:EVEX.B
561:EVEX.X
544:EVEX.R
186:ModR/M
171:ModR/M
168:Opcode
26:x86-64
1692:(PDF)
1685:(PDF)
1666:(PDF)
1659:(PDF)
1002:vvvvv
978:and B
618:INDEX
527:Bits
524:Bit 3
521:Bit 4
237:index
206:index
202:scale
155:4 / 1
129:bytes
50:With
1595:ND=0
989:, X̅
962:, X̅
713:Mask
638:VIDX
598:BASE
291:vvvv
248:vvvv
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239:and
210:base
196:and
184:The
165:EVEX
91:SIMD
16:The
993:, B
974:, X
630:GPR
610:GPR
590:GPR
538:REG
482:V̅’
388:R̅’
284:reg
269:r/m
233:reg
231:or
229:r/m
225:reg
198:r/m
194:mod
190:reg
41:VEX
22:x86
1723::
1622:P
1616:SC
1610:SC
1604:SC
1598:SC
1578:P
1560:X̅
1557:CF
1554:ZF
1551:SF
1548:OF
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1516:R̅
1510:B̅
1504:X̅
1498:R̅
1488:0
1459:0
1416:P
1413:0
1407:NF
1401:v̅
1398:ND
1381:P
1363:X̅
1357:v̅
1351:v̅
1345:v̅
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431:2
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351:1
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335:1
332:2
329:3
326:4
323:5
320:6
317:7
293:.
286:.
152:1
149:1
146:1
143:4
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