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chips are placed on a carrier. The distance between the chips can be chosen freely, but it is typically larger than on the silicon wafer. The gaps and the edges around the chips are now filled with a casting compound to form a wafer. After curing an artificial wafer containing a mold frame around the
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With this technology any number of additional interconnects can be realized on the package in an arbitrary distance (fan-out design). Therefore, this wafer level packaging technology can also be used for space sensitive applications, where the chip area wouldn’t be sufficient to place the required
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The eWLB technology allows the realization of chips with a high number of interconnects. The package is not created on a silicon wafer as for the classical wafer level package, but on an artificial wafer. Therefore a front-end-processed wafer is diced and the
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303:(eWLB) is a packaging technology for integrated circuits. The package interconnects are applied on an artificial wafer made of silicon chips and a casting compound.
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https://web.archive.org/web/20080517033548/http://www.ciol.com/Semicon/Tech-Watch/News-Reports/Infineon,-ASE-intro-eWLB-package-technology/131107101404/0/
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350:) the electrical connections from the chip pads to the interconnects are made in thin-film technology, as for any other classical wafer level package.
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All process steps for the generation of the package are performed on the wafer. This allows, in comparison to classical packaging technologies (e. g.
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329:) fit on the chip (so called fan-in design). Therefore only chips with a restricted number of interconnects can be packaged.
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http://www.statschippac.com/services/packagingservices/waferlevelproducts/~/media/Files/Package%20Datasheets/eWLB.ashx
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dies for carrying additional interconnect elements is created. After the build of the artificial wafer (the so-called
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It is relatively common to find packages that contain other components than their designated ones, such as diodes or
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https://web.archive.org/web/20090728202431/http://annualreport2008.infineon.com/de/template.asp?content=innovationen
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that states a
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Mechanical stress between package and board is transmitted stronger than for other package technologies
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eWLB is a further development of the classical wafer level ball grid array technology (WLB or WLP:
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and STATS ChipPAC Ltd. First components were brought into market mid of 2009 (mobile phone).
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number of interconnects at a suitable distance. The eWLB technology was developed by
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Thermal and
Electrical Characterization of eWLB (embedded Wafer Level BGA),
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Inspection and repair difficult since visual inspection is restricted
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Number of realizable interconnects on the package is not restricted
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https://safe.nrao.edu/pub/Main/EuropeanMicrowaveWeek08/WFR14-1.pdf
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High integration potential for multi-die- and stacked packages
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Electronic
Components and Technology Conference (ECTC), 2010
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personal reflection, personal essay, or argumentative essay
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http://www.wsdmag.com/Articles/ArticleID/19576/19576.html
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http://www.amkor.com/go/packaging/all-packages/cspnl/
467:"Infineon, ST and STATS Develops eWLB | TopNews"
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90:. Unsourced material may be challenged and removed.
371:Lamination of foil onto carrier (lamination tool)
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8:
532:https://ieeexplore.ieee.org/document/4147210
16:Packaging technology for integrated circuits
409:Excellent electrical and thermal properties
53:Learn how and when to remove these messages
973:List of integrated circuit packaging types
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288:Learn how and when to remove this message
270:Learn how and when to remove this message
208:Learn how and when to remove this message
150:Learn how and when to remove this message
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233:This article includes a list of general
630:(SOD-123 / SOD-323 / SOD-523 / SOD-923)
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406:Minimal lateral package size and height
387:De-bonding of carrier (de-bonding tool)
99:"Embedded wafer level ball grid array"
7:
301:Embedded wafer level ball grid array
88:adding citations to reliable sources
521:Francoise von Trapp, Nov. 30, 2009
239:it lacks sufficient corresponding
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34:This article has multiple issues.
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393:Ball drop reflow and wafer test
75:needs additional citations for
42:or discuss these issues on the
612:(DO-7 / DO-26 / DO-35 / DO-41)
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1002:in transistor packages, etc.
968:Integrated circuit packaging
403:Low cost (package and test)
374:Chip placement onto wafer (
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418:Upcoming package standard
983:Surface-mount technology
390:Flip reconstructed wafer
988:Through-hole technology
546:Seung Wook Yoon et al.
254:more precise citations.
618:(MELF / SOD-80 / LL34)
587:Semiconductor packages
519:eWLB hits the big time
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188:by rewriting it in an
978:Printed circuit board
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963:Electronic packaging
84:improve this article
316:wafer level package
1000:voltage regulators
525:2012-03-04 at the
442:Chip-scale package
360:STMicroelectronics
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336:Cross-section eWLB
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190:encyclopedic style
177:is written like a
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756:(Super-247) (SMT)
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624:(SMA / SMB / SMC)
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310:Principle eWLB
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423:Disadvantages
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366:Process Steps
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73:This article
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21:
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947:WL-CSP / WLP
817:TSOP / HTSOP
726:(DPAK) (SMT)
720:(IPAK) (SMT)
714:(TH / Panel)
708:(TH / Panel)
702:(TH / Panel)
696:(TH / Panel)
684:(TH / Panel)
654:(TH / Panel)
548:
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384:(mold press)
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327:solder balls
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82:Please help
77:verification
74:
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36:Please help
33:
865:QUIP / QUIL
252:introducing
873:Grid array
812:SOP / SSOP
764:Single row
647:SOT / TSOT
453:References
398:Advantages
343:singulated
260:March 2010
235:references
198:March 2010
140:March 2010
110:newspapers
39:improve it
927:Flip Chip
846:QIP / QIL
807:SO / SOIC
797:Flat Pack
792:DIP / DIL
771:SIP / SIL
639:3...5-pin
45:talk page
1014:Category
836:Quad row
780:Dual row
523:Archived
436:See also
356:Infineon
606:(DO-27)
594:Single
382:Molding
248:improve
184:Please
124:scholar
754:TO-274
748:TO-273
742:TO-268
736:TO-263
730:TO-262
724:TO-252
718:TO-251
712:TO-247
706:TO-220
700:TO-202
694:TO-126
622:DO-214
616:DO-213
610:DO-204
604:DO-201
237:, but
126:
119:
112:
105:
97:
905:Wafer
688:TO-92
682:TO-66
676:TO-39
670:TO-18
596:diode
378:tool)
131:JSTOR
117:books
942:UICC
885:eWLB
851:PLCC
802:MSOP
690:(TH)
678:(TH)
672:(TH)
666:(TH)
664:TO-8
660:(TH)
658:TO-5
652:TO-3
103:news
932:PoP
922:CSP
918:COG
915:COF
912:COB
895:PGA
890:LGA
880:BGA
861:QFP
856:QFN
842:LCC
827:ZIP
787:DFN
628:SOD
86:by
1016::
937:QP
358:,
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