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much hotter than
Pentium III-M processors without significant performance advantages. Its inefficiency affected not only the cooling system complexity, but also the all-important battery life. Intel went back to the drawing board for a design that would be optimally suited for this market segment. The result was a modernized P6 design called the
967:
Upon release of the
Pentium 4-M and Mobile Pentium 4, it was quickly realized that the new mobile NetBurst processors were not ideal for mobile computing. NetBurst-based processors were simply not as efficient per clock or per watt compared to their P6 predecessors. Mobile Pentium 4 processors ran
1515:
Dynamic
Acceleration Technology for some mobile Core 2 Duo processors, and Dual Dynamic Acceleration Technology for mobile Core 2 Quad processors. Dynamic Acceleration Technology allows the CPU to overclock one processor core while turning off the one. In Dual Dynamic Acceleration Technology two
1021:
The
Pentium M was the most power efficient x86 processor for notebooks for several years, consuming a maximum of 27 watts at maximum load and 4-5 watts while idle. The processing efficiency gains brought about by its modernization allowed it to rival the Mobile Pentium 4 clocked over 1 GHz
1025:
The first
Pentium M family processors ("Banias") internally support PAE but do not show the PAE support flag in their CPUID information; this causes some operating systems (primarily Linux distributions) to refuse to boot on such processors since PAE support is required in their kernels.
1511:
Dynamic Front Side Bus
Throttling (some mobile models), where the speed of the FSB is reduced in half, which by extension reduces the processor's speed in half. Thus the processor goes to a low power consumption mode called Super Low Frequency Mode that helps extend battery
1516:
cores are deactivated and two cores are overclocked. This feature is triggered when an application only uses a single core for Core 2 Duo or up to two cores for Core 2 Quad. The overclocking is performed by increasing the clock multiplier by 1.
703:
995:. L1 cache increased from predecessor's 32 KB to current 64 KB in all models. Initially 1 MB L2 cache in the Banias core, then 2 MB in the Dothan core. Dynamic cache activation by quadrant selector from sleep states.
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P6 was used within Intel's mainstream offerings from the
Pentium Pro to Pentium III, and was widely known for low power consumption, excellent integer performance, and relatively high instructions per cycle (IPC).
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Increased L2 cache size, with the L2 cache size ranging from 1 MB to 12 MB (Core 2 Duo processors use a shared L2 cache while Core 2 Quad processors having half of the total cache is shared by each core
576:
Superpipelining, which increased from
Pentium's 5-stage pipeline to 14 of the Pentium Pro and early model of the Pentium III (Coppermine), and eventually morphed into less than 10-stage pipeline of the
581:
for embedded and mobile market due to energy inefficiency and higher voltage issues that encountered in the predecessor, and then again lengthening the 10- to 12-stage pipeline back to the
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due to facing difficulty increasing clock speed while improving fabrication process can somehow negate some negative impact of higher power consumption on the deeper pipeline design.
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Micro-ops Fusion of certain sub-instructions mediated by decoding units. x86 commands can result in fewer micro-operations and thus require fewer processor cycles to complete.
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A 10- or 12-stage
Enhanced instruction pipeline that allows for higher clock speeds without lengthening the pipeline stage, reduced from 14 stage on Pentium Pro/II/III.
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While all these chips are technically derivatives of the
Pentium Pro, the architecture has gone through several radical changes since its inception.
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higher (the fastest-clocked Mobile Pentium 4 compared to the fastest-clocked Pentium M) and equipped with much more memory and bus bandwidth.
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This resulted in the interim microarchitecture for low-voltage only CPUs, part way between P6 and the following Core microarchitecture.
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and later also refuses to boot on these processors for the same reason, as they specifically require PAE support to run properly.
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Addition of global history, indirect prediction, and loop prediction to branch prediction table. Removal of local prediction.
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The P6 core was the sixth generation Intel microprocessor in the x86 line. The first implementation of the P6 core was the
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at once. The Pentium Pro was the first x86 microprocessor designed by Intel to use this technique, though the NexGen
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FSB first used in Pentium 4. The Dothan core moved to the 533 MT/s FSB, following Pentium 4's evolution.
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bus for communication with the rest of the system. Improvements relative to the Intel Core processors were:
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processor. Subsequently, more processors were released with the Core microarchitecture under Core 2,
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Single- and dual-core technology with 2 MB of shared L2 cache (restructuring processor organization)
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line of microprocessors. The successor to the Pentium M variant of the P6 microarchitecture is the
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brand names. The Core microarchitecture is Intel's final mainstream processor line to use
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brand. Single and dual-core mobile version were sold under the Core Solo, Core Duo, and
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microprocessor that was introduced in November 1995. It is frequently referred to as
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and later Intel microarchitectures featuring an integrated memory controller and a
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1653:(8th ed.). Upper Saddle River, N.J.: Pearson Prentice Hall. p. 754.
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SSE4.1 support for all Core 2 models manufactured at a 45 nm lithography.
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architecture, which was previously only offered by Prescott processors, the
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Increased FSB speed, with the FSB running at 533 MT/s or 667 MT/s.
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Other features first implemented in the x86 space in the P6 core include:
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CPU in 1995, the immediate successor to the original Pentium design (P5).
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front-side bus. With the initial Banias core, Intel adopted the 400
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598:(PAE) and a wider 36-bit address bus to support 64 GB of physical memory.
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Other new instructions: FCMOV, FCOMI/FCOMIP/FUCOMI/FUCOMIP, RDPMC, UD2.
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387:
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A 14-stage instruction pipeline that allows for higher clock speeds.
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Increased FSB speed, ranging from 533 MT/s to 1600 MT/s.
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540:
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1550:"Pentium® Pro Processor at 150 MHz, 166 MHz, 180 MHz and 200 MHz"
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31:
1555:. Intel Corporation. November 1995. p. 1. Archived from
1347:. These processors provided partial solutions to some of the
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to enable four discrete processors to share system resources.
1620:
Pentium and Pentium Pro Processors and Related Products
1575:"Defaulting to i686 for the Debian i386 architecture"
1335:
The Yonah CPU was launched in January 2006 under the
222:
Pentium II/III: 32 KB (16 KB I cache + 16 KB D cache)
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1623:. Intel Corporation. December 1995. pp. 1–10.
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62:. Unsourced material may be challenged and removed.
1451:, a derivative of P6, was launched in form of the
645:(Covington/Mendocino/Coppermine/Tualatin variants)
543:instructions into sequences of buffered RISC-like
1682:"Intel's 90nm Pentium M 755: Dothan Investigated"
1419:It has been suggested that parts of this page be
220:Pentium Pro: 16 KB (8 KB I cache + 8 KB D cache)
621:New instructions in Pentium II Deschutes core:
1741:"Pat Gelsinger talk at Stanford, Jun 7th 2006"
1770:
1672:
1670:
1343:brands, and a server version was released as
8:
1077:
695:
134:
1722:Can You Install Windows 10 on a Pentium II?
1471:, with all later Intel processors based on
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2138:
1925:
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1763:
1755:
140:
1594:"Intel's P6 Uses Decoupled Scalar Design"
122:Learn how and when to remove this message
502:. It was planned to be succeeded by the
2855:Process–architecture–optimization model
1541:
518:which in turn is also derived from P6.
2958:Computer-related introductions in 1995
1076:
694:
555:, introduced in 1994, did so earlier.
133:
1592:Gwennap, Linley (February 16, 1995).
1573:Hutchings, Ben (September 28, 2015).
7:
1530:List of Intel CPU microarchitectures
1011:Dedicated register stack management.
764:64KB (32 KB I Cache + 32 KB D cache)
588:A front-side bus using a variant of
539:P6 processors dynamically translate
60:adding citations to reliable sources
656:(a Pentium II chip in the 387 pin
25:
628:New instructions in Pentium III:
510:in 2000, but was revived for the
27:Intel processor microarchitecture
2870:Intel HD, UHD, and Iris Graphics
1410:
1364:A 12-stage instruction pipeline.
1042:(Banias/Shelton/Dothan variants)
701:
36:
1958:P6 variant (Enhanced Pentium M)
1501:last architectural installment.
1152:Architecture and classification
777:Architecture and classification
237:Architecture and classification
47:needs additional citations for
1425:Intel Core (microarchitecture)
506:microarchitecture used by the
1:
1067:P6 Variant Enhanced Pentium M
193:150 MHz to 1.40 GHz
611:, which are heavily used in
2948:Superscalar microprocessors
1729:. Section starts at 32:35.
1702:"PAE - Community Help Wiki"
1351:'s shortcomings by adding:
204:66 MHz to 133 MHz
71:"P6" microarchitecture
2974:
1268:Products, models, variants
1070:
903:Products, models, variants
688:
596:Physical Address Extension
407:Products, models, variants
2938:Intel x86 microprocessors
1647:The Intel Microprocessors
1328:
960:
700:
630:Streaming SIMD Extensions
590:Gunning transceiver logic
473:
139:
2943:Intel microarchitectures
1282:Pentium Dual-Core Series
484:is the sixth-generation
232:256 KB to 2048 KB (Xeon)
1719:This Does Not Compute.
1493:Support for the 64-bit
1211:Physical specifications
832:Physical specifications
567:out-of-order completion
436:Pentium III Xeon Series
295:Physical specifications
2953:X86 microarchitectures
1953:P6 variant (Pentium M)
1449:Core microarchitecture
1447:On July 27, 2006, the
1073:Yonah (microprocessor)
516:Core microarchitecture
427:Pentium II Xeon Series
166:; 28 years ago
1601:Microprocessor Report
1078:P6 Enhanced Pentium M
1034:Banias/Dothan variant
1005:Extensions 2 support.
613:compiler optimization
563:Speculative execution
494:, implemented by the
1644:Brey, Barry (2009).
1168:Instruction set
1121:533 MT/s to 667 MT/s
1110:1.06 GHz to 2.33 GHz
793:Instruction set
748:400 MT/s to 533 MT/s
685:P6 Variant Pentium M
654:Pentium II Overdrive
482:P6 microarchitecture
345:(A1, A2, B0, C0, D0)
253:Instruction set
56:improve this article
1083:General information
1079:
737:600 MHz to 2.26 GHz
710:General information
697:
156:General information
136:
2752:Sandy Bridge-based
1921:Microarchitectures
1906:Microarchitectures
1562:on April 12, 2016.
950:Enhanced Pentium M
625:, FXSAVE, FXRSTOR.
433:Pentium III Series
430:Celeron III Series
418:Pentium Pro Series
277:(Pentium II/III/M)
2925:
2924:
2838:
2837:
2211:
2210:
2130:
2129:
1680:(July 21, 2004).
1678:Shimpi, Anand Lal
1660:978-0-13-502645-8
1445:
1444:
1391:T2060/T2080/T2130
1389:Pentium Dual-Core
1341:Pentium Dual-Core
1333:
1332:
1158:Microarchitecture
965:
964:
783:Microarchitecture
772:512 KB to 2048 KB
602:Register renaming
492:microarchitecture
478:
477:
424:Pentium II Series
421:Celeron II Series
243:Microarchitecture
132:
131:
124:
106:
16:(Redirected from
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2757:Ivy Bridge-based
2348:8/16-bit databus
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2139:
2135:Current products
1926:
1786:Intel processors
1779:
1772:
1765:
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1748:
1747:on June 3, 2011.
1743:. Archived from
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1406:
1285:Core Solo Series
1279:Celeron M Series
1080:
923:Pentium M Series
920:Celeron M Series
705:
698:
679:Pentium III Xeon
545:micro-operations
528:
352:(A1, B1, C1, D0)
230:128 KB to 512 KB
174:
172:
171:November 1, 1995
167:
164:November 1, 1995
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2921:
2850:Tick–tock model
2834:
2778:
2767:Broadwell-based
2658:Extreme Edition
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1969:
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1581:(Mailing list).
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1288:Core Duo Series
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1247:
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1206:
1146:
1075:
1069:
1036:
976:Design Overview
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866:
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669:Pentium II Xeon
639:
571:pipeline stalls
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439:
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282:(Pentium III/M)
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2569:NetBurst-based
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2376:
2375:32-bit databus
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2357:16-bit databus
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2019:
2009:
2008:
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1996:
1995:
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1982:
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1324:Support status
1321:
1320:
1315:
1311:
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1305:
1301:
1300:
1296:
1295:
1293:
1292:
1291:Xeon LV Series
1289:
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1270:
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1071:Main article:
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1019:
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989:
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962:
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956:Support status
953:
952:
947:
943:
942:
937:
933:
932:
928:
927:
925:
924:
921:
918:
917:EP80579 Series
915:
911:
909:
905:
904:
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899:
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739:
738:
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724:
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719:
718:March 12, 2003
716:
712:
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706:
689:Main article:
686:
683:
682:
681:
676:
671:
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661:
651:
646:
638:
637:P6 based chips
635:
634:
633:
626:
619:
616:
605:
599:
593:
586:
574:
549:execution unit
529:
524:
476:
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469:Support status
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2798:
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2781:
2773:
2772:Skylake-based
2770:
2768:
2765:
2763:
2762:Haswell-based
2760:
2758:
2755:
2753:
2750:
2748:
2747:Nehalem-based
2745:
2744:
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2512:Original i586
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2109:
2108:Goldmont Plus
2106:
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2018:
2015:
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1630:1-55512-251-5
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1396:
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1384:Core Solo/Duo
1382:
1379:
1376:
1375:
1372:Yonah variant
1371:
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115:
104:
101:
97:
94:
90:
87:
83:
80:
76:
73: –
72:
68:
67:Find sources:
61:
57:
51:
50:
45:This article
43:
39:
34:
33:
30:
19:
2216:Discontinued
2053:Cypress Cove
2012:Sandy Bridge
1947:
1745:the original
1735:
1726:
1721:
1714:
1705:
1696:
1685:
1646:
1639:
1619:
1613:
1604:
1600:
1587:
1579:debian-devel
1578:
1568:
1557:the original
1544:
1519:
1446:
1436:October 2021
1433:
1367:
1355:SSE3 Support
1334:
1145:1 MB to 2 MB
1024:
1020:
975:
974:
966:
696:P6 Pentium M
609:instructions
557:
538:
531:
520:
499:
481:
479:
146:Die shot of
118:
109:
99:
92:
85:
78:
66:
54:Please help
49:verification
46:
29:
2065:Golden Cove
2060:Willow Cove
2041:Cannon Lake
1706:Ubuntu Help
1395:Xeon LV/ULV
1329:Unsupported
1304:Predecessor
1217:Transistors
1147:2 MB (Xeon)
1096:Performance
993:L1/L2 cache
982:Quad-pumped
961:Unsupported
936:Predecessor
914:A100 Series
838:Transistors
723:Performance
674:Pentium III
649:Pentium Pro
534:Pentium Pro
496:Pentium Pro
474:Unsupported
449:Predecessor
301:Transistors
287:(Pentium M)
179:Performance
2932:Categories
2860:Intel GPUs
2574:Core-based
2338:(external
2226:oriented (
2096:Silvermont
2048:Sunny Cove
2017:Ivy Bridge
1800:Processors
1536:References
1397:(Sossaman)
1380:400 series
1318:Intel Core
1183:Extensions
1106:clock rate
1001:Streaming
894:Socket 479
808:Extensions
733:clock rate
664:Pentium II
398:Socket 479
393:Socket 370
268:Extensions
189:clock rate
82:newspapers
2912:Codenames
2825:StrongARM
2663:Dual-Core
2636:Dual-Core
2547:Dual-Core
2517:OverDrive
2466:A100/A110
2459:OverDrive
2253:pre-x86 (
2120:Gracemont
2029:Broadwell
1687:AnandTech
1499:Pentium 4
1402:Successor
1378:Celeron M
1349:Pentium M
1314:Successor
1308:Pentium M
1051:A100/A110
1046:Pentium M
1040:Celeron M
1028:Windows 8
970:Pentium M
946:Successor
691:Pentium M
579:Pentium M
512:Pentium M
508:Pentium 4
459:Successor
148:Deschutes
112:June 2013
2917:Larrabee
2795:iAPX 432
2730:11th gen
2725:10th gen
2564:P6-based
2454:RapidCAD
2196:14th gen
2191:13th gen
2186:12th gen
2181:11th gen
2176:10th gen
2103:Goldmont
2091:Saltwell
2005:Westmere
1965:NetBurst
1911:Chipsets
1524:See also
1259:Socket M
1228:(C0, D0)
1142:L2 cache
1088:Launched
940:NetBurst
863:(C0, D0)
856:(B0, C0)
849:(B1, B2)
769:L2 cache
715:Launched
658:Socket 8
527:Features
504:NetBurst
463:NetBurst
383:Socket 8
331:(B0, C0)
324:(B0, B1)
227:L2 cache
161:Launched
2907:Stratix
2843:Related
2805:Itanium
2720:9th gen
2715:8th gen
2710:7th gen
2705:6th gen
2700:5th gen
2695:4th gen
2690:3rd gen
2685:2nd gen
2680:1st gen
2643:Pentium
2626:Celeron
2586:Tolapai
2507:Pentium
2490:(1998)
2488:Celeron
2379:80387DX
2371:80387SX
2166:Pentium
2161:Celeron
2115:Tremont
2086:Bonnell
2036:Skylake
2024:Haswell
2000:Nehalem
1899:Itanium
1815:Pentium
1810:Celeron
1727:YouTube
1473:Nehalem
1465:Celeron
1461:Pentium
1429:Discuss
1345:Xeon LV
1299:History
1061:CE 3100
1056:EP80579
991:Larger
931:History
643:Celeron
444:History
376:Sockets
169: (
96:scholar
2830:XScale
2600:64-bit
2596:x86-64
2501:(2004)
2398:32-bit
2361:80C187
2354:(1980)
2327:(1982)
2321:(1982)
2315:(1982)
2309:(1979)
2303:(1978)
2292:16-bit
2286:Early
2278:(1977)
2272:(1974)
2266:(1972)
2245:(1974)
2239:(1971)
2147:64-bit
2143:x86-64
1993:Penryn
1979:64-bit
1975:x86-64
1934:32-bit
1657:
1627:
1508:pair).
1495:x86-64
1453:Core 2
1273:Models
1252:Socket
1173:x86-16
1118:speeds
908:Models
887:Socket
847:130 nm
798:x86-16
745:speeds
583:Core 2
412:Models
388:Slot 1
350:130 nm
343:180 nm
336:250 nm
329:250 nm
322:250 nm
316:350 nm
310:500 nm
258:x86-16
201:speeds
98:
91:
84:
77:
69:
2902:PIIXs
2783:Other
2581:Quark
2394:IA-32
2384:80487
2366:80287
2325:80286
2319:80188
2313:80186
2255:8-bit
2228:4-bit
1930:IA-32
1894:Quark
1793:Lists
1651:(PDF)
1597:(PDF)
1560:(PDF)
1553:(PDF)
1512:life.
1423:into
1421:moved
1237:Cores
1226:65 nm
1224:151M
1177:IA-32
1137:64 KB
1133:cache
1126:Cache
1101:Max.
872:Cores
861:65 nm
859:151M
854:90 nm
852:144M
802:IA-32
760:cache
753:Cache
728:Max.
607:CMOV
553:Nx586
541:IA-32
486:Intel
361:Cores
327:9.5M
320:7.5M
314:7.5M
308:5.5M
262:IA-32
216:cache
209:Cache
184:Max.
103:JSTOR
89:books
2897:ICHs
2892:SCHs
2887:PCHs
2820:i960
2815:i860
2810:RISC
2800:EPIC
2790:CISC
2742:Xeon
2670:Core
2609:Atom
2559:Xeon
2554:Core
2471:Atom
2429:i486
2407:i386
2400:x86)
2352:8087
2340:FPUs
2307:8088
2301:8086
2276:8085
2270:8080
2264:8008
2243:4040
2237:4004
2203:Xeon
2171:Core
2156:Atom
1988:Core
1936:x86)
1889:Xeon
1852:Core
1805:Atom
1655:ISBN
1625:ISBN
1607:(2).
1463:and
1457:Xeon
1337:Core
1202:SSE3
1198:SSE2
1091:2006
1003:SIMD
999:SSE2
986:MT/s
845:77M
823:SSE2
565:and
500:i686
480:The
348:44M
341:28M
338:(B0)
334:19M
285:SSE2
150:core
75:news
18:I686
2880:Arc
2865:GMA
2614:SoC
2532:III
2522:Pro
2481:SoC
2444:DX4
2439:DX2
2417:376
2336:x87
2288:x86
2224:BCD
2078:ULV
2075:x86
1830:III
1820:Pro
1481:DMI
1479:or
1477:QPI
1469:FSB
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1244:1-2
1194:SSE
1190:MMX
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819:SSE
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758:L1
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730:CPU
623:MMX
489:x86
280:SSE
275:MMX
214:L1
199:FSB
186:CPU
58:by
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2476:CE
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2422:EX
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1877:i9
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1867:i5
1862:i3
1825:II
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