274:, which is less than its predecessor, the zEC12. The PU chip can have six, seven or eight cores (or "processor units" in IBM's parlance) enabled depending on configuration. The PU chip is packaged in a single-chip module, a departure from IBM's previous mainframe processors, which were mounted on large
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shared by three PU chips. The two SC chips add a total of 960 MB L4 cache per drawer. The SC chips also handle the communications between the sets of three PU chips and to other drawers. The SC chip is manufactured on the same 22 nm process as the z13 PU chips, has 15 metal layers, measures
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The z13 processor supports a new vector facility architecture. It adds 32 vector registers, each 128 bits wide; the existing 16 floating-point registers are overlaid on the new vector registers. The new architecture adds over 150 new instructions to operate on data in vector registers, including
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The IBM z13 is the last z
Systems server to support running an operating system in ESA/390 architecture mode. However, all 24-bit and 31-bit problem-state application programs originally written to run on the ESA/390 architecture are unaffected by this change.
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A compute drawer consists of two clusters. Each cluster comprises three PU chips and one
Storage Controller chip (SC chip). Even though each PU chip has 64 MB L3 cache shared by the 8 cores and other on-die facilities the SC chip adds 480 MB off-die
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The instruction pipeline has an instruction queue that can fetch 6 instructions per cycle; and issue up to 10 instructions per cycle. Each core has a private 96
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fabrication plant (formerly IBM's own plant). IBM stated that it is the world's fastest microprocessor and is about 10% faster than its predecessor the
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28.4 × 23.9 mm (678 mm), consists of 7.1 billion transistors and runs at half the clock frequency of the CP chip.
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instruction cache, and a private 2 MB L2 data cache. In addition, there is a 64 MB shared L3 cache implemented in
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integer, floating-point, and string data types. The z13 implementation includes two independent
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as well as two new Gen 3 PCIe controllers for accessing host channel adapters and peripherals.
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in general single-threaded computing, but significantly more when doing specialized tasks.
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The
Processor Unit chip (PU chip) has an area of 678 mm and contains 3.99 billion
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512:"Accommodate functions for the z13 server to be discontinued on future servers"
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358:-like configuration to recover from memory faults. The z13 also includes two
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424:"IBM Launches z13 -- Most Powerful & Secure System Ever Built"
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410:"IBM Systems Get Breathing Room With Globalfoundries Chip Deal"
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538:. 2015 IEEE International Solid-State Circuits Conference.
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536:22nm Next-Generation IBM System z Microprocessor
575:"IBM z Systems Processor Optimization Primer"
466:"IBM z13 and IBM z13s Technical Introduction"
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430:(Press release). 2015-01-13. Archived from
27:2015 64-bit mainframe microprocessor by IBM
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558:"z/Architecture Principles of Operation"
347:The z13 chip has on board multi-channel
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614:Computer-related introductions in 2015
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303:, and new features such as two-way
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375:units to operate on vector data.
487:"IBM Renews Mainframe With z13"
299:. It has facilities related to
257:. It is fabricated using IBM's
136:Architecture and classification
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305:simultaneous multithreading
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544:10.1109/ISSCC.2015.7062930
609:IBM mainframe technology
534:J. Warnock; et al.
281:The cores implement the
18:IBM z13 (microprocessor)
235:East Fishkill, New York
163:Physical specifications
331:L1 instruction cache
321:logical partitioning
301:transactional memory
265:silicon on insulator
152:Instruction set
142:Technology node
604:IBM microprocessors
434:on January 14, 2015
268:fabrication process
227:mainframe computers
59:Common manufacturer
36:General information
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412:. 20 October 2014.
379:Storage Controller
276:multi-chip modules
352:memory controller
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105:96 KB instruction
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317:cryptography
294:out-of-order
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290:superscalar
255:transistors
249:Description
189:Predecessor
107:128 KB data
75:Performance
49:Designed by
598:Categories
497:2015-01-14
438:2020-05-05
393:References
259:22 nm
222:for their
89:5 GHz
85:clock rate
199:Successor
119:2 MB data
386:L4 cache
349:DDR3 RAM
338:L2 cache
297:pipeline
218:made by
126:L3 cache
121:per core
114:L2 cache
109:per core
41:Launched
288:with a
184:History
360:GX bus
131:shared
578:(PDF)
561:(PDF)
469:(PDF)
342:eDRAM
239:zEC12
214:is a
193:zEC12
169:Cores
146:22 nm
129:64 MB
101:cache
94:Cache
80:Max.
373:SIMD
356:RAID
319:and
309:SIMD
283:CISC
262:CMOS
210:The
44:2015
583:IBM
540:doi
517:IBM
473:IBM
272:GHz
224:z13
220:IBM
212:z13
203:z14
99:L1
82:CPU
66:IBM
53:IBM
31:z13
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