236:
132:
124:
27:
1630:
On x86 PCs, many video card BIOS and system BIOS will reprogram the second counter for their own use. Reprogramming typically happens during video mode changes, when the video BIOS may be executed, and during system management mode and power saving state changes, when the system BIOS may be executed.
360:
Latch the count for a given timer. The next read will, rather than returning the counter value at the moment of the read, return the counter value at the moment of the latch command. After the read completes, later reads will return the current counter. When the latch command is used, the mode and
1073:
from the GATE input signal. Status byte format. Bit 7 allows software to monitor the current state of the OUT pin. Bit 6 indicates when the count can be read; when this bit is 1, the counting element has not yet been loaded and cannot be read back by the processor. Bits 5 through 0 are the same as
341:
The next two bits (if not 00) select the format that will be used for subsequent read/write access to the counter register. This is commonly set to a mode where accesses alternate between the least-significant and most-significant bytes. One difference between the 8253 and 8254 is that the former
1262:
The one-shot is retriggerable, hence OUT will remain low for N CLK pulses after any trigger. The one-shot pulse can be repeated without rewriting the same count into the counter. GATE has no effect on OUT. If a new count is written to the
Counter during a oneshot pulse, the current one-shot is not
1537:
After receiving the
Control Word and COUNT, the output will be set high. Once the device detects a rising edge on the GATE input, it will start counting. When the counter reaches 0, the output will go low for one clock cycle – after that it will become high again, to repeat the cycle on the next
1230:
The OUT pin is set low after the
Control Word is written, and counting starts one clock cycle after the COUNT is programmed. OUT remains low until the counter reaches 0, at which point OUT will be set high until the counter is reloaded or the Control Word is written. The counter wraps around to
1634:
As stated above, Channel 0 is implemented as a counter. Typically, the initial value of the counter is set by sending bytes to the
Control, then Data I/O Port registers (the value 36h sent to port 43h, then the low byte to port 40h, and port 40h again for the high byte). The counter counts
1274:
Like other modes, the counting process will start the next clock cycle after COUNT is sent. OUT will then remain high until the counter reaches 1, and will go low for one clock pulse. The following cycle, the count is reloaded, OUT goes high again, and the whole process repeats itself.
1669:
According to a 2002 Microsoft document, "because reads from and writes to this hardware require communication through an IO port, programming it takes several cycles, which is prohibitively expensive for the OS. Because of this, the aperiodic functionality is not used in practice."
1258:
After writing the
Control Word and initial count, the Counter is armed. A trigger results in loading the Counter and setting OUT low on the next CLK pulse, thus starting the one-shot pulse. An initial count of N will result in a one-shot pulse N CLK cycles in duration.
1647:. The counter then resets to its initial value and begins to count down again. The fastest possible interrupt frequency is a little over a half of a megahertz. The slowest possible frequency, which is also the one normally used by computers running
326:
To initialize the counters, the microprocessor must write a control word (CW) in this register. This can be done by setting proper values for the pins of the Read/Write Logic block and then by sending the control word to the Data/Bus Buffer block.
1254:
OUT will be initially high. OUT will go low on the Clock pulse following a trigger to begin the one-shot pulse, and will remain low until the
Counter reaches zero. OUT will then go high and remain high until the CLK pulse after the next trigger.
1590:, and to make TV output possible, this oscillator had to run at a multiple of the NTSC color subcarrier frequency. This frequency, divided by 2 (the largest divisor the 8253 is capable of) produces the ≈18.2 Hz timer interrupt used in
1226:
Mode 0 is used for the generation of accurate time delay under software control. In this mode, the counter will start counting from the initial COUNT value loaded into it, down to 0. Counting rate is equal to the input clock frequency.
196:
The 8253 is described in the 1980 Intel "Component Data
Catalog" publication. The 8254, described as a superset of the 8253 with higher clock speed ratings, has a "preliminary" data sheet in the 1982 Intel "Component Data Catalog".
342:
had one internal bit which affected both reads and writes, so if the format was set to 2-byte, a read of the lsbyte would cause a following write to be directed to the msbyte. The 8254 used separate bits for reads and writes.
1068:
When setting the PIT, the microprocessor first sends a control message, then a count message to the PIT. The counting process will start after the PIT has received these messages, and, in some cases, if it detects the rising
1546:
The 8253 was used in IBM PC compatibles since their introduction in 1981. In modern times, this PIT is not included as a separate chip in an x86 PC. Rather, its functionality is included as part of the motherboard chipset's
1522:
After
Control Word and COUNT is loaded, the output will remain high until the counter reaches zero. The counter will then generate a low pulse for 1 clock cycle (a strobe) – after that the output will become high again.
1235:
internally and continues counting, but the OUT pin never changes again. The Gate signal should remain active high for normal counting. If Gate goes low, counting is suspended, and resumes when it goes high again.
364:(8254 only) Latch the status and/or count for multiple timers. This allows multiple simultaneous latch commands using a bitmap. Also, the current channel configuration may be read back in addition to the count.
1203:
The D3, D2, and D1 bits of the control word set the operating mode of the timer. There are 6 modes in total; for modes 2 and 3, the D3 bit is ignored, so the missing modes 6 and 7 are aliases for modes 2 and 3.
1217:
Modes 2 and 3: GATE low forces OUT high immediately (without waiting for a clock pulse) and resets the counter (on the next clock falling edge). When GATE goes high again, counting restarts from the beginning.
1472:
1349:
1437:
219:
There is military version of Intel M8253 with the temperature range of -55 °C to +125 °C which it also have ±10% 5V power tolerance. The available 82C53 CMOS version was outsourced to
211:
typically implement full 8254 compatibility for backward compatibility and interoperability. The Read Back command being a vital I/O feature for interoperability with multicore CPUs and GPUs.
261:
Data bus buffer contains the logic to buffer the data bus between the microprocessor and the internal registers. It has 8 input pins, usually labelled as D7..D0, where D7 is the
177:-0 (the highest priority hardware interrupt). Timer Channel 1 is assigned to DRAM refresh (at least in early models before the 80386). Timer Channel 2 is assigned to the
1613:
1214:
Modes 1 and 5: The rising edge of GATE starts counting. GATE may go low without affecting counting, but another rising edge will restart the count from the beginning.
246:
The timer has three counters, numbered 0 to 2. Each channel can be programmed to operate in one of six modes. Once programmed, the channels operate independently.
1512:
1492:
1402:
1371:
1263:
affected unless the counter is retriggered. In that case, the
Counter is loaded with the new count and the oneshot pulse continues until the new count expires.
200:
The 8254 is implemented in HMOS and has a "Read Back" command not available on the 8253, and permits reading and writing of the same counter to be interleaved.
253:
input) and "GATE" – and one pin, "OUT", for data output. The three counters are 16-bit down counters independent of each other, and can be easily read by the
1662:, first for the low byte, and then for the high byte. However, in free-running counter applications such as in the x86 PC, it is necessary to first write a
1609:
2008:
1936:
1655:
operating systems, the BIOS accumulates the number of INT 8 calls that it receives in real mode address 0040:006c, which can be read by a program.
1710:
302:
Operation mode of the PIT is changed by setting the above hardware signals. For example, to write to the
Control Word Register, one needs to set
162:-processors, but were later used in x86 compatible systems. The 825x chips, or an equivalent circuit embedded in a larger chip, are found in all
1927:
1751:
1978:
1815:
1787:
Intel Corporation, "Focus Components: Military Intelligence: Timers, EPROMs, Leadless Chip Carriers", Solutions, March/April 1983, Page 12.
174:
1278:
The time between the high pulses depends on the preset count in the counter's register, and is calculated using the following formula:
1381:
This mode is similar to mode 2. However, the duration of the high and low clock pulses of the output will be different from mode 2.
1207:
All modes are sensitive to the GATE input, with GATE high causing normal operation, but the effects of GATE low depend on the mode:
110:
1937:
Intel Corporation, "8253 Programmable Interval Timer", Intel 8080 Microcomputer Systems User's Manual, September 1975, page 5-169
48:
1597:
In the original IBM PCs, Counter 0 is used to generate a timekeeping interrupt. Counter 1 is used to trigger the refresh of
1442:
1284:
1957:
1796:
Intel Corporation, "NewsBit: Intel Licenses Oki on CMOS Version of Several Products", Solutions, July/August 1984, Page 1.
1407:
322:) to the device. It defines how each channel of the PIT logically works. Each access to these ports takes about 1 μs.
1805:
Ashborn, Jim; "Advanced Packaging: A Little Goes A Long Way", Intel Corporation, Solutions, January/February 1986, Page 2
91:
1666:
command for the desired channel to the control register, so that both bytes read will belong to one and the same value.
1271:
In this mode, the device acts as a divide-by-n counter, which is commonly used to generate a real-time clock interrupt.
63:
2003:
1841:
148:
44:
1969:
1582:
frequency which comes from dividing the system clock (14.31818 MHz) by 12. This is a holdover of the very first
1551:. In a modern chipset, this change may show up in the form of noticeably faster access to the PIT's registers in the
1617:
70:
37:
1248:
1998:
1548:
254:
208:
77:
1583:
1900:
220:
1717:
59:
1627:
On PCs the address for timer0 (chip) is at port 40h..43h and the second timer1 (chip) is at 50h..53h.
774:
352:. (BCD counting almost never used and may not be implemented properly in emulators or southbridges.)
349:
334:). The decoding is somewhat complex. Most values set the parameters for one of the three counters:
331:
262:
1663:
1873:
1949:
1819:
1640:
1621:
1587:
1923:
1767:
1747:
1631:
This prevents any serious alternative uses of the timer's second counter on many x86 systems.
1534:
This mode is similar to mode 4. However, the counting process is triggered by the GATE input.
163:
1239:
The first byte of the new count when loaded in the count register, stops the previous count.
338:
The most significant two bits (if not 11) select the counter register the command applies to.
204:
1973:
1961:
235:
318:
The control word register contains the programmed information which will be sent (by the
84:
1497:
1477:
1404:
is the number loaded into the counter (the COUNT message), the output will be high for
1387:
1356:
1211:
Modes 0 and 4: Counting is suspended while GATE is low, and resumed while GATE is high.
319:
123:
1992:
1983:
1658:
As a timer counts down, its value can also be read directly by reading its I/O port
294:
224:
131:
1917:
151:(PITs), which perform timing and counting functions using three 16-bit counters.
1555:
1070:
348:
The least significant bit selects whether the counter will operate in binary or
26:
1954:
1919:
The Undocumented PC: A Programmer's Guide to I/O, CPUs, and Fixed Memory Areas
1602:
1579:
178:
167:
159:
155:
1878:
1652:
1848:
1966:
843:
Next read of selected counters will read back latched status, then count
533:
Latch counter value. Next read of counter will read snapshot of value.
135:
Intel 8253 programmable interval timer. Intel 8254 has the same pinout.
1526:
GATE low suspends the count, which resumes when GATE goes high again.
1648:
1591:
345:
The next three bits select the mode that the counter will operate in.
330:
The control word register contains 8 bits, labeled D7..D0 (D7 is the
1651:
or compatible operating systems, is about 18.2 Hz. Under these
1561:
All PC compatibles operate the PIT at a clock rate of 105/88 = 1.193
1679:
250:
234:
130:
122:
1685:
1598:
1576:
185:
1644:
1552:
20:
901:
Next read of selected counters will read back latched status
223:. The available package version of Intel 82C54 was in 28-pin
1192:
Counter mode bits, as defined for the control word register
872:
Next read of selected counters will read back latched count
1608:
Newer motherboards include additional counters through the
1586:
PCs – they derived all necessary frequencies from a single
268:
Read/write logic has 5 pins, which are listed below. The "
1816:"8254/82C54: Introduction to Programmable Interval Timer"
593:
2×Read/2xWrite low byte then high byte of counter value
188:
logic) variant handles up to 10 MHz clock signals.
1467:{\displaystyle \left\lfloor {n \over 2}\right\rfloor }
1353:
Note that the values in the COUNT register range from
1344:{\displaystyle f_{\rm {input}} \over f_{\rm {output}}}
963:
Do nothing (latch count and/or status on no counters)
1514:
is odd, the extra half-cycle is spent with OUT high.
1500:
1480:
1445:
1410:
1390:
1359:
1288:
1601:
memory. Counter 2 is used to generate tones via the
1432:{\displaystyle \left\lceil {n \over 2}\right\rceil }
1874:"Guidelines For Providing Multimedia Timer Support"
51:. Unsourced material may be challenged and removed.
1506:
1486:
1466:
1431:
1396:
1365:
1343:
930:Do nothing (latch nothing on any or all counters)
735:Mode 5: Hardware Triggered Strobe (Retriggerable)
173:In PC compatibles, Timer Channel 0 is assigned to
1901:Guidelines For Providing Multimedia Timer Support
1074:the last bits written to the control register.
1922:(second, illustrated ed.). Addison-Wesley.
1614:Local Advanced Programmable Interrupt Controller
154:The 825x family was primarily designed for the
1711:"Intel 82C54 CHMOS Programmabe Interval Timer"
756:Counter is a 16-bit binary counter (0–65535)
529:
8:
573:Read/Write high byte of counter value only
1979:8254/82C54 Programmable Interval Timer FAQ
1610:Advanced Configuration and Power Interface
553:Read/Write low byte of counter value only
1499:
1479:
1450:
1444:
1415:
1409:
1389:
1358:
1319:
1318:
1294:
1293:
1286:
1222:Mode 0 (000): Interrupt on terminal count
249:Each counter has two input pins – "CLK" (
203:Modern PC compatibles, either when using
111:Learn how and when to remove this message
1984:Programmable Interval Timer – OSDev Wiki
1742:Deepali A. Godse; Atul P. Godse (2007).
1705:
1703:
1701:
1076:
643:Mode 1: Hardware Retriggerable One-Shot
367:
1697:
1530:Mode 5 (101): Hardware Triggered Strobe
1518:Mode 4 (100): Software Triggered Strobe
1373:to 1; the register never reaches zero.
1251:. GATE input is used as trigger input.
1062:Read-back command applies to counter 0
1029:Read-back command applies to counter 1
996:Read-back command applies to counter 2
1746:. Technical Publications. p. 74.
227:of sampling at first quarter of 1986.
272:" denotes X is an active low signal.
7:
620:Mode 0: Interrupt on Terminal Count
479:Set mode of Counter 2 (at port 42h)
356:However, there are two other forms:
49:adding citations to reliable sources
1955:Overview of the Intel 8253 PIT chip
1818:. Intel Corporation. Archived from
1620:. The CPU itself also provides the
1377:Mode 3 (X11): square wave generator
1247:In this mode 8253 can be used as a
1243:Mode 1 (001): programmable one shot
1474:counts. Thus, the period will be
1335:
1332:
1329:
1326:
1323:
1320:
1307:
1304:
1301:
1298:
1295:
1281:Value to be loaded into counter =
712:Mode 4: Software Triggered Strobe
14:
1058:
1025:
992:
959:
926:
897:
868:
839:
810:
676:
653:
508:
2009:Input/output integrated circuits
221:Oki Electronic Industry Co., Ltd
25:
1594:and related operating systems.
36:needs additional citations for
1967:Intel 8253 complete datasheets
814:Read-back command (8254 only)
512:Read-back command (8254 only)
166:and Soviet computers like the
16:Programmable interval timer IC
1:
1682:provides a programmable timer
1267:Mode 2 (X10): rate generator
455:
435:
149:programmable interval timers
1916:Gilluwe, Frank Van (1997).
1716:(datasheet). Archived from
361:BCD status are not changed.
2025:
1618:High Precision Event Timer
1191:
1175:
1163:
1151:
1141:
1061:
1028:
995:
962:
929:
900:
871:
842:
772:
755:
734:
711:
688:
665:
642:
619:
592:
572:
552:
532:
511:
478:
458:
438:
1960:29 September 2011 at the
1612:(ACPI), a counter on the
1185:
1182:
1180:
1176:The counter is being set
1173:
1161:
1149:
1139:
1085:
1082:
781:
766:
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376:
373:
1972:20 February 2012 at the
1939:from bitsaver.org in PDF
1775:pdf.datasheetcatalog.com
1744:Advanced Microprocessors
1249:monostable multivibrator
666:Mode 2: Rate Generator
369:8253/8254 control word
184:The Intel 82c54 (c for
1643:(IRQ 0, INT 8) to the
1639:to zero, then sends a
1508:
1488:
1468:
1433:
1398:
1367:
1345:
459:Set mode of Counter 1
439:Set mode of Counter 0
243:
136:
128:
1842:"MSM 82c53 Datasheet"
1538:rising edge of GATE.
1509:
1489:
1469:
1434:
1399:
1368:
1346:
773:Counter is a 4-digit
238:
134:
126:
1498:
1478:
1443:
1439:counts, and low for
1408:
1388:
1357:
1285:
1164:Counter can be read
775:binary-coded decimal
689:Mode 3: Square Wave
290:: chip select signal
45:improve this article
1882:. 20 September 2002
1822:on 22 November 2016
1079:
370:
2004:IBM PC compatibles
1854:on 6 December 2014
1641:hardware interrupt
1622:Time Stamp Counter
1542:IBM PC programming
1504:
1484:
1464:
1429:
1394:
1363:
1313:
1086:Short Description
1077:
530:— x —
377:Short Description
368:
244:
164:IBM PC compatibles
137:
129:
1929:978-0-201-47950-8
1753:978-81-89411-33-6
1507:{\displaystyle n}
1487:{\displaystyle n}
1458:
1423:
1397:{\displaystyle n}
1366:{\displaystyle n}
1341:
1196:
1195:
1078:8254 status word
1066:
1065:
777:counter (0–9999)
239:Block diagram of
121:
120:
113:
95:
2016:
1933:
1903:
1898:
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1891:
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1887:
1870:
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1847:. Archived from
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1234:
1080:
1047:
1042:
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105:
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53:
29:
21:
2024:
2023:
2019:
2018:
2017:
2015:
2014:
2013:
1989:
1988:
1974:Wayback Machine
1962:Wayback Machine
1950:82C54 Datasheet
1946:
1930:
1915:
1912:
1910:Further reading
1907:
1906:
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1494:counts, and if
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1379:
1355:
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1314:
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1269:
1245:
1232:
1224:
1201:
1199:Operation modes
1131:
1126:
1121:
1116:
1111:
1106:
1101:
1099:
1094:
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1045:
1040:
1012:
1007:
979:
974:
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941:
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42:
30:
17:
12:
11:
5:
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2012:
2011:
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2001:
1999:Intel chipsets
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1944:External links
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1734:
1723:on 3 June 2015
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1588:quartz crystal
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320:microprocessor
300:
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291:
285:
284:: write signal
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33:
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24:
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13:
10:
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1152:Out pin is 1
1146:
1145:
1142:Out pin is 0
1136:
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314:=0, A1=A0=1.
296:
295:address lines
292:
286:
280:
278:: read signal
274:
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62: –
61:
57:
56:Find sources:
50:
46:
40:
39:
34:This article
32:
28:
23:
22:
19:
1918:
1896:
1884:. Retrieved
1877:
1868:
1856:. Retrieved
1849:the original
1836:
1824:. Retrieved
1820:the original
1810:
1801:
1792:
1783:
1774:
1762:
1743:
1737:
1725:. Retrieved
1718:the original
1668:
1659:
1657:
1636:
1633:
1629:
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1607:
1596:
1560:
1545:
1536:
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107:
98:
88:
81:
74:
67:
60:"Intel 8253"
55:
43:Please help
38:verification
35:
18:
1858:26 November
1727:26 November
1565: MHz,
1556:I/O address
1549:southbridge
1083:Bit #/Name
374:Bit #/Name
209:southbridge
127:Intel C8253
1993:Categories
1886:13 October
1692:References
1624:facility.
1603:PC speaker
1580:colorburst
241:Intel 8253
179:PC speaker
168:Vector-06C
156:Intel 8080
141:Intel 8253
71:newspapers
1879:Microsoft
1826:21 August
1653:real mode
1970:Archived
1958:Archived
1674:See also
1616:, and a
1461:⌋
1448:⌊
1426:⌉
1413:⌈
1384:Suppose
761:counter
744:counter
717:counter
694:counter
671:counter
648:counter
625:counter
602:counter
578:counter
558:counter
538:counter
521:counter
293:A0, A1:
231:Features
215:Variants
207:CPUs or
101:May 2024
1768:"Intel"
1570:⁄
1558:space.
1183:format
1095:Status
764:format
747:format
720:format
697:format
674:format
651:format
628:format
605:format
470:format
450:format
430:format
192:History
85:scholar
1926:
1750:
1649:MS-DOS
1592:MS-DOS
1233:0xFFFF
1102:count
1093:Output
1046:status
1013:status
980:status
947:status
798:status
496:status
87:
80:
73:
66:
58:
1852:(PDF)
1845:(PDF)
1771:(PDF)
1721:(PDF)
1714:(PDF)
1680:LAPIC
1664:latch
1660:twice
1186:mode
1041:count
1008:count
975:count
942:count
793:count
767:mode
750:mode
587:mode
567:mode
547:mode
491:count
473:mode
453:mode
433:mode
251:clock
92:JSTOR
78:books
1924:ISBN
1888:2010
1860:2012
1828:2011
1748:ISBN
1729:2012
1686:HPET
1637:down
1599:DRAM
1577:NTSC
1575:the
1189:BCD
1132:BCD
1112:RW0
1107:RW1
1100:null
1071:edge
732:BCD
709:BCD
686:BCD
663:BCD
640:BCD
617:BCD
590:BCD
570:BCD
550:BCD
476:BCD
456:BCD
436:BCD
419:BCD
399:RW0
394:RW1
389:SC2
384:SC1
310:=1,
306:=0,
225:PLCC
186:CMOS
160:8085
147:are
145:8254
143:and
139:The
64:news
1645:CPU
1584:CGA
1553:x86
1127:M0
1122:M1
1117:M2
1053:C1
1050:C2
1023:C0
1017:C2
990:C0
987:C1
924:C0
921:C1
918:C2
895:C0
892:C1
889:C2
866:C0
863:C1
860:C2
837:C0
834:C1
831:C2
808:C0
805:C1
802:C2
506:C0
503:C1
500:C2
414:M0
409:M1
404:M2
350:BCD
332:MSB
263:MSB
255:CPU
205:SoC
175:IRQ
47:by
1995::
1876:.
1773:.
1700:^
1605:.
1563:18
1171:1
1159:0
1147:1
1137:0
1130:D0
1125:D1
1120:D2
1115:D3
1110:D4
1105:D5
1098:D6
1091:D7
1059:x
1056:1
1037:1
1034:1
1026:x
1020:1
1004:1
1001:1
993:x
984:1
971:1
968:1
960:x
957:0
954:0
951:0
938:1
935:1
927:x
915:1
912:1
909:1
906:1
898:x
886:0
883:1
880:1
877:1
869:x
857:1
854:0
851:1
848:1
840:x
828:0
825:0
822:1
819:1
811:x
789:1
786:1
770:1
753:0
729:1
726:0
723:1
706:0
703:0
700:1
683:1
680:1
677:x
660:0
657:1
654:x
637:1
634:0
631:0
614:0
611:0
608:0
584:1
581:1
564:0
561:1
544:1
541:0
527:0
524:0
509:x
487:1
484:1
467:0
464:1
447:1
444:0
427:0
424:0
417:D0
412:D1
407:D2
402:D3
397:D4
392:D5
387:D6
382:D7
312:WR
308:RD
304:CS
288:CS
282:WR
276:RD
257:.
181:.
170:.
1932:.
1890:.
1862:.
1830:.
1777:.
1756:.
1731:.
1572:3
1568:1
1502:n
1482:n
1456:2
1453:n
1421:2
1418:n
1392:n
1361:n
1336:t
1333:u
1330:p
1327:t
1324:u
1321:o
1316:f
1308:t
1305:u
1302:p
1299:n
1296:i
1291:f
270:X
265:.
158:/
114:)
108:(
103:)
99:(
89:·
82:·
75:·
68:·
41:.
Text is available under the Creative Commons Attribution-ShareAlike License. Additional terms may apply.
