20:
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89:, etc.). As a result of its CMOS technology and low clock speeds, 8 MHz for the Harris HM-6100A, it had relatively low power consumption, less than 100 mW at 10 V/2 MHz, and could be operated from a single supply over the wide range of 4–11 V. Thus, it could be used in high reliability
332:
There is no stack pointer; subroutines return to their callers by jumping back into the main code, typically by storing the return address in the first word of the subroutine itself. This makes it difficult to have subroutines in ROM, these must find some other location to store the address. This was
96:
The 6100 was available to military specification, and since it was dual sourced by
Intersil and Harris, it was used in some military products as a low power alternative to the 8080, 6800 etc. Although it had a very simple instruction set and architecture, it was eminently suitable for use in embedded
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Conditionals in the 6100 allow only the next instruction to be skipped. Branches are constructed with a conditional and a following jump. There is only one maskable interrupt. When the interrupt is tripped, the CPU stores the current PC in 0000, and then starts executing from 0001. The interrupt can
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The 6100 has a 12-bit data/address bus, limiting RAM to only 4K words, or 6 KB. Memory references are 7-bit, offset either from address 0, or from the PC page base address (obtained by setting the seven least significant bits of PC to zero). Memory could be expanded using the optional 6102
353:
and thus expanded memory to 32K words (48 KB) in the same way that the PDP-8/E expanded the PDP-8. The 6102 has two internal registers, IFR (instruction field register) and DFR (data field register), that offset the 4K page when the CPU accesses memory.
419:
Family
Sampler Kit, and with the 6960 Sampler PC Board, a single-board system including the IM6100 CPU, IM6101 PIE, the IM6312 ODT (Octal Debugging Technique) Monitor ROM, three 256×4 CMOS RAMs and a IM6403
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sold the integrated circuits commercially through 1982 as the IM6100 family. It was not priced competitively, and the offering failed. The
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the IM6102 MEDIC (Memory
Extension, DMA Controller, Interval Timer), which converts an IM6100 into something resembling a PDP-8/E's CPU
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329:), and MQ (Multiplier Quotient). All two-operand instructions read the AC and MQ and write back to the AC.
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without the need for any significant thermal management, if the rest of the system was also CMOS.
58:. The Intersil 6100 was introduced in the second quarter of 1975, and the Harris version in 1976.
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500:
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the IM6100 CPU, which implements a straight-8 (basic PDP-8 without memory mapping hardware)
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instruction set, along with a range of peripheral support and memory ICs developed by
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Intersil (1981). "8. Digital §Microprocessor, Peripherals, Development System".
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A selection of these components were offered as parts of the
Intersil 6801
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The 6100 family was used in a number of commercial products, including the
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the IM6101 PIE (Programmable
Interface Element) is a basic PDP-8 I/O port
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Intersil offered a variety of related chips to support 6100 systems:
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be disabled or enabled using the IOF and ION (or SKON) instructions.
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for a more complete discussion). It has three primary registers: PC (
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systems that had previously used discrete logic circuits and even
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The basic 6100 was later upgraded to the 6120, with the 6102
507:(7). Byte Publications: 88 – via the Internet Archive.
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motorised rotary switches or relay-based logic controllers.
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in the mid-1970s. It was sometimes referred to as the
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the IM6312 (12 Kbit, 1024×12) mask programmable
313:The 6100 is a 12-bit CPU that closely emulates the
116:. The Intersil 6100 was first used, according to
69:technologies used by most of its contemporaries (
375:the IM6103 PIO (Parallel Input-Output Port), and
333:not a problem for the original PDP-8, where all
451:. AntiqueTech.com. 2009-04-21. Archived from
8:
471:
469:
449:"The Explosion 1975-1976 » AntiqueTech"
134:in 1981 cemented the doom of the "CMOS-8s".
542:"Intersil 6100 microprocessor architecture"
398:the IM6551 and IM6561 (1 Kbit, 256×4)
404:the IM6512 (768 Bit, 64x12) SRAM, and
386:Intersil also offered compatible sizes of
482:, (Poster), Digital Equipment Corporation
440:
152:
7:
61:The 6100 family was produced using
479:Family Tree of Digital's Computers
14:
501:"The First of the 12-Bit Micros?"
382:- basic PDP-8 I/O devices on ICs.
358:Versions and supporting hardware
349:support chip, which added three
50:. Since it was also produced by
112:'s first attempt to produce a
1:
549:"IM6100 CMOS Family Sampler"
65:rather than the bipolar and
499:Staff writer (March 1976).
54:, it was also known as the
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571:12-bit microprocessors
527:. pp. 8-77–8-211.
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35:implementation of the
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476:Bell, Gordon (1980),
378:the IM6402 or IM6403
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22:
16:12-bit microprocessor
124:Pacific Cyber/Metrix
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126:'s PCM-12 in 1976.
554:2014-10-02 at the
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52:Harris Corporation
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429:memory controller
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154:IM6100 registers
149:of Intersil 6100.
114:personal computer
31:is a single-chip
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91:embedded systems
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264:Program counter
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536:External links
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231:Main registers
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56:Harris HM-6100
33:microprocessor
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455:on 2017-07-03
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303:ink register
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29:Intersil 6100
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457:. Retrieved
453:the original
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286:Status flags
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544:, CPU World
335:main memory
327:accumulator
138:Description
547:Intersil,
486:2017-06-19
459:2017-06-19
435:References
431:built-in.
254:ultiplier
243:cumulator
521:Data Book
48:CMOS-PDP8
565:Category
552:Archived
258:uotient
128:Intersil
44:Intersil
292:
280:ounter
276:rogram
106:DECmate
132:IBM PC
108:line,
37:12-bit
525:(PDF)
319:PDP-8
317:(See
315:PDP-8
99:Ledex
40:PDP-8
505:Byte
422:UART
417:CMOS
409:PROM
400:SRAM
390:and
380:UART
339:core
119:Byte
87:9900
83:6800
79:6502
75:8080
67:NMOS
63:CMOS
27:The
392:ROM
388:RAM
270:PC
248:MQ
237:AC
147:Die
110:DEC
71:Z80
567::
503:.
468:^
424:.
394::
341:.
241:AC
85:,
81:,
77:,
73:,
462:.
411:.
301:L
296:L
278:C
274:P
256:Q
252:M
219:0
214:1
209:2
204:3
199:4
194:5
189:6
184:7
179:8
174:9
169:0
164:1
Text is available under the Creative Commons Attribution-ShareAlike License. Additional terms may apply.
