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of code. During the execution of such a critical section, all interrupt handlers that cannot execute safely within a critical section are blocked (they save the minimum amount of information required to restart the interrupt handler after all critical sections have exited). So the interrupt latency
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by having the hardware wait a programmable minimum amount of time between each interrupt it generates. Interrupt rate limiting reduces the amount of time spent servicing interrupts, allowing the processor to spend more time doing useful work. Exceeding this time results in a soft (recoverable) or
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design that improve interrupt latency will decrease throughput and increase processor utilization. Techniques that increase throughput may increase interrupt latency and increase processor utilization. Lastly, trying to reduce processor utilization may increase interrupt latency and decrease
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Maximum interrupt latency is largely determined by the methods an OS uses for interrupt handling. For example, most processors allow programs to disable interrupts, putting off the execution of interrupt handlers, in order to protect
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Also, there are many other methods hardware may use to help lower the requirements for shorter interrupt latency in order to make a given interrupt latency tolerable in a situation. These include buffers, and
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refers to the delay between the start of an
Interrupt Request (IRQ) and the start of the respective Interrupt Service Routine (ISR). For many operating systems, devices are serviced as soon as the device's
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for a blocked interrupt is extended to the end of the critical section, plus any interrupts with equal and higher priority that arrived while the block was in place.
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Lin, Feng; Ashley, David T.; Burke, Michael J.; Heymann, Michael (1999). "A Hybrid System
Solution of the Interrupt Latency Compatibility Problem".
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Advanced interrupt controllers implement a multitude of hardware features in order to minimize the overhead during
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Modern hardware also implements interrupt rate limiting. This helps prevent
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is well known for producing a huge amount of interrupt latency jitter.
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and the effective interrupt latency. These include features like:
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Many computer systems require low interrupt latencies, especially
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in the interrupt latency, which can drastically affect the
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circuit and its configuration. They can also affect the
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There is usually a trade-off between interrupt latency,
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machinery in real-time. Sometimes these systems use a
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Minimum interrupt latency is largely determined by the
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Minimum jitter through non-interruptible instructions
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112:Learn how and when to remove this message
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383:Yiu, Joseph (2016-04-01).
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309:Inter-processor interrupt
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325:Non-maskable interrupt
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298:Ethernet flow control
257:Sleep-on-exit feature
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353:References
303:IEEE 802.3
279:live-locks
159:throughput
153:Background
145:, and the
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16:See also:
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315:Interrupt
183:real-time
102:June 2019
449:Category
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393:Archived
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