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Pumping (computer systems)

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259: 22: 121: 182:(FSB) of a computer system. This works by transmitting data at the rising edge, peak, falling edge, and trough of each clock cycle. Intel computer systems (and others) use this technology to reach effective FSB speeds of 1600 MT/s (million transfers per second), even though the FSB clock speed is only 400 MHz (cycles per second). A 193:
E6600 processor is listed as 2.4 GHz with a 1066 MHz FSB. The FSB is known to be quad-pumped, so its clock frequency is 1066/4 = 266 MHz. Therefore, the CPU multiplier is 2400/266, or 9×. The DDR2 RAM that it is compatible with is known to be double-pumped and to have an
300: 39: 202:) the type of RAM that is appropriate is quadruple 266 MHz, or DDR2-1066 (PC2-8400 or PC2-8500, depending on the manufacturer's labeling.). 224:"Understanding System Memory and CPU speeds: A layman's guide to the Front Side Bus (FSB), Part Three: Double Pumping, Quad Pumping, and DDR" 86: 58: 293: 105: 194:
Input/Output Bus twice that of the true FSB frequency (effectively transferring data 4 times a clock cycle), so to run the system
324: 65: 43: 223: 72: 286: 178:, the data was transmitted on both rising and falling edges. However, quad-pumping has been used for a while for the 54: 319: 32: 125: 79: 160: 266: 183: 169: 129: 270: 199: 179: 133: 258: 313: 186:
in the CPU then multiplies the FSB clock by a factor in order to get the CPU speed.
167:, transmitted data on only the rising edge of the clock signal. With the advent of 148: 147:
systems, is an informal term for transmitting a data signal more than one time per
231: 21: 190: 175: 144: 120: 164: 119: 15: 274: 46:. Unsourced material may be challenged and removed. 294: 8: 217: 215: 301: 287: 106:Learn how and when to remove this message 211: 7: 255: 253: 44:adding citations to reliable sources 14: 222:Lee Penrod (September 21, 2007). 257: 20: 55:"Pumping" computer systems 31:needs additional citations for 159:Early types of system memory ( 1: 273:. You can help Knowledge by 341: 252: 325:Computer hardware stubs 172:synchronous dynamic RAM 137: 124:A comparison between 123: 143:, when referring to 40:improve this article 234:on January 18, 2016 138: 282: 281: 267:computer hardware 184:phase-locked loop 116: 115: 108: 90: 332: 303: 296: 289: 261: 254: 244: 243: 241: 239: 230:. Archived from 219: 170:double data rate 130:double data rate 126:single data rate 111: 104: 100: 97: 91: 89: 48: 24: 16: 340: 339: 335: 334: 333: 331: 330: 329: 320:Computer memory 310: 309: 308: 307: 250: 248: 247: 237: 235: 221: 220: 213: 208: 157: 112: 101: 95: 92: 49: 47: 37: 25: 12: 11: 5: 338: 336: 328: 327: 322: 312: 311: 306: 305: 298: 291: 283: 280: 279: 262: 246: 245: 210: 209: 207: 204: 200:front-side bus 180:front-side bus 156: 153: 134:quad data rate 114: 113: 28: 26: 19: 13: 10: 9: 6: 4: 3: 2: 337: 326: 323: 321: 318: 317: 315: 304: 299: 297: 292: 290: 285: 284: 278: 276: 272: 269:article is a 268: 263: 260: 256: 251: 233: 229: 228:directron.com 225: 218: 216: 212: 205: 203: 201: 197: 196:synchronously 192: 187: 185: 181: 177: 173: 171: 166: 162: 154: 152: 150: 146: 142: 135: 131: 127: 122: 118: 110: 107: 99: 88: 85: 81: 78: 74: 71: 67: 64: 60: 57: –  56: 52: 51:Find sources: 45: 41: 35: 34: 29:This article 27: 23: 18: 17: 275:expanding it 264: 249: 236:. Retrieved 232:the original 227: 195: 189:Example: A 188: 168: 158: 149:clock signal 140: 139: 117: 102: 93: 83: 76: 69: 62: 50: 38:Please help 33:verification 30: 163:), such as 314:Categories 206:References 191:Core 2 Duo 66:newspapers 176:DDR SDRAM 96:June 2015 155:Overview 145:computer 238:May 24, 141:Pumping 80:scholar 132:, and 82:  75:  68:  61:  53:  265:This 198:(see 165:SDRAM 87:JSTOR 73:books 271:stub 240:2017 59:news 174:or 161:RAM 42:by 316:: 226:. 214:^ 151:. 128:, 302:e 295:t 288:v 277:. 242:. 136:. 109:) 103:( 98:) 94:( 84:· 77:· 70:· 63:· 36:.

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single data rate
double data rate
quad data rate
computer
clock signal
RAM
SDRAM
double data rate
DDR SDRAM
front-side bus
phase-locked loop
Core 2 Duo
front-side bus


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