482:, for suspending and resuming load address tracking, respectively. While the tracking is suspended, any loads from memory will not be added to the transaction read set. This means that, unless these memory locations were added to the transaction read or write sets outside the suspend region, writes at these locations by other threads will not cause transaction abort. Suspending load address tracking for a portion of code within a transactional region allows to reduce the amount of memory that needs to be tracked for read-write conflicts and therefore increase the probability of successful commit of the transaction.
582:
According to Intel 64 and IA-32 Architectures
Software Developer's Manual from May 2020, Volume 1, Chapter 2.5 Intel Instruction Set Architecture And Features Removed, HLE has been removed from Intel products released in 2019 and later. RTM is not documented as removed. However, Intel 10th generation
512:
Independent research points into
Haswell’s transactional memory most likely being a deferred update system using the per-core caches for transactional data and register checkpoints. In other words, Haswell is more likely to use the cache-based transactional memory system, as it is a much less risky
326:
Restricted
Transactional Memory (RTM) is an alternative implementation to HLE which gives the programmer the flexibility to specify a fallback code path that is executed when a transaction cannot be successfully executed. Unlike HLE, RTM is not backward compatible with processors that do not support
571:
as a mitigation for TSX Asynchronous Abort (TAA) vulnerability. Earlier mitigation for memory ordering issue was removed. By default, with the updated microcode, the processor would still indicate support for RTM but would always abort the transaction. System software is able to detect this mode of
504:
Haswell's L1 data cache has an associativity of eight. This means that in this implementation, a transactional execution that writes to nine distinct locations mapping to the same cache set will abort. However, due to micro-architectural implementations, this does not mean that fewer accesses to
533:
In August 2014, Intel announced that a bug exists in the TSX/TSX-NI implementation on
Haswell, Haswell-E, Haswell-EP and early Broadwell CPUs, which resulted in disabling the TSX/TSX-NI feature on affected CPUs via a microcode update. The bug was fixed in F-0 steppings of the vPro-enabled Core
470:
TSX/TSX-NI Suspend Load
Address Tracking (TSXLDTRK) is an instruction set extension that allows to temporarily disable tracking loads from memory in a section of code within a transactional region. This feature extends HLE and RTM, and its support in the processor must be detected separately.
578:
instruction, preventing detection of TSX/TSX-NI by applications. System software may also enable the "Unsupported
Software Development Mode", where RTM is fully active, but in this case RTM usage may be subject to the issues described earlier, and therefore this mode should not be enabled on
496:
Intel's TSX/TSX-NI specification describes how the transactional memory is exposed to programmers, but withholds details on the actual transactional memory implementation. Intel specifies in its developer's and optimization manuals that
Haswell maintains both read-sets and write-sets at the
144:
of transactional code regions. The hardware monitors multiple threads for conflicting memory accesses, while aborting and rolling back transactions that cannot be successfully completed. Mechanisms are provided for software to detect and handle failed transactions.
1239:
BDM53 E-0: X, F-0:, Status: Fixed ERRATA: Intel TSX Instructions Not
Available. 1. Applies to Intel Core M-5Y70 processor. Intel TSX is supported on Intel Core M-5Y70 processor with Intel vPro Technology. Intel TSX is not supported on other processor
56:
support, speeding up execution of multi-threaded software through lock elision. According to different benchmarks, TSX/TSX-NI can provide around 40% faster applications execution in specific workloads, and 4–5 times more database
1017:
882:
Under a complex set of internal timing conditions and system events, software using the Intel TSX/TSX-NI (Transactional
Synchronization Extensions) instructions may observe unpredictable system behavior.
309:
HLE allows optimistic execution of a critical section by skipping the write to a lock, so that the lock appears to be free to other threads. A failed transaction results in execution restarting from the
811:
1161:
The whole "CPU does the fine grained locks" is based upon tagging the L1 (64 B) cachelines and there are 512 of them to be specific (64 x 512 = 32 KB). There is only one "lock tag" per cacheline.
1284:
The
October 2018 microcode update also disabled the HLE instruction prefix of Intel TSX and force all RTM transactions to abort when operating in Intel SGX mode or System Management Mode (SMM).
591:
client processors, which were released in 2020, do not support TSX/TSX-NI, including both HLE and RTM. Engineering versions of Comet Lake processors were still retaining TSX/TSX-NI support.
594:
In Intel Architecture Instruction Set Extensions Programming Reference revision 41 from October 2020, a new TSXLDTRK instruction set extension was documented. It was first included in
548:
processors. As a result of a microcode update, HLE support was disabled in the affected CPUs, and RTM was mitigated by sacrificing one performance counter when used outside of Intel
1021:
1276:
864:"Desktop 4th Generation Intel Core Processor Family, Desktop Intel Pentium Processor Family, and Desktop Intel Celeron Processor Family: Specification Update (Revision 014)"
1415:
148:
In other words, lock elision through transactional execution uses memory transactions as a fast path where possible, while the slow (fallback) path is still a normal lock.
894:
863:
462:
instruction that returns whether the processor is executing a transactional region. This instruction is supported by the processor if it supports HLE or RTM or both.
2603:
2165:
117:
Support for TSX/TSX-NI emulation is provided as part of the Intel Software Development Emulator. There is also experimental support for TSX/TSX-NI emulation in a
80:
do not support TSX/TSX-NI. In August 2014, Intel announced a bug in the TSX/TSX-NI implementation on current steppings of Haswell, Haswell-E, Haswell-EP and early
1070:
1331:
1220:
1394:
1352:
1310:
1252:
2004:
1968:
1858:
497:
granularity of a cache line, tracking addresses in the L1 data cache of the processor. Intel also states that data conflicts are detected through the
2046:
509:, the L1 cache is shared between the two threads on the same core, so operations in a sibling logical processor of the same core can cause evictions.
1506:
1099:
1565:
1196:
556:). System software would have to either effectively disable RTM or update performance monitoring tools not to use the affected performance counter.
1373:
691:
538:
106:(KASLR) on all major operating systems. In 2021, Intel released a microcode update that disabled the TSX/TSX-NI feature on CPU generations from
2091:
1148:
993:
1713:
765:
1277:"Performance Monitoring Impact of Intel® Transactional Synchronization Extension Memory Ordering Issue White Paper, June 2021, Revision 1.4"
937:
1512:
2158:
1135:
The processor tracks both the read-set addresses and the write-set addresses in the first level data cache (L1 cache) of the processor.
836:
2259:
2177:
2076:
2034:
628:
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2419:
2295:
2185:
1820:
1808:
1803:
1798:
1793:
1459:
607:
354:
instruction explicitly aborts a transaction. Transaction failure redirects the processor to the fallback code path specified by the
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2189:
595:
559:
In June 2021, Intel published a microcode update that further disables TSX/TSX-NI on various Xeon and Core processor models from
2623:
327:
it. For backward compatibility, programs are required to detect support for RTM in the CPU before using the new instructions.
133:(HLE) is an instruction prefix-based interface designed to be backward compatible with processors without TSX/TSX-NI support.
2151:
2061:
1851:
1297:"Intel® Transactional Synchronization Extensions (Intel® TSX) Memory and Performance Monitoring Update for Intel® Processors"
663:
Tomas Karnagel; Roman Dementiev; Ravi Rajwar; Konrad Lai; Thomas Legler; Benjamin Schlegel; Wolfgang Lehner (February 2014).
744:
2618:
2116:
568:
81:
2628:
2436:
2096:
1963:
1558:
537:
The bug was found and then reported during a diploma thesis in the School of Electrical and Computer Engineering of the
49:
2613:
2051:
584:
560:
545:
514:
107:
73:
1296:
2394:
2358:
1907:
1761:
522:
506:
521:(MOB) for the same purpose, possibly also providing multi-versioned transactional memory that is more amenable to
2608:
2509:
2465:
2320:
1844:
1484:
588:
549:
401:
Set if another logical processor conflicted with a memory address that was part of the transaction that aborted.
1259:
2071:
1071:"Intel 64 and IA-32 Architectures Software Developer's Manual Combined Volumes: 1, 2A, 2B, 2C, 3A, 3B, and 3C"
76:
microarchitecture. Haswell processors below 45xx as well as R-series and K-series (with unlocked multiplier)
790:
2515:
2444:
2215:
2210:
2111:
2101:
2029:
1551:
58:
664:
2633:
2283:
2132:
2056:
1922:
1897:
553:
692:"Performance Evaluation of Intel Transactional Synchronization Extensions for High Performance Computing"
629:"Performance Evaluation of Intel Transactional Synchronization Extensions for High-Performance Computing"
2485:
2308:
2106:
1958:
1771:
1688:
579:
production systems. On some systems RTM can't be re-enabled when SGX is active. HLE is always disabled.
141:
699:
129:
TSX/TSX-NI provides two software interfaces for designating code regions for transactional execution.
2526:
2497:
2242:
491:
53:
665:"Improving In-Memory Database Index Performance with Intel Transactional Synchronization Extensions"
2479:
2376:
2370:
1825:
1786:
1781:
1776:
1766:
1599:
92:
2570:
2564:
2558:
2039:
1465:
77:
27:
Extension to the x86 instruction set architecture that adds hardware transactional memory support
1683:
17:
2449:
2247:
2227:
2014:
1973:
1455:
1221:"Intel Core M Processor Family. Specification Update. December 2014. Revision 003. 330836-003"
912:
2411:
2024:
1917:
1447:
137:(RTM) is a new instruction set interface that provides greater flexibility for programmers.
393:
If set, the transaction may succeed on a retry. This bit is always clear if bit 0 is set.
2174:
2081:
1902:
639:
498:
913:"Intel sticks another nail in the coffin of TSX with feature-disabling microcode update"
1708:
1490:
1444:
Proceedings of the 2014 ACM symposium on Principles of distributed computing - PODC '14
962:
69:
1197:"Intel Disables TSX Instructions: Erratum Found in Haswell, Haswell-E/EP, Broadwell-Y"
1123:
720:
505:
the same set are guaranteed to never abort. Additionally, in CPU configurations with
2597:
1927:
1723:
1703:
1698:
95:
1469:
1932:
916:
544:
In October 2018, Intel disclosed a TSX/TSX-NI memory ordering issue found in some
1531:
2473:
1937:
627:
Richard M. Yoo; Christopher J. Hughes; Konrad Lai; Ravi Rajwar (November 2013).
564:
111:
84:
CPUs, which resulted in disabling the TSX/TSX-NI feature on affected CPUs via a
1174:
2019:
1978:
1892:
1718:
1658:
1653:
1609:
298:
prefix hint can be used both with the instructions listed above, and with the
207:
prefix hint can only be used with the following instructions with an explicit
99:
2143:
2503:
2425:
2266:
2203:
2198:
2086:
2066:
1942:
1912:
1693:
1663:
1451:
1200:
1149:"Making Sense of the Intel Haswell Transactional Synchronization eXtensions"
997:
994:"Making Sense of the Intel Haswell Transactional Synchronization eXtensions"
350:
instructions mark the start and the end of a transactional code region; the
85:
1046:
721:"Benchmarks: Haswell's TSX and Memory Transaction Throughput (HLE and RTM)"
98:
was found by abusing the way TSX/TSX-NI handles transactional faults (i.e.
1537:
1887:
1882:
1733:
1728:
2388:
2271:
2254:
2237:
2220:
1637:
1500:
165:
1523:
1416:"Intel® Architecture Instruction Set Extensions Programming Reference"
837:"Errata prompts Intel to disable TSX in Haswell, early Broadwell CPUs"
2491:
2454:
2314:
1756:
1751:
1604:
1594:
1518:
1474:. Software-based improvements to hardware lock-elision in Intel TSX.
1836:
1496:
963:"Supporting Intel Transactional Synchronization Extensions in QEMU"
895:"Breaking Kernel Address Space Layout Randomization with Intel TSX"
425:
Set if an abort occurred during execution of a nested transaction.
2400:
2338:
2278:
1988:
1983:
1867:
1589:
1519:
Web Resources about Intel Transactional Synchronization Extensions
1227:
941:
870:
812:"Intel Comparison Table of Haswell Pentium, i3, i5, and i7 models"
573:
103:
65:
1543:
1524:
x86, microcode: BUG: microcode update that changes x86_capability
2382:
2364:
2350:
2344:
2332:
2326:
2232:
2009:
1815:
1632:
1527:
1100:"Intel 64 and IA-32 Architectures Optimization Reference Manual"
118:
2147:
1840:
1547:
156:
Hardware Lock Elision (HLE) adds two new instruction prefixes,
2299:
1574:
314:-prefixed instruction, but treating the instruction as if the
46:
68:
in February 2012, and debuted in June 2013 on selected Intel
1094:
1092:
1090:
766:"Transactional memory going mainstream with Intel Haswell"
938:"Fun with Intel Transactional Synchronization Extensions"
39:
Transactional Synchronization Extensions New Instructions
444:
argument (only valid if bit 0 set, otherwise reserved).
858:
856:
517:
or later may combine this cache-based approach with
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2184:
2125:
1997:
1951:
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1744:
1676:
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1625:
1618:
1582:
1446:. Software-improved hardware lock elision, p. 212.
572:operation and mask support for TSX/TSX-NI from the
513:implementation choice. On the other hand, Intel's
358:instruction, with the abort status returned in the
192:prefixes are ignored on instructions for which the
1395:"Intel® Core™ i7-1068NG7 Processor specifications"
1332:"Intel® Core™ i9-10980HK Processor specifications"
830:
828:
114:, as a mitigation for discovered security issues.
1353:"Intel® Core™ i7-10810U Processor specifications"
1311:"Intel® Core™ i9-10900K Processor specifications"
1065:
1063:
200:are valid, thus enabling backward compatibility.
987:
985:
492:Transactional memory § Available implementations
1374:"Intel® Xeon® W-1290P Processor specifications"
2422:(ABM: 2007, BMI1: 2012, BMI2: 2013, TBM: 2012)
2159:
1852:
1559:
1040:
1038:
8:
1047:"Analysis of Haswell's Transactional Memory"
1175:"Haswell Transactional Memory Alternatives"
2166:
2152:
2144:
2005:Advanced Programmable Interrupt Controller
1969:Intel Communication Streaming Architecture
1859:
1845:
1837:
1622:
1566:
1552:
1544:
745:"Transactional Synchronization in Haswell"
474:TSXLDTRK introduces two new instructions,
184:). On processors that do not support HLE,
2047:High-bandwidth Digital Content Protection
1442:Afek, Y.; Levy, A.; Morrison, A. (2014).
104:kernel address space layout randomization
1530:, September 2014 (there is also another
364:
31:Transactional Synchronization Extensions
2482:(2008); ARMv8 also has AES instructions
619:
539:National Technical University of Athens
534:M-5Y70 Broadwell CPU in November 2014.
2604:Computer-related introductions in 2012
2092:Platform Environment Control Interface
1493:, Linux Plumbers Conference 2012 (PDF)
1147:De Gelas, Johan (September 20, 2012).
409:Set if an internal buffer overflowed.
1124:"Intel TSX implementation properties"
598:processors released in January 2023.
7:
1105:. Intel. September 2013. p. 446
1076:. Intel. September 2013. p. 342
287:instruction can be used without the
2077:Host Embedded Controller Interface
25:
1503:, January 30, 2013, by Andi Kleen
1497:Lock elision in the GNU C library
608:Advanced Synchronization Facility
466:TSX Suspend Load Address Tracking
417:Set if debug breakpoint was hit.
330:RTM adds three new instructions:
2582:Suspended extensions' dates are
1282:. Intel. 2021-06-12. p. 5.
1018:"Hardware Lock Elision Overview"
552:mode or System Management Mode (
961:Sebastien Dabdoub; Stephen Tu.
911:Gareth Halfacree (2021-06-29).
698:. November 2013. Archived from
322:Restricted Transactional Memory
164:. These two prefixes reuse the
135:Restricted Transactional Memory
18:Restricted Transactional Memory
1:
1515:, Volume 1, Chapter 2.5 (PDF)
992:Johan De Gelas (2012-09-20).
64:TSX/TSX-NI was documented by
2035:Active Management Technology
1964:MultiProcessor Specification
1540:, Gentoo, September 19, 2015
1491:Adding lock elision to Linux
1258:. p. 12. Archived from
793:. Tom's Hardware. 2013-06-01
610:– AMD's competing technology
50:instruction set architecture
1230:. December 2014. p. 10
1173:David Kanter (2012-08-21).
1045:David Kanter (2012-08-21).
1020:. intel.com. Archived from
936:Wooyoung Kim (2013-07-25).
835:Scott Wasson (2014-08-12).
2650:
1513:Software Developers Manual
1485:Presentation from IDF 2012
1195:Ian Cutress (2014-08-12).
791:"The Core i7-4770K Review"
523:speculative multithreading
507:Hyper-Threading Technology
489:
458:TSX/TSX-NI provides a new
45:), is an extension to the
2580:
1177:. Real World Technologies
1049:. Real World Technologies
318:prefix were not present.
52:(ISA) that adds hardware
2379:(FMA4: 2011, FMA3: 2012)
2072:Serial Digital Video Out
2062:Rapid Storage Technology
2437:Compressed instructions
2117:Ultra Path Interconnect
2102:Platform Controller Hub
2030:Intel Management Engine
1452:10.1145/2611462.2611482
873:. June 2014. p. 46
381:Set if abort caused by
59:transactions per second
2624:Transaction processing
2133:Silicon Photonics Link
2097:QuickPath Interconnect
1507:TSX Optimization Guide
519:memory ordering buffer
2107:System Management Bus
2052:High Definition Audio
1959:Common Building Block
1689:High Bandwidth Memory
152:Hardware Lock Elision
131:Hardware Lock Elision
2619:Transactional memory
2527:Transactional memory
1299:. Intel. 2021-06-12.
747:. Software.intel.com
142:optimistic execution
102:) in order to break
54:transactional memory
2629:Concurrency control
140:TSX/TSX-NI enables
2614:Parallel computing
1532:similar bug report
1509:, Chapter 12 (PDF)
696:supercomputing.org
672:software.intel.com
636:intel-research.net
2591:
2590:
2141:
2140:
2015:Intel Turbo Boost
1974:Intel Inboard 386
1834:
1833:
1672:
1671:
448:
447:
16:(Redirected from
2641:
2609:X86 instructions
2412:Bit manipulation
2168:
2161:
2154:
2145:
2057:Hub Architecture
2025:Intel Secure Key
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725:sisoftware.co.uk
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638:. Archived from
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529:History and bugs
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365:
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2175:Instruction set
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2082:Hyper-threading
1993:
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1600:Radeon Software
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1538:Intel microcode
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1436:Further reading
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1479:External links
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1421:. Intel. 2020
1417:
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1397:. Intel. 2020
1396:
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1376:. Intel. 2020
1375:
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1355:. Intel. 2020
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1313:. Intel. 2020
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1253:"HiPEAC info"
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1126:. Intel. 2013
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1024:on 2013-10-29
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702:on 2013-10-29
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645:on 2016-10-24
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96:timing attack
94:
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72:based on the
71:
67:
62:
60:
55:
51:
48:
44:
40:
36:
32:
19:
2583:
2534:
2466:cryptography
2353:
2040:AMT versions
1952:Discontinued
1745:Instructions
1684:Cool'n'Quiet
1443:
1423:. Retrieved
1410:
1399:. Retrieved
1389:
1378:. Retrieved
1368:
1357:. Retrieved
1347:
1336:. Retrieved
1326:
1315:. Retrieved
1305:
1291:
1283:
1271:
1260:the original
1247:
1238:
1232:. Retrieved
1215:
1204:. Retrieved
1190:
1179:. Retrieved
1168:
1160:
1153:. Retrieved
1142:
1134:
1128:. Retrieved
1118:
1107:. Retrieved
1078:. Retrieved
1051:. Retrieved
1026:. Retrieved
1022:the original
1012:
1001:. Retrieved
973:. Retrieved
969:
956:
945:. Retrieved
931:
920:. Retrieved
917:The Register
906:
889:
881:
875:. Retrieved
844:. Retrieved
840:
816:. Retrieved
806:
795:. Retrieved
785:
774:. Retrieved
772:. 2012-02-08
770:Ars Technica
769:
760:
749:. Retrieved
739:
728:. Retrieved
724:
715:
704:. Retrieved
700:the original
695:
686:
675:. Retrieved
671:
658:
647:. Retrieved
640:the original
635:
622:
593:
581:
569:Whiskey Lake
558:
543:
536:
532:
518:
511:
503:
495:
473:
469:
457:
370:bit position
368:EAX register
329:
325:
308:
304:MOV mem, imm
300:MOV mem, reg
293:
202:
155:
147:
139:
134:
130:
128:
116:
93:side-channel
90:
63:
42:
38:
34:
30:
29:
2450:MIPS16e ASE
2112:Thunderbolt
1155:23 December
1151:. AnandTech
814:. intel.com
565:Coffee Lake
454:instruction
112:Coffee Lake
100:page faults
91:In 2016, a
2598:Categories
2178:extensions
1979:Intel Play
1918:Skulltrail
1888:Centrino 2
1870:technology
1772:CVT16/F16C
1719:AMD Wraith
1709:Turbo Core
1677:Technology
1610:Xilinx ISE
1577:technology
1425:2020-10-21
1401:2020-10-10
1380:2020-10-10
1359:2020-10-10
1338:2020-10-10
1317:2020-10-10
1234:2014-12-28
1206:2014-08-30
1181:2013-11-14
1130:2013-11-14
1109:2013-11-19
1080:2013-11-19
1053:2013-11-19
1028:2013-10-27
1003:2013-10-20
975:2013-11-12
947:2013-11-12
922:2012-10-17
877:2014-08-13
846:2014-08-12
818:2014-02-11
797:2012-06-03
776:2012-02-09
751:2012-02-07
730:2013-11-14
706:2013-11-14
677:2014-03-03
649:2013-11-14
615:References
585:Comet Lake
501:protocol.
490:See also:
433:Reserved.
362:register.
176:prefixes (
2267:Power ISA
2248:MIPS SIMD
2087:Omni-Path
2067:SpeedStep
1913:Ultrabook
1876:Platforms
1704:PowerTune
1699:PowerPlay
1694:PowerNow!
1619:Platforms
1201:AnandTech
998:AnandTech
480:XRESLDTRK
476:XSUSLDTRK
241:CMPXCHG8B
86:microcode
82:Broadwell
2573:(AMD-Vi)
2126:Upcoming
1883:Centrino
1734:Ryzen AI
1647:Obsolete
1583:Software
1470:16645370
602:See also
589:Ice Lake
563:through
373:Meaning
316:XACQUIRE
312:XACQUIRE
296:XRELEASE
211:prefix:
205:XACQUIRE
198:XRELEASE
194:XACQUIRE
162:XRELEASE
158:XACQUIRE
125:Features
88:update.
2474:PadLock
2389:AVX-512
2255:PA-RISC
2238:MIPS-3D
1998:Current
1928:Galileo
1638:GPUOpen
1626:Current
1501:LWN.net
970:mit.edu
900:. 2016.
561:Skylake
546:Skylake
515:Skylake
237:CMPXCHG
166:opcodes
108:Skylake
74:Haswell
61:(TPS).
2567:(2006)
2561:(2005)
2537:(2013)
2518:(2021)
2512:(2015)
2506:(2015)
2500:(2013)
2494:(2012)
2492:RDRAND
2488:(2010)
2480:AES-NI
2476:(2003)
2428:(2014)
2403:(2023)
2397:(2022)
2391:(2015)
2385:(2013)
2373:(2009)
2367:(2009)
2361:(2008)
2354:(2007)
2347:(2006)
2341:(2006)
2335:(2004)
2329:(2001)
2323:(1999)
2317:(1998)
2315:3DNow!
2311:(1996)
1933:Edison
1903:Tablet
1757:3DNow!
1752:X86-64
1724:Virtex
1659:Dragon
1654:Spider
1605:Vivado
1595:AMDGPU
1468:
1458:
442:XABORT
383:XABORT
356:XBEGIN
352:XABORT
344:XBEGIN
342:. The
340:XABORT
332:XBEGIN
283:. The
279:, and
121:fork.
43:TSX-NI
2565:AMD-V
2486:CLMUL
2445:Thumb
2401:AVX10
2339:SSSE3
2279:SPARC
2199:Alpha
1989:MMC-2
1984:MMC-1
1938:Curie
1868:Intel
1664:Horus
1590:AGESA
1487:(PDF)
1466:S2CID
1419:(PDF)
1280:(PDF)
1263:(PDF)
1256:(PDF)
1240:SKUs.
1228:Intel
1224:(PDF)
1103:(PDF)
1074:(PDF)
966:(PDF)
942:Intel
898:(PDF)
871:Intel
867:(PDF)
668:(PDF)
643:(PDF)
632:(PDF)
575:CPUID
460:XTEST
452:XTEST
438:31:24
186:REPNE
170:REPNE
66:Intel
2571:VT-d
2559:VT-x
2383:AVX2
2365:F16C
2351:SSE5
2345:SSE4
2333:SSE3
2327:SSE2
2296:SIMD
2233:MDMX
2228:MIPS
2216:NEON
2190:RISC
2186:SIMD
2020:vPro
2010:CNVi
1908:CULV
1893:Viiv
1816:SSE5
1804:BMI1
1787:FMA3
1782:FMA4
1729:XDNA
1714:ASTC
1633:ROCm
1528:LKML
1456:ISBN
1157:2013
587:and
567:and
478:and
430:23:6
348:XEND
346:and
338:and
336:XEND
302:and
294:The
289:LOCK
285:XCHG
281:XCHG
277:XADD
209:LOCK
203:The
190:REPE
174:REPE
160:and
119:QEMU
78:SKUs
2541:ASF
2535:TSX
2516:TDX
2510:SGX
2504:MPX
2498:SHA
2455:RVC
2426:ADX
2420:BMI
2395:AMX
2377:FMA
2371:XOP
2359:AVX
2321:SSE
2309:MMX
2300:x86
2284:VIS
2272:VMX
2260:MAX
2243:MXU
2221:SVE
2211:ARM
2204:MVI
1943:Evo
1923:NUC
1898:MID
1826:AES
1821:ASF
1809:TBM
1799:ABM
1794:BMI
1777:FMA
1767:XOP
1762:AVX
1575:AMD
1448:doi
554:SMM
550:SGX
360:EAX
273:XOR
269:SUB
265:SBB
257:NOT
253:NEG
249:INC
245:DEC
233:BTS
229:BTR
225:BTC
221:AND
217:ADC
213:ADD
182:F3H
178:F2H
110:to
47:x86
35:TSX
2600::
1526:,
1499:,
1464:.
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