158:
Table', this configuration table in each device allows the host to access the local memory of a PCIe device. Both the Type 1 and Type 0 configuration tables are set up by the Host
Operating System that controls the Root Complex by a process known as enumeration and which acts to build a device memory map for the system by querying each bridge, and endpoint device connected on the bus network. Similarly, a PCIe Bridge acts a tiered root complex with a "Type 0 Configuration Table".
17:
260:
61:
157:
The PCIe Root
Complex holds a master copy of a 'Type 1 Configuration Table' that defines the host memory space that is accessible from each Endpoint device. In addition, each PCIe Endpoint device holds a master copy of their own memory space map in the host system memory as a 'Type 0 Configuration
47:, which is interconnected through a local bus. Root complex functionality may be integrated in the chipset and/or the CPU. A root complex may contain more than one PCI Express port and multiple switch devices can be connected to ports on the root complex or cascaded.
301:
320:
294:
144:
325:
228:
82:
32:
device connects the CPU and memory subsystem to the PCI Express switch fabric composed of one or more PCIe or PCI devices.
125:
78:
176:
97:
287:
104:
71:
111:
93:
16:
267:
271:
40:
204:
118:
20:
An example of the PCI Express topology, displaying the position of a root complex.
259:
314:
232:
60:
36:
25:
229:"Choosing the Right Programmable Logic Solution for PCI Express Applications"
43:
system, the root complex generates transaction requests on behalf of the
183:
85: in this section. Unsourced material may be challenged and removed.
15:
54:
44:
275:
295:
8:
302:
288:
145:Learn how and when to remove this message
205:"Bus Specifics (Writing Device Drivers)"
167:
7:
256:
254:
83:adding citations to reliable sources
177:"PCI Express Basics and Background"
274:. You can help Knowledge (XXG) by
14:
321:Peripheral Component Interconnect
258:
59:
70:needs additional citations for
175:Richard Solomon (2015-06-17).
1:
342:
253:
326:Computer hardware stubs
21:
19:
79:improve this article
235:on 21 February 2011
22:
283:
282:
268:computer hardware
155:
154:
147:
129:
51:Device Memory Map
28:(PCIe) system, a
333:
304:
297:
290:
262:
255:
245:
244:
242:
240:
231:. Archived from
225:
219:
218:
216:
215:
201:
195:
194:
192:
191:
181:
172:
150:
143:
139:
136:
130:
128:
87:
63:
55:
341:
340:
336:
335:
334:
332:
331:
330:
311:
310:
309:
308:
251:
249:
248:
238:
236:
227:
226:
222:
213:
211:
209:docs.oracle.com
203:
202:
198:
189:
187:
179:
174:
173:
169:
164:
151:
140:
134:
131:
88:
86:
76:
64:
53:
12:
11:
5:
339:
337:
329:
328:
323:
313:
312:
307:
306:
299:
292:
284:
281:
280:
263:
247:
246:
220:
196:
166:
165:
163:
160:
153:
152:
94:"Root complex"
67:
65:
58:
52:
49:
13:
10:
9:
6:
4:
3:
2:
338:
327:
324:
322:
319:
318:
316:
305:
300:
298:
293:
291:
286:
285:
279:
277:
273:
270:article is a
269:
264:
261:
257:
252:
234:
230:
224:
221:
210:
206:
200:
197:
185:
178:
171:
168:
161:
159:
149:
146:
138:
127:
124:
120:
117:
113:
110:
106:
103:
99:
96: –
95:
91:
90:Find sources:
84:
80:
74:
73:
68:This section
66:
62:
57:
56:
50:
48:
46:
42:
38:
35:Similar to a
33:
31:
27:
18:
276:expanding it
265:
250:
237:. Retrieved
233:the original
223:
212:. Retrieved
208:
199:
188:. Retrieved
186:. p. 26
170:
156:
141:
132:
122:
115:
108:
101:
89:
77:Please help
72:verification
69:
34:
30:root complex
29:
23:
135:August 2012
37:host bridge
26:PCI Express
315:Categories
214:2020-11-14
190:2016-04-12
162:References
105:newspapers
239:31 March
184:PCI-SIG
119:scholar
121:
114:
107:
100:
92:
266:This
180:(PDF)
126:JSTOR
112:books
39:in a
24:In a
272:stub
241:2010
98:news
81:by
45:CPU
41:PCI
317::
207:.
182:.
303:e
296:t
289:v
278:.
243:.
217:.
193:.
148:)
142:(
137:)
133:(
123:·
116:·
109:·
102:·
75:.
Text is available under the Creative Commons Attribution-ShareAlike License. Additional terms may apply.