SPARC64 V - Knowledge (XXG)

1213:. Each of the two pipelines of a core can fetch 8 instructions, decode 4 instructions and execute 6 instructions per cycle, and supports 4 SMT threads (for 96 threads per CPU). Each pipeline has an own 32 MB 4-way L1 data cache, and two pipelines share a 64 MB 4-way associative L1 instruction cache and a 512 MB 16-way L2 cache. SPARC64 XII is Fujitsu's first SPARC CPU with L3 cache (32 MB 16-way). The number of 8-lane PCIe 3.0 ports has been doubled to 4 per chip. Memory speed has been increased by 50% to 2400 MT/s, bringing the theoretical combined bandwidth of the 8 DDR4 channels of the chip to 153 GB/s, and the capacity per CPU is up to 1.5 TB across 24 slots. Two CPUs can be connected in a Building Block, and up to 16 Building Blocks can be connected to create a 32-CPU server with up to 48 TB of memory. 238:

stations, two that serve the integer units, one for the address generators, two for the floating-point units, and one for branch instructions. Each integer, address generator and floating-point unit has an eight-entry reserve station. Each reserve station can dispatch an instruction to its execution unit. Which instruction is dispatched firstly depends on operand availability and then its age. Older instructions are given higher priority than newer ones. The reserve stations can dispatch instructions speculatively (speculative dispatch). That is, instructions can be dispatched to the execution units even when their operands are not yet available but will be when execution begins. During stage six, up to six instructions are dispatched.

736: 702:. It is socket-compatible with its predecessor, the SPARC64 VI, and is field-upgradeable. SPARC64 VIIs could coexist, whilst operating at their native clock frequency, alongside SPARC64 VIs. The first versions of the SPARC64 VII were a 2.4 GHz version with a 5 MB L2 cache used in the SPARC Enterprise M4000 and M5000, and a 2.52 GHz version with a 6 MB L2 cache. On 28 October 2008, a 2.52 GHz version with a 5 MB L2 cache was introduced in the SPARC Enterprise M3000. On 13 October 2009, Fujitsu and Sun introduced new versions of the SPARC64 VII (code-named 880:

execution pipeline to access the larger floating-point register file. The 128-bit SIMD instructions from HPC-ACE were implemented by adding two extra floating-point units for a total of four. SIMD execution can perform up four single- or double-precision fused-multiply-add operations (eight FLOPs) per cycle. The number of load queue entries was increased to 20 from 16, and the L1 data cache was halved in size to 32 KB. The number of commit stack entries, which determined the number of instructions that could be in-flight in the back-end, was reduced to 48 from 64.

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registers. The SPARC V9 instruction encoding limited the number of registers specifiable to 32. To specify the extra registers, HPC-ACE has a "prefix" instruction that would immediately follow one or two SPARC V9 instructions. The prefix instruction contained (primarily) the portions of the register numbers that could not fit within a SPARC V9 instruction. This extra pipeline stage was where up to four SPARC V9 instructions were combined with up to two prefix instructions in the preceding stage. The combined instructions were then decoded in the next pipeline stage.

198:, a small but very fast 8 KB L1 data cache, and separate L2 caches for instructions and data. It was designed in Fujitsu's CS85 process, a 0.17 μm CMOS process with six levels of copper interconnect; and would have consisted of 65 million transistors on a 380 mm die. Originally scheduled for a late 2001 release in Fujitsu GranPower servers, it was canceled in mid-2001 when HAL was closed by Fujitsu, and replaced by a Fujitsu design. 2988: 1164: 755: 3462: 727:

approximately 20% increase to overall performance. A 2.66 GHz version was for mid-range M4000 and M5000 models. On 12 April 2011, a 2.86 GHz version with two or four cores and a 5.5 MB L2 cache was announced for the low-end M3000. The VII+ is socket-compatible with its predecessor, the VII. Existing high-end SPARC Enterprise M-Series servers are able to upgrade to the VII+ processors in the field.

1119:, the IXfx was the first processor to use HMCs. The XIfx is connected to 32 GB of memory provided by eight 4 GB HMCs. The HMCs are 16-lane versions, with each lane operating at 15 Gbit/s. Each CMG has two HMC interfaces, and each HMC interface is connected to two HMCs via its own ports. Each CMG has 240 GB/s (120 GB/s in and 120 GB/s out) of memory bandwidth. 3474: 963:

to 12 MB, and increasing peak DDR3 SDRAM memory bandwidth to 85 GB/s. The IXfx operates at 1.848 GHz, has a peak performance of 236.5 GFLOPS, and consumes 110 W for a power efficiency of more than 2 GFLOPS per watt. It consisted of 1 billion transistors and was implemented in a 40 nm CMOS process with copper interconnects.

40: 284:(SIMD) instructions. All instructions are pipelined except for divide and square root, which are executed using iterative algorithms. The FMA instruction is implemented by reading three operands from the operand register, multiplying two of the operands, forwarding the result and the third operand to the adder, and adding them to produce the final result. 642:(VMT). In CMT, which thread is executed is determined by time-sharing, or if the thread is executing a long-latency operation, then execution is switched to the other thread. The addition of CMT required duplication of the program counter and the control, integer, and floating-point registers so there is one set of each for every thread. A floating-point 1092:), each consisting of 16 compute cores and 1 assistant core sharing a 12 MB L2 unified cache. The division of the cores into CMGs enabled 34 cores to be integrated on a single die by easing the implementation of cache coherence and avoiding the need for the L2 cache to be shared between 34 cores. The two CMGs share the memory through a 247:

contains a subset of the eight register windows, the previous, current and next register windows. Its purpose is reduce the size of register file so that the microprocessor can operate at higher clock frequencies. The floating-point register file contains 64 entries and has six read ports and two write ports.

1205:, L1 instruction cache and L2 cache, and as a result the single-threaded performance is almost unchanged from SPARC64 X. SPARC64 XII operates at up to 4.25 GHz base frequency and 4.35 GHz boost frequency. The size of the chip is 25.8mm × 30.8mm (795mm), containing 5.45 billion transistors made on 1083:

used to run the operating system and other system services. The delegation of user applications and operating system to dedicated cores improves performance by ensuring that the private caches of the compute cores are not shared with or disrupted by non-application instructions and data. The 34 cores

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The register files are read during stage seven. The SPARC architecture has separate register files for integer and floating-point instructions. The integer register file has eight register windows. The JWR (Joint Work Register) contains 64 entries and has eight read ports and two write ports. The JWR

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supercomputer on 7 November 2011. It, along with the PRIMEHPC FX10, is a commercialization of the technologies that first appeared in the VIIIfx and K computer. Compared to the VIIIfx, organizational improvements included doubling the number of cores was to 16, doubling the amount of shared L2 cache

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The back-end was also heavily modified. The number of reservation station entries for branch and integer instructions were reduced to six and ten, respectively. Both the integer and floating-point register files had registers added to them: the integer register file gained 32, and there were a total

975:

is a 16-core server microprocessor announced in 2012 and used in Fujitsu's M10 servers (which are also marketed by Oracle). The SPARC64 X is based on the SPARC64 VII+ with significant enhancements to its core and chip organization. The cores were improved by the inclusion of a pattern history table

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defined by SPARC V9, but are always accessible via the prefix instruction; and the 256 floating-point registers could be used by both scalar floating-point instructions and by both integer and floating-point SIMD instructions. An extra pipeline stage was added to the beginning of the floating-point

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The SPARC64 VI was originally to have been introduced in mid-2004 in Fujitsu's PrimePower servers. Development of the PrimerPowers were canceled after Fujitsu and Sun Microsystems announced in June 2004 that they would collaborate on new servers called the Advanced Product Line (APL). These servers

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The SPARC64 V fetches up to eight instructions from the instruction cache during the first stage and places them into a 48-entry instruction buffer. In the next stage, four instructions are taken from this buffer, decoded and issued to the appropriate reserve stations. The SPARC64 V has six reserve

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The first Fujitsu SPARC64 Vs were fabricated in December 2001. They operated at 1.1 to 1.35 GHz. Fujitsu's 2003 SPARC64 roadmap showed that the company planned a 1.62 GHz version for release in late 2003 or early 2004, but it was canceled in favor of the SPARC64 V+. The SPARC64 V was used

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is an enhanced SPARC64 X processor announced in 2013. It features minor improvements to the core organization, and a higher 3.5 GHz clock frequency obtained through better circuit design and layout. It contained 2.99 billion transistors, measured 24 mm by 25 mm (600 mm), and is

1122:

The XIfx replaced the ten SERDES channels to an external Tofu interconnect controller with a ten-port integrated controller for the second-generation Tofu2 interconnect. Tofu2 is a 6D mesh/torus network with a 25 GB/s full-duplex bandwidth (12.5 GB/s per direction, 125 GB/s for ten

649:

The cores share a 6 MB on-die unified L2 cache. The L2 cache is 12-way set associative and has 256-byte lines. The cache is accessed via two unidirectional buses, a 256-bit read bus and a 128-bit write bus. The SPARC64 VI has a new system bus, the Jupiter Bus. The SPARC64 VI consisted of 540

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Results from the execution units and loads are not written to the register file. To maintain program order, they are written to update buffers, where they reside until committed. The SPARC64 V has separate update buffers for integer and floating-point units. Both have 32 entries each. The integer

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The level 1 (L1) caches each have a capacity of 128 KB. They are both two-way set associative and have 64-byte line size. They are virtually indexed and physically tagged. The instruction cache is accessed via a 256-bit bus. The data cache is accessed with two 128-bit buses. The data cache

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reduced to two from eight; and an extra pipeline stage was inserted before the instruction decoder. This stage accommodated the greater number of integer and floating-point registers defined by HPC-ACE. The SPARC V9 architecture was designed to have only 32 integer and 32 floating-point number

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by Oracle, is a further development of the SPARC64 VII. The clock frequency was increased up to 3 GHz and the L2 cache size was doubled to 12 MB. This version was announced on 2 December 2010 for the high-end SPARC Enterprise M8000 and M9000 servers. These improvements resulted in an

451:

The first SPARC64 V+, a 1.89 GHz version, was shipped in September 2004 in the Fujitsu PrimePower 650 and 850. In December 2004, a 1.82 GHz version was shipped in the PrimePower 2500. These versions have a 3 MB L2 cache. In February 2006, four versions were introduced: 1.65 and

865:

The VIIIfx core is based on that of the SPARC64 VII with numerous modifications for HPC, namely High Performance Computing-Arithmetic Computational Extensions (HPC-ACE) a Fujitsu-designed extension to the SPARC V9 architecture. The front-end had coarse-grained multi-threading removed, the L1

348:

At 1.3 GHz, the SPARC64 V has a power dissipation of 34.7 W. The Fujitsu PrimePower servers that use the SPARC64 V supply a slightly higher voltage the microprocessor to enable it to operate at 1.35 GHz. The increased power supply voltage and operating frequency increased the power

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units to 256 bits and added new SIMD instructions. Compared to the SPARC64 IXfx, the XIfx has an improvement of a factor of 3.2 for double precision and 6.1 for single precision. To complement the increased width of the SIMD units, the L1 cache bandwidth was increased to 4.4 TB/s.

830:, Hitachi and NEC announced in May 2009 that they would leave the project because manufacturing the hardware they were responsible for would result in financial losses for them. Afterwards, Fujitsu redesigned the supercomputer to use the VIIIfx as its only processor type. 690:

features; the integer register file is now protected by ECC, and the number of error checkers has been increased to around 3,400. It consists of 600 million transistors, is 21.31 mm × 20.86 mm (444.63 mm) large, and is fabricated by Fujitsu in its

706:), a 2.53 GHz version with a 5.5 MB L2 cache for the M4000 and M5000, and a 2.88 GHz version with a 6 MB L2 cache for the M8000 and M9000. On 12 January 2010, a 2.75 GHz version with a 5 MB L2 cache was introduced in the M3000. 158:

servers. In addition to servers, a version of the SPARC64 VII was also used in the commercially available Fujitsu FX1 supercomputer. As of October 2017, the SPARC64 XII is the latest server processor, and it is used in the Fujitsu and Oracle M12 servers.

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Yoshida, Toshio; Maruyama, Takumi; Akizuki, Yasunobu; Kan, Ryuji; Kiyota, Naohiro; Ikenishi, Kiyoshi; Itou, Shigeki; Watahiki, Tomoyuki; Okano, Hiroshi (November–December 2013). "Sparc64 X: Fujitsu's New-Generation 16-Core Processor for Unix Servers".

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register has eight read ports and four write ports. Half of the write ports are used for results from the integer execution units and the other half by data returned by loads. The floating-point update buffer has six read ports and four write ports.

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Kan, Ryuji; Tanaka, Tomohiro; Sugizaki, Go; Nishiyama, Ryuichi; Sakabayashi, Sota; Koyanagi, Yoichi; Iwatsuki, Ryuji; Hayasaka, Kazumi; Uemura, Taiki; Ito, Gaku; Ozeki, Yoshitomo; Adachi, Hiroyuki; Furuya, Kazuhiro; Motokurumada, Tsuyoshi (2013).

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Maruyama, Takumi; Yoshida, Toshio; Kan, Ryuji; Yamazaki, Iwao; Yamamura, Shuji; Takahashi, Noriyuki; Hondou, Mikio; Okano, Hiroshi (March–April 2010). "Sparc64 VIIIfx: A New-Generation Octocore Processor for Petascale Computing".

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Yoshida, Toshio; Hondou, Mikio; Tabata, Takekazu; Kan, Ryuji; Kiyota, Naohiro; Kojima, Hiroyuki; Hosoe, Koji; Okano, Hiroshi (March–April 2015). "Sparc64 XIfx: Fujitsu's Next-Generation Processor for High-Performance Computing".

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The microprocessor has a 128-bit system bus that operates at 260 MHz. The bus can operate in two modes, single-data rate (SDR) or double-data (DDR) rate, yielding a peak bandwidth of 4.16 or 8.32 GB/s, respectively.

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Kan, Ryuji; Tanaka, Tomohiro; Sugizaki, Go; Ishizaka, Kinya; Nishiyama, Ryuichi; Sakabayashi, Sota; Koyanagi, Yoichi (January 2014). "The 10th Generation 16-Core SPARC64 Processor for Mission Critical UNIX Server".

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Commit takes place during stage ten at the earliest. The SPARC64 V can commit up to four instructions per cycle. During stage eleven, results are written to the register file, where it becomes visible to software.

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The two floating-point units (FPUs) are designated FLA and FLB. Each FPU contains an adder and a multiplier, but only FLA has a graphics unit attached. They execute add, subtract, multiply, divide, square root and

260:(ALU) and a shift unit, but only EXA has multiply and divide units. Loads and stores are executed by two address generators (AGs) designated AGA and AGB. These are simple ALUs used to calculate virtual addresses. 1807: 773:(HPC). As a result, the VIIIfx did not succeed the VII, but existed concurrently with it. It consists of 760 million transistors, measures 22.7 mm by 22.6 (513.02 mm;), is fabricated in Fujitu's 255:

Execution begins during stage nine. There are six execution units, two for integer, two for loads and stores, and two for floating-point. The two integer execution units are designated EXA and EXB. Both have an

2598:

Okano, Hiroshi; Kawabe, Yukihito; Kan, Ryuji; Yoshida, Toshio; Yamazaki, Iwao; Sakurai, Hitoshi; Hondou, Mikio; Matsui, Nobuyki; Yamashita, Hideo; Nakada, Tatsumi; Maruyama, Takumi; Asakawa, Takeo (2010).

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Ando, H.; Yoshida, Y.; Inoue, A.; Sugiyama, I.; Asakawa, T.; Morita, K.; Muta, T.; Motokurumada, T.; Okada, S.; Yamashita, H.; Satsukawa, Y.; Konmoto, A.; Yamashita, R.; Sugiyama, H. (13 February 2003).

992:, and decimal floating-point number arithmetic and conversion functions. The 16 cores share a unified, 24 MB, 24-way set-associative L2 cache. Chip organization improvements include four integrated 809:

in January 2006. The project aimed to produce the world's fastest supercomputer with performance of over 10 PFLOPS by March 2011. The companies contracted to develop the supercomputer were Fujitsu,

448:, code-named "Olympus-B", is a further development of the SPARC64 V. Improvements over the SPARC64 V included higher clock frequencies of 1.82–2.16 GHz and a larger 3 or 4 MB L2 cache. 806: 658:. The SPARC64 VI processors featured in the SPARC Enterprise at its announcement were a 2.15 GHz version with a 5 MB L2 cache, and 2.28 and 2.4 GHz versions with 6 MB L2 caches. 2250: 2456:

Ando, H.; Yoshida, Y.; Inoue, A.; Sugiyama, I.; Asakawa, T.; Morita, K.; Muta, T.; Motokurumada, T.; Okada, S.; Yamashita, H.; Satsukawa, Y.; Konmoto, A.; Yamashita, R.; Sugiyama, H. (2003).

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1.98 GHz versions with 3 MB L2 caches shipped in the PrimePower 250 and 450; and 2.08 and 2.16 GHz versions with 4 MB L2 caches shipped in mid-range and high-end models.

205:

The SPARC64 V was first presented at Microprocessor Forum 2002. At introduction, it had the highest clock frequency of both SPARC and 64-bit server processors in production; and the highest

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controllers. The SPARC64 X contains 2.95 billion transistors, measures 23.5 mm by 25 mm (587.5 mm), and is fabricated in a 28 nm CMOS process with copper interconnects.

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The XIfx core was based on the SPARC64 X+ with organizational improvements. The XIfx implements an improved version of the HPC-ACE extensions (HPC-ACE2), which doubled the width of the

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The SPARC64 V has two-level cache hierarchy. The first level consists of two caches, an instruction cache and a data cache. The second level consists of an on-die unified cache.

1201:

that was launched the same year, each of the twelve cores consists of two separate pipelines, and the only resources shared between SPARC64 XII core's pipelines are the

984:, more execution units, support for the HPC-ACE extension (originally from the SPARC64 VIIIfx), deeper pipeline for a 3.0 GHz clock frequency, and accelerators for 1816: 333: 826:. The Fujitsu-designed VIIIfx was to have been the scalar processor, with the vector processor to have been jointly designed by Hitachi and NEC. However, due to the 3227: 304:

consists of eight banks separated by 32-bit boundaries. It uses a write-back policy. The data cache writes to the L2 cache with its own 128-bit unidirectional bus.

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The servers series are the SPARC64 V+, VI, VI+, VII, VII+, X, X+ and XII. The SPARC64 VI and its successors up to the VII+ were used in the Fujitsu and Sun (later

1770: 2193: 1918: 2257: 2274: 1058: 2838: 2820: 1057:. The XIfx operates at 2.2 GHz and has a peak performance of 1.1 TFLOPS. It consists of 3.75 billion transistors and is fabricated by the 1132: 866:

instruction cache halved in size to 32 KB; and the number of branch target address cache (BTAC) entries reduced to 1,024 from 8,192, and its

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It contained approximately 400 million transistors on an 18.46 mm by 15.94 mm die for an area of 294.25 mm. It was fabricated in a

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Sakamoto, Mariko et al. (2003). "Microarchitecture and Performance Analysis of a SPARC-V9 Microprocessor for Enterprise Server Systems".

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four-way symmetrical multiprocessing, ten SERDES channels for symmetrical multiprocessing scalability to 64 sockets, and two integrated

674:, is a further development of the SPARC64 VI announced in July 2008. It is a quad-core microprocessor. Each core is capable of two-way 170:. As of July 2016, the SPARC64 XIfx is the latest supercomputer processor, and it is used in the Fujitsu PRIMEHPC FX100 supercomputer. 1841: 827: 162:

The supercomputer series was based on the SPARC64 VII, and are the SPARC64 VIIfx, IXfx, and XIfx. The SPARC64 VIIIfx was used in the

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and a typical power consumption of 58 W at 30 °C for an efficiency of 2.2 GFLOPS/W. The VIIIfx has four integrated

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as the SPARC64 V. First announced at Microprocessor Forum 1999, the HAL SPARC64 V would have operated 1 GHz and had a wide

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CMOS process with copper interconnects, and has 1,271 I/O pins. The VIIIfx has a peak performance at 2 GHz of 128

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Fine grained power analysis and low-power techniques of a 128GFLOPS/58W SPARC64 VIIIfx processor for peta-scale computing

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with separate multiplication and addition operations, thus with up to two rounding errors. The graphics unit executes

147:. The SPARC64 V was the basis for a series of successive processors designed for servers, and later, supercomputers. 2809: 2034: 2384: 770: 2188: 3051: 654:

were scheduled to be introduced in mid-2006, but were delayed until April 2007, when they were introduced as the

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The SPARC64 V consisted of 191 million transistors, of which 19 million are contained in logic circuits. It was

3075: 2916: 3390: 2371: 1745: 1697: 1385:"Microarchitecture and Performance Analysis of a SPARC-V9 Microprocessor for Enterprise Server Systems", p. 4. 2022: 1896: 1581:"Sun SPARC Enterprise Server Family Architecture: Flexible, Mainframe-Class Compute Power for the Datacenter" 1147:

will implement extensions to the ARMv8 architecture, equivalent to HPC-ACE2, that Fujitsu is developing with

622:, code-named Olympus-C, is a two-core processor (the first multi-core SPARC64 processor) which succeeded the 3335: 3011: 496: 392: 76: 1197:

was launched in 2017 with Fujitsu's SPARC M12 servers. It nominally features 12 cores, but just like IBM's

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The second level cache has a capacity of 1 or 2 MB and the set associativity depends on the capacity.

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Prickett, Timothy Morgan (8 April 2014). "Oracle Unfolds Sparc Roadmap, Fujitsu boosts SPARC64 X Clocks".

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Project Committee announced that the K computer (still incomplete with only 68,544 processors) topped the

630:(SOI) process, which enabled two cores and an L2 cache to be integrated on a die. Each core is a modified 277: 222: 1648: 3157: 2858: 2358: 2350: 2341: 2332: 2323: 2314: 2305: 2160: 2008: 1332: 1260: 981: 857:, realizing 93% of its peak performance, making it the fastest supercomputer in the world at that time. 257: 191: 2423:

Solid-State Circuits Conference, 1997. Digest of Technical Papers. 43rd ISSCC., 1997 IEEE International

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Ando, Hisashige; Kan, Ryuji; Tosaka, Yoshiharu; Takahisa, Keiji; Hatanaka, Kichiji (24–27 June 2008).

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Yoshida, Toshio (27 August 2013). "SPARC64 X+: Fujitsu's Next Generation Processor for UNIX servers".

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Microarchitecture and Performance Analysis of a SPARC-V9 Microprocessor for Enterprise Server Systems

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Ito, N.; Komatsu, H.; Tanamura, Y.; Yamashita, R.; Sugiyama, H.; Sugiyama, Y.; Hamamura, H. (2003).

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Improvements to the SoC organization were to the memory and interconnect interfaces. The integrated

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estimated the die to have an area of 500 mm; and a typical power consumption of 200 W.

643: 226: 151: 1870: 686:(VMT) by Fujitsu. Thus, it can execute eight threads simultaneously. Other changes include more 1282:. Ninth International Symposium on High-Performance Computer Architecture, 2003 (HPCA-9 2003). 3415: 3410: 3286: 2942: 2778: 2733: 2695: 2665: 2655: 2622: 2612: 2578: 2541: 2531: 2506: 2496: 2469: 2444: 2434: 2069: 1786: 1606: 1413: 1400:

Ando, Hisashige; et al. (June 2003). "A 1.3GHz fifth generation SPARC64 microprocessor".

1255: 1115:(HMC) interfaces for decreased memory latency and improved memory bandwidth. According to the 1108: 850: 782: 340:(SOI) process. The die measured 18.14 mm by 15.99 mm for a die area of 290 mm. 941:

Page sizes: 8 KB, 64 KB, 512 KB, 4 MB, 32 MB, 256 MB, 2 GB

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SPARC64™ X: Fujitsu's new generation 16 core processor for the next generation UNIX servers

1062: 3204: 2973: 2824: 2293: 2197: 1018: 1001: 955: 904: 876: 2522:. 2008 IEEE International Conference on Dependable Systems and Networks. pp. 62–69. 2398:

Proceedings of the 9th International Symposium on High-Performance Computer Architecture

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symposium. It is used in the Fujitsu PRIMEHPC FX100 supercomputer, which succeeded the

818:. The supercomputer was originally envisioned to have a hybrid architecture containing 754: 747: 650:

million transistors. The die measures 20.38 mm by 20.67 mm (421.25 mm).

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SPARC64 VIIIfx: Fujitsu's New Generation Octo Core Processor for PETA Scale computing

1557: 1520: 1475: 1302: 1241: 1210: 1144: 1054: 959: 845:, Japan; it obtains its performance from 88,128 VIIIfx processors. In June 2011, the 329: 167: 2707: 2083: 1952: 907:

data, 32 KB two-way set-associative instruction (128-byte cache line), sectored

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The VIIIfx was developed for the Next-Generation Supercomputer Project (also called

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A 16-entry micro-TLB; and 256-entry, four-way set-associative TLB for instructions

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Validation of hardware error recovery mechanisms for the SPARC64 V microprocessor

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of 256 floating-point registers. The extra integer registers are not part of the

623: 3395: 3306: 3291: 3024: 610: 218: 195: 187: 183: 2651: 2608: 2430: 2251:"SPARC64™ XII: Fujitsu's latest 12 Core Processor for Mission Critical Servers" 1017:

fabricated in the same process as the SPARC64 X. On 8 April 2014, 3.7 GHz

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A 10th generation 16-core SPARC64 processor for mission-critical UNIX server

1945:"Japan Reclaims Top Ranking on Latest TOP500 List of World's Supercomputers" 1050: 867: 833:

By 2010, the supercomputer that would be built by the project was named the

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supercomputer will feature processors of its own design that implement the

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Halfhill, Tom R. (17 September 2012). "Fujitsu and Oracle Ignite SPARCs".

1409: 39: 17: 3247: 3189: 3056: 1746:"Ellison: Sparc T4 due next year: Sparc64-VII+ clock and cache bumps now" 1718:"Fujitsu and Oracle Enhance SPARC Enterprise M-Series with New Processor" 989: 911: 900: 521: 415: 99: 2729: 2158:

Halfhill, Tom R. (22 September 2014). "Sparc64 XIfx Uses Memory Cubes".

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Gwennap, Linley (7 October 2013). "Fujitsu, Oracle Processors Evolve".

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Byrne, Joseph (5 December 2011). "Sparc64 IXfx Burns Through FP Code".

811: 379: 144: 63: 2646:. IEEE International Solid-State Circuits Conference. pp. 60–61. 2487:. 21st International Conference on Computer Design. pp. 204–210. 2485:

A physical design methodology for 1.3 GHz SPARC 64 microprocessor

1773:. The Inquirer. 14 May 2009. Archived from the original on 17 May 2009 646:(FMA) instruction was also added, the first SPARC processor to do so. 3242: 3232: 3137: 3102: 3097: 2303:

Krewell, Kevin (24 November 2003). "Fujitsu Makes SPARC See Double".

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is an improved version of the SPARC64 VIIIfx designed by Fujitsu and

854: 846: 778: 626:. It is fabricated by Fujitsu in a 90 nm, 10-layer copper, CMOS 2348:

McGhan, Harlan (23 October 2006). "SPARC64 VI Ready for PrimeTime".

2339:

McGhan, Harlan (25 September 2006). "The Sun-Fujitsu APL Alliance".

1815:. Proceedings of Hot Chips 21. IEEE Computer Society. Archived from 2275:"Fujitsu SPARC M12 and Fujitsu M10 Server Architecture White Paper" 1732:"Fujitsu and Oracle Deliver Enhanced SPARC Enterprise M3000 Server" 1488:"Fujitsu-Siemens Cranks the Clock on Sparc V Chips for PrimePowers" 1303:"Fujitsu-Siemens Cranks the Clock on Sparc V Chips for PrimePowers" 934:

A 512-entry, four-way set-associative TLB for data, no victim cache

769:) is an eight-core processor based on the SPARC64 VII designed for 634:

processor. One of the main improvements is the addition of two-way

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Now integrated into other Fujitsu divisions or business groupings

2330:

Krewell, Kevin (14 November 2005). "SPARC's Still Going Strong".

3271: 3266: 3117: 1206: 1022: 842: 206: 2847: 1550:"Fujitsu and Sun Flex Their Quads with New Sparc Server Lineup" 1158: 1034: 1021:

parts became available in response to the introduction of new

914:

12-way set-associative (128-byte line), index-hashed, sectored

815: 807:

Ministry of Education, Culture, Sports, Science and Technology

1975:"K computer, SPARC64 VIIIfx 2.0 GHz, Tofu interconnect" 182:, a subsidiary of Fujitsu, was designing a successor to the 2421:. 2003 IEEE International Solid-State Circuits Conference. 1402:

Proceedings of the 40th annual Design Automation Conference

746:

featuring four SPARC64 VIIIfx processors (under the larger

2843: 2372:"Fujitsu, Oracle pair up on future 'Athena' Sparc64 chips" 841:'s Advanced Institute for Computational Science (AICS) in 2060:. 2012 IEEE Hot Chips 24 Symposium (HCS). pp. 1–20. 1513:"Fujitsu, Sun Deliver Joint Sparc Enterprise Server Line" 1919:"Supercomputer "K computer" Takes First Place in World" 1897:"Supercomputer "K computer" Takes First Place in World" 1369: 1367: 1175: 2385:"Fujitsu launches 'Athena' Sparc64-X servers in Japan" 2321:

Krewell, Kevin (25 October 2004). "SPARC Turns 90nm".

2153: 2151: 2149: 2051: 2049: 2312:

Krewell, Kevin (24 June 2004). "SPARC's New Roadmap.

2035:"Fujitsu readies 23 petaflops Sparc FX10 super beast" 166:, and the SPARC64 IXfx in the commercially available 2211:

Fujitsu guns for faster supercomputers with new chip

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page 56, Fujitsu Limited, Release 1.3, 27 March 2007

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complementary metal–oxide–semiconductor

110: 105: 93: 88: 74: 69: 59: 51: 46: 2460:. Design Automation Conference. pp. 702–705. 2226:"Inside Japan's Future Exascale ARM Supercomputer" 1720:(Press release). Fujitsu Limited. 2 December 2010. 1468:"Fujitsu-Siemens Upgrades PrimePower Unix Servers" 2419:A 1.3 GHz fifth generation SPARC64 microprocessor 2359:"Fujitsu to embiggen iron bigtime with Sparc64-X" 1607:"Sun, Fujitsu launches entry quad-core Sparc box" 793:and has a peak memory bandwidth of 64 GB/s. 2603:. Symposium on VLSI Circuits. pp. 167–168. 2458:A 1.3GHz fifth generation SPARC64 microprocessor 1734:(Press release). Fujitsu Limited. 14 April 2011. 670:(previously called the SPARC64 VI+), code-named 3228:Corporate Headquarters Office Technology System 1871:"Japanese 'K' Computer Is Ranked Most Powerful" 1842:"Japanese supercomputer 'K' is world's fastest" 1626:Morgan, Timothy Prickett (11 September 2009). 2859: 2357:Morgan, Timothy Prickett (4 September 2012). 1698:"Oracle, Fujitsu goose Sparc M3000 entry box" 1395: 1393: 1391: 1232:Morgan, Timothy Prickett (23 February 2006). 1123:ports) and an improved routing architecture. 8: 2383:Morgan, Timothy Prickett (25 January 2013). 2033:Morgan, Timothy Prickett (7 November 2011). 2023:Fujitsu Launches PRIMEHPC FX10 Supercomputer 1668:Morgan, Timothy Prickett (12 January 2010). 1647:Morgan, Timothy Prickett (13 October 2009). 1605:Morgan, Timothy Prickett (28 October 2008). 1345: 1343: 1301:Morgan, Timothy Prickett (9 February 2006). 1258:(15 November 1999). "Hal Makes Sparcs Fly". 1227: 1225: 471: 357: 32: 2370:Morgan, Timothy Prickett (1 October 2012). 1865: 1863: 3082: 3001: 2887: 2866: 2852: 2844: 2810:Fujitsu PRIMEHPC FX100/FX10 Supercomputers 1696:Morgan, Timothy Prickett (12 April 2011). 1570:"Hot Chips: Fujitsu shows off SPARC64 VII" 1511:Morgan, Timothy Prickett (19 April 2007). 1059:Taiwan Semiconductor Manufacturing Company 958:first revealed in the announcement of the 805:and Project Keisoku) initiated by Japan's 38: 2224:Morgan, Timothy Prickett (23 June 2016). 1548:Morgan, Timothy Prickett (17 July 2008). 1466:Morgan, Timothy Prickett (24 June 2004). 1234:"Fujitsu Draws Sparc64 Roadmap Past 2010" 2176:Sparc-Prozessor für 100-Petaflop-Rechner 1029:; and the impending introduction of the 202:by Fujitsu in their PRIMEPOWER servers. 1649:"Sun, Fujitsu crank Sparc64-VII clocks" 1441: 1358: 1221: 1133:International Supercomputing Conference 1075:The XIfx has 34 cores, 32 of which are 1921:(Press release). RIKEN. Archived from 1784: 470: 356: 31: 1771:"Fujitsu unveils world's fastest CPU" 1628:"Sun's Sparc server roadmap revealed" 1349:"SPARC64 V Processor For UNIX Server" 1079:used to run user applications, and 2 225:. It was based on the Fujitsu GS8900 7: 3473: 2906:Fujitsu Computer Products of America 2834:High Performance Processor SPARC64 X 2680:IEEE Journal of Solid-State Circuits 1670:"Sun, Fujitsu juice entry Sparc box" 1453: 889:Physical address range: 41 bits 698:The SPARC64 VII was featured in the 332:, eight-layer copper metallization, 2839:Multi Core Processor SPARC64 Series 2827: (archived April 3, 2019), and 2821:V, VI, VII, VIIIfx, IXfx Extensions 2298:SPARC64 V Processor For UNIX Server 2056:Maruyama, Takumi (29 August 2012). 1533:"SPARC's Still Going Strong", p. 1. 828:Financial crisis of 2007–2008 695:CMOS, copper interconnect process. 268:instructions. Unlike its successor 2214:Agam Shah, PC World, 6 August 2014 1497:Fujitsu Limited (27 March 2007). " 1325:"Fujitsu's SPARC64 V Is Real Deal" 1323:Krewell, Kevin (21 October 2002). 27:Microprocessor designed by Fujitsu 25: 3167: 282:single instruction, multiple data 3472: 3461: 3460: 2986: 1501:, Release 1.3". pp. 45–46. 1162: 459:CMOS process with ten levels of 3162: 2969:International Computers Limited 2256:. 20 April 2017. Archived from 2179:Heise Newsticker, 6 August 2014 1951:(Press release). Archived from 1084:are further organized into two 789:. It connects to 64 GB of 631: 537:Architecture and classification 405:Architecture and classification 209:rating of any SPARC processor. 89:Architecture and classification 982:speculative execution of loads 678:(SMT), which replaces two-way 636:coarse-grained multi-threading 400:1.65 GHz to 2.16 GHz 217:The SPARC64 V is a four-issue 84:1.10 GHz to 1.35 GHz 1: 2805:Fujitsu SPARC Servers Roadmap 2066:10.1109/HOTCHIPS.2012.7476503 1135:in June 2016 that its future 680:coarse-grained multithreading 280:(VIS) instructions, a set of 272:, the SPARC64 V performs the 3176:Supercomputers and servers: 2933:Fujitsu Technology Solutions 922:Translation lookaside buffer 884:Miscellaneous specifications 638:(CMT), which Fujitsu called 3511:Superscalar microprocessors 676:simultaneous multithreading 3532: 2652:10.1109/ISSCC.2013.6487637 2609:10.1109/VLSIC.2010.5560313 2431:10.1109/ISSCC.2003.1234286 1309:. Vol. 3, no. 5. 771:high-performance computing 532:4–6 MB per core 3434: 3052:Fujitsu Siemens Computers 2984: 2692:10.1109/JSSC.2013.2284650 2493:10.1109/ICCD.2003.1240896 1791:: CS1 maint: unfit URL ( 1288:10.1109/HPCA.2003.1183533 1131:Fujitsu announced at the 156:SPARC Enterprise M-Series 37: 2917:Fujitsu Consulting India 2902:Fujitsu Client Computing 2528:10.1109/DSN.2008.4630071 2190:Next Generation PRIMEHPC 1806:Takumi Maruyama (2009). 1111:were replaced with four 640:vertical multi-threading 3501:Fujitsu microprocessors 3012:General Airconditioners 1374:"SPARC64 VI Extensions" 1045:Fujitsu introduced the 684:vertical multithreading 554:Physical specifications 422:Physical specifications 106:Physical specifications 3516:64-bit microprocessors 1049:in August 2014 at the 758: 751: 722:), referred to as the 349:dissipation to ~45 W. 278:Visual Instruction Set 223:out-of-order execution 3506:SPARC microprocessors 3391:Fujitsu's Application 3113:Global Cloud Platform 2929:Fujitsu Semiconductor 2815:Fujitsu SPARC Servers 2466:10.1145/775832.776010 2425:. pp. 246, 491. 2351:Microprocessor Report 2342:Microprocessor Report 2333:Microprocessor Report 2324:Microprocessor Report 2315:Microprocessor Report 2306:Microprocessor Report 2161:Microprocessor Report 2114:Microprocessor Report 2099:Microprocessor Report 2009:Microprocessor Report 1499:SPARC64 VI Extensions 1410:10.1145/775832.776010 1333:Microprocessor Report 1261:Microprocessor Report 1117:Microprocessor Report 1070:Microprocessor Report 785:for a total of eight 757: 738: 504:2150 - 2400 258:arithmetic logic unit 3370:Shiodome City Center 3201:Business computers: 2964:HAL Computer Systems 2925:Fujitsu Laboratories 2829:X / X+ Specification 2196:4 March 2016 at the 1560:on 20 November 2008. 1404:. pp. 702–705. 1068:(HKMG) process. The 1025:E5 and E7 models by 996:memory controllers, 628:silicon on insulator 543:Instruction set 411:Instruction set 338:silicon on insulator 221:microprocessor with 194:, an L1 instruction 180:HAL Computer Systems 95:Instruction set 2730:10.1109/MM.2013.126 2400:. pp. 141–152. 1523:on 3 December 2008. 1478:on 21 October 2004. 477:General information 473: 461:copper interconnect 363:General information 359: 178:In the late 1990s, 47:General information 34: 3076:Products, services 3045:Former and defunct 2996:Joint ventures and 2952:Former and defunct 2911:Fujitsu Consulting 2898:Amdahl Corporation 2775:10.1109/MM.2015.11 2575:10.1109/MM.2010.40 2263:on 29 August 2017. 2200:Fujitsu Ltd., 2014 1875:The New York Times 1586:. Sun Microsystems 1256:Diefendorff, Keith 1211:20 nm process 1174:. You can help by 1143:architecture. The 1113:Hybrid Memory Cube 1109:memory controllers 1086:Core Memory Groups 783:memory controllers 759: 752: 644:fused multiply-add 190:organization with 3488: 3487: 3416:Fujitsu Frontiers 3411:Kawasaki Frontale 3330: 3329: 3070: 3069: 2982: 2981: 2943:Nifty Corporation 2661:978-1-4673-4515-6 2618:978-1-4244-5454-9 2537:978-1-4244-2397-2 2230:The Next Platform 2075:978-1-4673-8879-5 1822:on 8 October 2010 1554:The Unix Guardian 1517:The Unix Guardian 1472:The Unix Guardian 1307:The Unix Guardian 1244:on 12 March 2006. 1238:The Unix Guardian 1192: 1191: 1066:high-κ metal gate 978:branch prediction 851:LINPACK benchmark 837:. Located at the 824:vector processors 803:Kei Soku Keisenki 616: 615: 442: 441: 126: 125: 16:(Redirected from 3523: 3476: 3475: 3464: 3463: 3444:Now wholly owned 3421:Fujitsu Red Wave 3386:Atlas Consortium 3302:SPARC Enterprise 3261: 3083: 3037: 3029: 3021: 3002: 2990: 2919: 2888: 2868: 2861: 2854: 2845: 2819:Fujitsu SPARC64 2794: 2749: 2711: 2673: 2630: 2594: 2549: 2514: 2479: 2452: 2282: 2281: 2279: 2271: 2265: 2264: 2262: 2255: 2247: 2241: 2240: 2238: 2236: 2221: 2215: 2207: 2201: 2186: 2180: 2172: 2166: 2165: 2155: 2144: 2143: 2135: 2129: 2128: 2124: 2118: 2117: 2109: 2103: 2102: 2094: 2088: 2087: 2053: 2044: 2031: 2025: 2020: 2014: 2013: 2003: 1994: 1993: 1992: 1990: 1981:, archived from 1971: 1965: 1964: 1962: 1960: 1941: 1935: 1934: 1932: 1930: 1915: 1909: 1908: 1906: 1904: 1893: 1887: 1886: 1884: 1882: 1867: 1858: 1857: 1855: 1853: 1838: 1832: 1831: 1829: 1827: 1821: 1814: 1803: 1797: 1796: 1790: 1782: 1780: 1778: 1767: 1761: 1760: 1758: 1756: 1742: 1736: 1735: 1728: 1722: 1721: 1714: 1708: 1707: 1693: 1680: 1679: 1665: 1659: 1658: 1644: 1638: 1637: 1623: 1617: 1616: 1602: 1596: 1595: 1593: 1591: 1585: 1577: 1571: 1568: 1562: 1561: 1556:. Archived from 1545: 1534: 1531: 1525: 1524: 1519:. Archived from 1508: 1502: 1495: 1489: 1486: 1480: 1479: 1474:. Archived from 1463: 1457: 1451: 1445: 1439: 1433: 1431: 1397: 1386: 1383: 1377: 1371: 1362: 1356: 1350: 1347: 1338: 1337: 1329: 1320: 1311: 1310: 1298: 1292: 1291: 1276: 1270: 1269: 1252: 1246: 1245: 1240:. Archived from 1229: 1187: 1184: 1166: 1159: 877:register windows 700:SPARC Enterprise 656:SPARC Enterprise 474: 360: 229:microprocessor. 192:superspeculation 42: 35: 21: 3531: 3530: 3526: 3525: 3524: 3522: 3521: 3520: 3491: 3490: 3489: 3484: 3430: 3374: 3358: 3326: 3257: 3216: 3077: 3066: 3040: 3035: 3027: 3019: 2997: 2991: 2978: 2974:Ross Technology 2947: 2938:Glovia Services 2915: 2883: 2877: 2872: 2825:Wayback Machine 2801: 2759: 2714: 2676: 2662: 2640: 2619: 2597: 2559: 2538: 2517: 2503: 2482: 2476: 2455: 2441: 2415: 2407: 2405:Further reading 2296:(August 2004). 2294:Fujitsu Limited 2290: 2285: 2277: 2273: 2272: 2268: 2260: 2253: 2249: 2248: 2244: 2234: 2232: 2223: 2222: 2218: 2208: 2204: 2198:Wayback Machine 2187: 2183: 2173: 2169: 2157: 2156: 2147: 2137: 2136: 2132: 2126: 2125: 2121: 2111: 2110: 2106: 2096: 2095: 2091: 2076: 2055: 2054: 2047: 2032: 2028: 2021: 2017: 2005: 2004: 1997: 1988: 1986: 1985:on 23 June 2011 1973: 1972: 1968: 1958: 1956: 1955:on 23 June 2011 1943: 1942: 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