1213:. Each of the two pipelines of a core can fetch 8 instructions, decode 4 instructions and execute 6 instructions per cycle, and supports 4 SMT threads (for 96 threads per CPU). Each pipeline has an own 32 MB 4-way L1 data cache, and two pipelines share a 64 MB 4-way associative L1 instruction cache and a 512 MB 16-way L2 cache. SPARC64 XII is Fujitsu's first SPARC CPU with L3 cache (32 MB 16-way). The number of 8-lane PCIe 3.0 ports has been doubled to 4 per chip. Memory speed has been increased by 50% to 2400 MT/s, bringing the theoretical combined bandwidth of the 8 DDR4 channels of the chip to 153 GB/s, and the capacity per CPU is up to 1.5 TB across 24 slots. Two CPUs can be connected in a Building Block, and up to 16 Building Blocks can be connected to create a 32-CPU server with up to 48 TB of memory.
238:
stations, two that serve the integer units, one for the address generators, two for the floating-point units, and one for branch instructions. Each integer, address generator and floating-point unit has an eight-entry reserve station. Each reserve station can dispatch an instruction to its execution unit. Which instruction is dispatched firstly depends on operand availability and then its age. Older instructions are given higher priority than newer ones. The reserve stations can dispatch instructions speculatively (speculative dispatch). That is, instructions can be dispatched to the execution units even when their operands are not yet available but will be when execution begins. During stage six, up to six instructions are dispatched.
736:
702:. It is socket-compatible with its predecessor, the SPARC64 VI, and is field-upgradeable. SPARC64 VIIs could coexist, whilst operating at their native clock frequency, alongside SPARC64 VIs. The first versions of the SPARC64 VII were a 2.4 GHz version with a 5 MB L2 cache used in the SPARC Enterprise M4000 and M5000, and a 2.52 GHz version with a 6 MB L2 cache. On 28 October 2008, a 2.52 GHz version with a 5 MB L2 cache was introduced in the SPARC Enterprise M3000. On 13 October 2009, Fujitsu and Sun introduced new versions of the SPARC64 VII (code-named
880:
execution pipeline to access the larger floating-point register file. The 128-bit SIMD instructions from HPC-ACE were implemented by adding two extra floating-point units for a total of four. SIMD execution can perform up four single- or double-precision fused-multiply-add operations (eight FLOPs) per cycle. The number of load queue entries was increased to 20 from 16, and the L1 data cache was halved in size to 32 KB. The number of commit stack entries, which determined the number of instructions that could be in-flight in the back-end, was reduced to 48 from 64.
871:
registers. The SPARC V9 instruction encoding limited the number of registers specifiable to 32. To specify the extra registers, HPC-ACE has a "prefix" instruction that would immediately follow one or two SPARC V9 instructions. The prefix instruction contained (primarily) the portions of the register numbers that could not fit within a SPARC V9 instruction. This extra pipeline stage was where up to four SPARC V9 instructions were combined with up to two prefix instructions in the preceding stage. The combined instructions were then decoded in the next pipeline stage.
198:, a small but very fast 8 KB L1 data cache, and separate L2 caches for instructions and data. It was designed in Fujitsu's CS85 process, a 0.17 ÎĽm CMOS process with six levels of copper interconnect; and would have consisted of 65 million transistors on a 380 mm die. Originally scheduled for a late 2001 release in Fujitsu GranPower servers, it was canceled in mid-2001 when HAL was closed by Fujitsu, and replaced by a Fujitsu design.
2988:
1164:
755:
3462:
727:
approximately 20% increase to overall performance. A 2.66 GHz version was for mid-range M4000 and M5000 models. On 12 April 2011, a 2.86 GHz version with two or four cores and a 5.5 MB L2 cache was announced for the low-end M3000. The VII+ is socket-compatible with its predecessor, the VII. Existing high-end SPARC Enterprise M-Series servers are able to upgrade to the VII+ processors in the field.
1119:, the IXfx was the first processor to use HMCs. The XIfx is connected to 32 GB of memory provided by eight 4 GB HMCs. The HMCs are 16-lane versions, with each lane operating at 15 Gbit/s. Each CMG has two HMC interfaces, and each HMC interface is connected to two HMCs via its own ports. Each CMG has 240 GB/s (120 GB/s in and 120 GB/s out) of memory bandwidth.
3474:
963:
to 12 MB, and increasing peak DDR3 SDRAM memory bandwidth to 85 GB/s. The IXfx operates at 1.848 GHz, has a peak performance of 236.5 GFLOPS, and consumes 110 W for a power efficiency of more than 2 GFLOPS per watt. It consisted of 1 billion transistors and was implemented in a 40 nm CMOS process with copper interconnects.
40:
284:(SIMD) instructions. All instructions are pipelined except for divide and square root, which are executed using iterative algorithms. The FMA instruction is implemented by reading three operands from the operand register, multiplying two of the operands, forwarding the result and the third operand to the adder, and adding them to produce the final result.
642:(VMT). In CMT, which thread is executed is determined by time-sharing, or if the thread is executing a long-latency operation, then execution is switched to the other thread. The addition of CMT required duplication of the program counter and the control, integer, and floating-point registers so there is one set of each for every thread. A floating-point
1092:), each consisting of 16 compute cores and 1 assistant core sharing a 12 MB L2 unified cache. The division of the cores into CMGs enabled 34 cores to be integrated on a single die by easing the implementation of cache coherence and avoiding the need for the L2 cache to be shared between 34 cores. The two CMGs share the memory through a
247:
contains a subset of the eight register windows, the previous, current and next register windows. Its purpose is reduce the size of register file so that the microprocessor can operate at higher clock frequencies. The floating-point register file contains 64 entries and has six read ports and two write ports.
1205:, L1 instruction cache and L2 cache, and as a result the single-threaded performance is almost unchanged from SPARC64 X. SPARC64 XII operates at up to 4.25 GHz base frequency and 4.35 GHz boost frequency. The size of the chip is 25.8mm Ă— 30.8mm (795mm), containing 5.45 billion transistors made on
1083:
used to run the operating system and other system services. The delegation of user applications and operating system to dedicated cores improves performance by ensuring that the private caches of the compute cores are not shared with or disrupted by non-application instructions and data. The 34 cores
246:
The register files are read during stage seven. The SPARC architecture has separate register files for integer and floating-point instructions. The integer register file has eight register windows. The JWR (Joint Work
Register) contains 64 entries and has eight read ports and two write ports. The JWR
962:
supercomputer on 7 November 2011. It, along with the PRIMEHPC FX10, is a commercialization of the technologies that first appeared in the VIIIfx and K computer. Compared to the VIIIfx, organizational improvements included doubling the number of cores was to 16, doubling the amount of shared L2 cache
874:
The back-end was also heavily modified. The number of reservation station entries for branch and integer instructions were reduced to six and ten, respectively. Both the integer and floating-point register files had registers added to them: the integer register file gained 32, and there were a total
975:
is a 16-core server microprocessor announced in 2012 and used in
Fujitsu's M10 servers (which are also marketed by Oracle). The SPARC64 X is based on the SPARC64 VII+ with significant enhancements to its core and chip organization. The cores were improved by the inclusion of a pattern history table
879:
defined by SPARC V9, but are always accessible via the prefix instruction; and the 256 floating-point registers could be used by both scalar floating-point instructions and by both integer and floating-point SIMD instructions. An extra pipeline stage was added to the beginning of the floating-point
653:
The SPARC64 VI was originally to have been introduced in mid-2004 in
Fujitsu's PrimePower servers. Development of the PrimerPowers were canceled after Fujitsu and Sun Microsystems announced in June 2004 that they would collaborate on new servers called the Advanced Product Line (APL). These servers
237:
The SPARC64 V fetches up to eight instructions from the instruction cache during the first stage and places them into a 48-entry instruction buffer. In the next stage, four instructions are taken from this buffer, decoded and issued to the appropriate reserve stations. The SPARC64 V has six reserve
201:
The first
Fujitsu SPARC64 Vs were fabricated in December 2001. They operated at 1.1 to 1.35 GHz. Fujitsu's 2003 SPARC64 roadmap showed that the company planned a 1.62 GHz version for release in late 2003 or early 2004, but it was canceled in favor of the SPARC64 V+. The SPARC64 V was used
1016:
is an enhanced SPARC64 X processor announced in 2013. It features minor improvements to the core organization, and a higher 3.5 GHz clock frequency obtained through better circuit design and layout. It contained 2.99 billion transistors, measured 24 mm by 25 mm (600 mm), and is
1122:
The XIfx replaced the ten SERDES channels to an external Tofu interconnect controller with a ten-port integrated controller for the second-generation Tofu2 interconnect. Tofu2 is a 6D mesh/torus network with a 25 GB/s full-duplex bandwidth (12.5 GB/s per direction, 125 GB/s for ten
649:
The cores share a 6 MB on-die unified L2 cache. The L2 cache is 12-way set associative and has 256-byte lines. The cache is accessed via two unidirectional buses, a 256-bit read bus and a 128-bit write bus. The SPARC64 VI has a new system bus, the
Jupiter Bus. The SPARC64 VI consisted of 540
287:
Results from the execution units and loads are not written to the register file. To maintain program order, they are written to update buffers, where they reside until committed. The SPARC64 V has separate update buffers for integer and floating-point units. Both have 32 entries each. The integer
303:
The level 1 (L1) caches each have a capacity of 128 KB. They are both two-way set associative and have 64-byte line size. They are virtually indexed and physically tagged. The instruction cache is accessed via a 256-bit bus. The data cache is accessed with two 128-bit buses. The data cache
870:
reduced to two from eight; and an extra pipeline stage was inserted before the instruction decoder. This stage accommodated the greater number of integer and floating-point registers defined by HPC-ACE. The SPARC V9 architecture was designed to have only 32 integer and 32 floating-point number
726:
by Oracle, is a further development of the SPARC64 VII. The clock frequency was increased up to 3 GHz and the L2 cache size was doubled to 12 MB. This version was announced on 2 December 2010 for the high-end SPARC Enterprise M8000 and M9000 servers. These improvements resulted in an
451:
The first SPARC64 V+, a 1.89 GHz version, was shipped in
September 2004 in the Fujitsu PrimePower 650 and 850. In December 2004, a 1.82 GHz version was shipped in the PrimePower 2500. These versions have a 3 MB L2 cache. In February 2006, four versions were introduced: 1.65 and
865:
The VIIIfx core is based on that of the SPARC64 VII with numerous modifications for HPC, namely High
Performance Computing-Arithmetic Computational Extensions (HPC-ACE) a Fujitsu-designed extension to the SPARC V9 architecture. The front-end had coarse-grained multi-threading removed, the L1
348:
At 1.3 GHz, the SPARC64 V has a power dissipation of 34.7 W. The
Fujitsu PrimePower servers that use the SPARC64 V supply a slightly higher voltage the microprocessor to enable it to operate at 1.35 GHz. The increased power supply voltage and operating frequency increased the power
1103:
units to 256 bits and added new SIMD instructions. Compared to the SPARC64 IXfx, the XIfx has an improvement of a factor of 3.2 for double precision and 6.1 for single precision. To complement the increased width of the SIMD units, the L1 cache bandwidth was increased to 4.4 TB/s.
830:, Hitachi and NEC announced in May 2009 that they would leave the project because manufacturing the hardware they were responsible for would result in financial losses for them. Afterwards, Fujitsu redesigned the supercomputer to use the VIIIfx as its only processor type.
690:
features; the integer register file is now protected by ECC, and the number of error checkers has been increased to around 3,400. It consists of 600 million transistors, is 21.31 mm Ă— 20.86 mm (444.63 mm) large, and is fabricated by
Fujitsu in its
706:), a 2.53 GHz version with a 5.5 MB L2 cache for the M4000 and M5000, and a 2.88 GHz version with a 6 MB L2 cache for the M8000 and M9000. On 12 January 2010, a 2.75 GHz version with a 5 MB L2 cache was introduced in the M3000.
158:
servers. In addition to servers, a version of the SPARC64 VII was also used in the commercially available
Fujitsu FX1 supercomputer. As of October 2017, the SPARC64 XII is the latest server processor, and it is used in the Fujitsu and Oracle M12 servers.
2715:
Yoshida, Toshio; Maruyama, Takumi; Akizuki, Yasunobu; Kan, Ryuji; Kiyota, Naohiro; Ikenishi, Kiyoshi; Itou, Shigeki; Watahiki, Tomoyuki; Okano, Hiroshi (November–December 2013). "Sparc64 X: Fujitsu's New-Generation 16-Core Processor for Unix Servers".
288:
register has eight read ports and four write ports. Half of the write ports are used for results from the integer execution units and the other half by data returned by loads. The floating-point update buffer has six read ports and four write ports.
2641:
Kan, Ryuji; Tanaka, Tomohiro; Sugizaki, Go; Nishiyama, Ryuichi; Sakabayashi, Sota; Koyanagi, Yoichi; Iwatsuki, Ryuji; Hayasaka, Kazumi; Uemura, Taiki; Ito, Gaku; Ozeki, Yoshitomo; Adachi, Hiroyuki; Furuya, Kazuhiro; Motokurumada, Tsuyoshi (2013).
2560:
Maruyama, Takumi; Yoshida, Toshio; Kan, Ryuji; Yamazaki, Iwao; Yamamura, Shuji; Takahashi, Noriyuki; Hondou, Mikio; Okano, Hiroshi (March–April 2010). "Sparc64 VIIIfx: A New-Generation Octocore Processor for Petascale Computing".
2760:
Yoshida, Toshio; Hondou, Mikio; Tabata, Takekazu; Kan, Ryuji; Kiyota, Naohiro; Kojima, Hiroyuki; Hosoe, Koji; Okano, Hiroshi (March–April 2015). "Sparc64 XIfx: Fujitsu's Next-Generation Processor for High-Performance Computing".
315:
The microprocessor has a 128-bit system bus that operates at 260 MHz. The bus can operate in two modes, single-data rate (SDR) or double-data (DDR) rate, yielding a peak bandwidth of 4.16 or 8.32 GB/s, respectively.
2677:
Kan, Ryuji; Tanaka, Tomohiro; Sugizaki, Go; Ishizaka, Kinya; Nishiyama, Ryuichi; Sakabayashi, Sota; Koyanagi, Yoichi (January 2014). "The 10th Generation 16-Core SPARC64 Processor for Mission Critical UNIX Server".
291:
Commit takes place during stage ten at the earliest. The SPARC64 V can commit up to four instructions per cycle. During stage eleven, results are written to the register file, where it becomes visible to software.
263:
The two floating-point units (FPUs) are designated FLA and FLB. Each FPU contains an adder and a multiplier, but only FLA has a graphics unit attached. They execute add, subtract, multiply, divide, square root and
260:(ALU) and a shift unit, but only EXA has multiply and divide units. Loads and stores are executed by two address generators (AGs) designated AGA and AGB. These are simple ALUs used to calculate virtual addresses.
1807:
773:(HPC). As a result, the VIIIfx did not succeed the VII, but existed concurrently with it. It consists of 760 million transistors, measures 22.7 mm by 22.6 (513.02 mm;), is fabricated in Fujitu's
255:
Execution begins during stage nine. There are six execution units, two for integer, two for loads and stores, and two for floating-point. The two integer execution units are designated EXA and EXB. Both have an
2598:
Okano, Hiroshi; Kawabe, Yukihito; Kan, Ryuji; Yoshida, Toshio; Yamazaki, Iwao; Sakurai, Hitoshi; Hondou, Mikio; Matsui, Nobuyki; Yamashita, Hideo; Nakada, Tatsumi; Maruyama, Takumi; Asakawa, Takeo (2010).
687:
2416:
Ando, H.; Yoshida, Y.; Inoue, A.; Sugiyama, I.; Asakawa, T.; Morita, K.; Muta, T.; Motokurumada, T.; Okada, S.; Yamashita, H.; Satsukawa, Y.; Konmoto, A.; Yamashita, R.; Sugiyama, H. (13 February 2003).
992:, and decimal floating-point number arithmetic and conversion functions. The 16 cores share a unified, 24 MB, 24-way set-associative L2 cache. Chip organization improvements include four integrated
809:
in January 2006. The project aimed to produce the world's fastest supercomputer with performance of over 10 PFLOPS by March 2011. The companies contracted to develop the supercomputer were Fujitsu,
448:, code-named "Olympus-B", is a further development of the SPARC64 V. Improvements over the SPARC64 V included higher clock frequencies of 1.82–2.16 GHz and a larger 3 or 4 MB L2 cache.
806:
658:. The SPARC64 VI processors featured in the SPARC Enterprise at its announcement were a 2.15 GHz version with a 5 MB L2 cache, and 2.28 and 2.4 GHz versions with 6 MB L2 caches.
2250:
2456:
Ando, H.; Yoshida, Y.; Inoue, A.; Sugiyama, I.; Asakawa, T.; Morita, K.; Muta, T.; Motokurumada, T.; Okada, S.; Yamashita, H.; Satsukawa, Y.; Konmoto, A.; Yamashita, R.; Sugiyama, H. (2003).
452:
1.98 GHz versions with 3 MB L2 caches shipped in the PrimePower 250 and 450; and 2.08 and 2.16 GHz versions with 4 MB L2 caches shipped in mid-range and high-end models.
205:
The SPARC64 V was first presented at Microprocessor Forum 2002. At introduction, it had the highest clock frequency of both SPARC and 64-bit server processors in production; and the highest
1004:
controllers. The SPARC64 X contains 2.95 billion transistors, measures 23.5 mm by 25 mm (587.5 mm), and is fabricated in a 28 nm CMOS process with copper interconnects.
1099:
The XIfx core was based on the SPARC64 X+ with organizational improvements. The XIfx implements an improved version of the HPC-ACE extensions (HPC-ACE2), which doubled the width of the
300:
The SPARC64 V has two-level cache hierarchy. The first level consists of two caches, an instruction cache and a data cache. The second level consists of an on-die unified cache.
1201:
that was launched the same year, each of the twelve cores consists of two separate pipelines, and the only resources shared between SPARC64 XII core's pipelines are the
984:, more execution units, support for the HPC-ACE extension (originally from the SPARC64 VIIIfx), deeper pipeline for a 3.0 GHz clock frequency, and accelerators for
1816:
333:
826:. The Fujitsu-designed VIIIfx was to have been the scalar processor, with the vector processor to have been jointly designed by Hitachi and NEC. However, due to the
3227:
304:
consists of eight banks separated by 32-bit boundaries. It uses a write-back policy. The data cache writes to the L2 cache with its own 128-bit unidirectional bus.
150:
The servers series are the SPARC64 V+, VI, VI+, VII, VII+, X, X+ and XII. The SPARC64 VI and its successors up to the VII+ were used in the Fujitsu and Sun (later
1770:
2193:
1918:
2257:
2274:
1058:
2838:
2820:
1057:. The XIfx operates at 2.2 GHz and has a peak performance of 1.1 TFLOPS. It consists of 3.75 billion transistors and is fabricated by the
1132:
866:
instruction cache halved in size to 32 KB; and the number of branch target address cache (BTAC) entries reduced to 1,024 from 8,192, and its
455:
It contained approximately 400 million transistors on an 18.46 mm by 15.94 mm die for an area of 294.25 mm. It was fabricated in a
679:
635:
2833:
2659:
2616:
2535:
2073:
3510:
2905:
735:
2396:
Sakamoto, Mariko et al. (2003). "Microarchitecture and Performance Analysis of a SPARC-V9 Microprocessor for Enterprise Server Systems".
1000:
four-way symmetrical multiprocessing, ten SERDES channels for symmetrical multiprocessing scalability to 64 sockets, and two integrated
674:, is a further development of the SPARC64 VI announced in July 2008. It is a quad-core microprocessor. Each core is capable of two-way
170:. As of July 2016, the SPARC64 XIfx is the latest supercomputer processor, and it is used in the Fujitsu PRIMEHPC FX100 supercomputer.
1841:
827:
162:
The supercomputer series was based on the SPARC64 VII, and are the SPARC64 VIIfx, IXfx, and XIfx. The SPARC64 VIIIfx was used in the
2865:
2500:
2473:
2438:
1100:
786:
281:
2209:
781:
and a typical power consumption of 58 W at 30 °C for an efficiency of 2.2 GFLOPS/W. The VIIIfx has four integrated
3500:
325:
2174:
1549:
1512:
1467:
1233:
186:
as the SPARC64 V. First announced at Microprocessor Forum 1999, the HAL SPARC64 V would have operated 1 GHz and had a wide
3515:
2968:
1944:
3505:
3122:
3092:
1417:
2828:
2804:
777:
CMOS process with copper interconnects, and has 1,271 I/O pins. The VIIIfx has a peak performance at 2 GHz of 128
2225:
3112:
1792:
2601:
Fine grained power analysis and low-power techniques of a 128GFLOPS/58W SPARC64 VIIIfx processor for peta-scale computing
2932:
1202:
921:
542:
410:
94:
1731:
1717:
1324:
675:
276:
with separate multiplication and addition operations, thus with up to two rounding errors. The graphics unit executes
147:. The SPARC64 V was the basis for a series of successive processors designed for servers, and later, supercomputers.
2809:
2034:
2384:
770:
2188:
3051:
654:
were scheduled to be introduced in mid-2006, but were delayed until April 2007, when they were introduced as the
1974:
1922:
324:
The SPARC64 V consisted of 191 million transistors, of which 19 million are contained in logic circuits. It was
3075:
2916:
3390:
2371:
1745:
1697:
1385:"Microarchitecture and Performance Analysis of a SPARC-V9 Microprocessor for Enterprise Server Systems", p. 4.
2022:
1896:
1581:"Sun SPARC Enterprise Server Family Architecture: Flexible, Mainframe-Class Compute Power for the Datacenter"
1147:
will implement extensions to the ARMv8 architecture, equivalent to HPC-ACE2, that Fujitsu is developing with
622:, code-named Olympus-C, is a two-core processor (the first multi-core SPARC64 processor) which succeeded the
3335:
3011:
496:
392:
76:
1197:
was launched in 2017 with Fujitsu's SPARC M12 servers. It nominally features 12 cores, but just like IBM's
307:
The second level cache has a capacity of 1 or 2 MB and the set associativity depends on the capacity.
3258:
3179:
2138:
Prickett, Timothy Morgan (8 April 2014). "Oracle Unfolds Sparc Roadmap, Fujitsu boosts SPARC64 X Clocks".
1373:
849:
Project Committee announced that the K computer (still incomplete with only 68,544 processors) topped the
630:(SOI) process, which enabled two cores and an L2 cache to be integrated on a die. Each core is a modified
277:
222:
1648:
3157:
2858:
2358:
2350:
2341:
2332:
2323:
2314:
2305:
2160:
2008:
1332:
1260:
981:
857:, realizing 93% of its peak performance, making it the fastest supercomputer in the world at that time.
257:
191:
2423:
Solid-State Circuits Conference, 1997. Digest of Technical Papers. 43rd ISSCC., 1997 IEEE International
1627:
3127:
2518:
Ando, Hisashige; Kan, Ryuji; Tosaka, Yoshiharu; Takahisa, Keiji; Hatanaka, Kichiji (24–27 June 2008).
1669:
3369:
2963:
2127:
Yoshida, Toshio (27 August 2013). "SPARC64 X+: Fujitsu's Next Generation Processor for UNIX servers".
1580:
1280:
Microarchitecture and Performance Analysis of a SPARC-V9 Microprocessor for Enterprise Server Systems
1065:
627:
578:
427:
337:
179:
111:
2483:
Ito, N.; Komatsu, H.; Tanamura, Y.; Yamashita, R.; Sugiyama, H.; Sugiyama, Y.; Hamamura, H. (2003).
1107:
Improvements to the SoC organization were to the memory and interconnect interfaces. The integrated
3478:
2937:
460:
2814:
2897:
2786:
2741:
2703:
2586:
2079:
1423:
1136:
1112:
1072:
estimated the die to have an area of 500 mm; and a typical power consumption of 200 W.
643:
226:
151:
1870:
686:(VMT) by Fujitsu. Thus, it can execute eight threads simultaneously. Other changes include more
1282:. Ninth International Symposium on High-Performance Computer Architecture, 2003 (HPCA-9 2003).
3415:
3410:
3286:
2942:
2778:
2733:
2695:
2665:
2655:
2622:
2612:
2578:
2541:
2531:
2506:
2496:
2469:
2444:
2434:
2069:
1786:
1606:
1413:
1400:
Ando, Hisashige; et al. (June 2003). "A 1.3GHz fifth generation SPARC64 microprocessor".
1255:
1115:(HMC) interfaces for decreased memory latency and improved memory bandwidth. According to the
1108:
850:
782:
340:(SOI) process. The die measured 18.14 mm by 15.99 mm for a die area of 290 mm.
941:
Page sizes: 8 KB, 64 KB, 512 KB, 4 MB, 32 MB, 256 MB, 2 GB
273:
265:
3466:
3420:
3385:
3301:
3209:
3132:
2851:
2770:
2725:
2687:
2647:
2604:
2570:
2523:
2488:
2461:
2426:
2061:
1405:
1283:
977:
823:
819:
699:
655:
559:
155:
2987:
2058:
SPARC64™ X: Fujitsu's new generation 16 core processor for the next generation UNIX servers
1062:
3204:
2973:
2824:
2293:
2197:
1018:
1001:
955:
904:
876:
2522:. 2008 IEEE International Conference on Dependable Systems and Networks. pp. 62–69.
2398:
Proceedings of the 9th International Symposium on High-Performance Computer Architecture
3405:
3400:
3353:
3343:
3321:
3252:
1053:
symposium. It is used in the Fujitsu PRIMEHPC FX100 supercomputer, which succeeded the
818:. The supercomputer was originally envisioned to have a hybrid architecture containing
754:
747:
650:
million transistors. The die measures 20.38 mm by 20.67 mm (421.25 mm).
140:
1163:
3494:
3237:
3147:
2790:
2590:
1809:
SPARC64 VIIIfx: Fujitsu's New Generation Octo Core Processor for PETA Scale computing
1557:
1520:
1475:
1302:
1241:
1210:
1144:
1054:
959:
845:, Japan; it obtains its performance from 88,128 VIIIfx processors. In June 2011, the
329:
167:
2707:
2083:
1952:
907:
data, 32 KB two-way set-associative instruction (128-byte cache line), sectored
801:
The VIIIfx was developed for the Next-Generation Supercomputer Project (also called
3425:
3348:
3281:
3107:
2745:
2389:
2376:
2363:
2039:
1702:
1674:
1653:
1632:
1611:
1427:
1148:
985:
743:
692:
567:
456:
2065:
931:
A 16-entry micro-TLB; and 256-entry, four-way set-associative TLB for instructions
2520:
Validation of hardware error recovery mechanisms for the SPARC64 V microprocessor
875:
of 256 floating-point registers. The extra integer registers are not part of the
623:
3395:
3306:
3291:
3024:
610:
218:
195:
187:
183:
2651:
2608:
2430:
2251:"SPARC64™ XII: Fujitsu's latest 12 Core Processor for Mission Critical Servers"
1017:
fabricated in the same process as the SPARC64 X. On 8 April 2014, 3.7 GHz
3316:
3311:
3184:
3152:
2691:
2492:
1287:
997:
993:
834:
790:
740:
499:
395:
269:
163:
79:
2782:
2737:
2699:
2669:
2626:
2582:
2545:
2527:
2510:
2448:
3061:
3032:
2644:
A 10th generation 16-core SPARC64 processor for mission-critical UNIX server
1945:"Japan Reclaims Top Ranking on Latest TOP500 List of World's Supercomputers"
1050:
867:
833:
By 2010, the supercomputer that would be built by the project was named the
515:
1139:
supercomputer will feature processors of its own design that implement the
17:
2465:
2097:
Halfhill, Tom R. (17 September 2012). "Fujitsu and Oracle Ignite SPARCs".
1409:
39:
3247:
3189:
3056:
1746:"Ellison: Sparc T4 due next year: Sparc64-VII+ clock and cache bumps now"
1718:"Fujitsu and Oracle Enhance SPARC Enterprise M-Series with New Processor"
989:
911:
900:
521:
415:
99:
2729:
2158:
Halfhill, Tom R. (22 September 2014). "Sparc64 XIfx Uses Memory Cubes".
3016:
2924:
2910:
2874:
2774:
2574:
2112:
Gwennap, Linley (7 October 2013). "Fujitsu, Oracle Processors Evolve".
2006:
Byrne, Joseph (5 December 2011). "Sparc64 IXfx Burns Through FP Code".
811:
379:
144:
63:
2646:. IEEE International Solid-State Circuits Conference. pp. 60–61.
2487:. 21st International Conference on Computer Design. pp. 204–210.
2485:
A physical design methodology for 1.3 GHz SPARC 64 microprocessor
1773:. The Inquirer. 14 May 2009. Archived from the original on 17 May 2009
646:(FMA) instruction was also added, the first SPARC processor to do so.
3242:
3232:
3137:
3102:
3097:
2303:
Krewell, Kevin (24 November 2003). "Fujitsu Makes SPARC See Double".
1982:
1198:
1093:
1030:
954:
is an improved version of the SPARC64 VIIIfx designed by Fujitsu and
854:
846:
778:
626:. It is fabricated by Fujitsu in a 90 nm, 10-layer copper, CMOS
2348:
McGhan, Harlan (23 October 2006). "SPARC64 VI Ready for PrimeTime".
2339:
McGhan, Harlan (25 September 2006). "The Sun-Fujitsu APL Alliance".
1815:. Proceedings of Hot Chips 21. IEEE Computer Society. Archived from
2275:"Fujitsu SPARC M12 and Fujitsu M10 Server Architecture White Paper"
1732:"Fujitsu and Oracle Deliver Enhanced SPARC Enterprise M3000 Server"
1488:"Fujitsu-Siemens Cranks the Clock on Sparc V Chips for PrimePowers"
1303:"Fujitsu-Siemens Cranks the Clock on Sparc V Chips for PrimePowers"
934:
A 512-entry, four-way set-associative TLB for data, no victim cache
769:) is an eight-core processor based on the SPARC64 VII designed for
634:
processor. One of the main improvements is the addition of two-way
3296:
3276:
2958:
1140:
1026:
838:
774:
753:
734:
547:
137:
3439:
Now integrated into other Fujitsu divisions or business groupings
2330:
Krewell, Kevin (14 November 2005). "SPARC's Still Going Strong".
3271:
3266:
3117:
1206:
1022:
842:
206:
2847:
1550:"Fujitsu and Sun Flex Their Quads with New Sparc Server Lineup"
1158:
1034:
1021:
parts became available in response to the introduction of new
914:
12-way set-associative (128-byte line), index-hashed, sectored
815:
807:
Ministry of Education, Culture, Sports, Science and Technology
1975:"K computer, SPARC64 VIIIfx 2.0 GHz, Tofu interconnect"
182:, a subsidiary of Fujitsu, was designing a successor to the
2421:. 2003 IEEE International Solid-State Circuits Conference.
1402:
Proceedings of the 40th annual Design Automation Conference
746:
featuring four SPARC64 VIIIfx processors (under the larger
2843:
2372:"Fujitsu, Oracle pair up on future 'Athena' Sparc64 chips"
841:'s Advanced Institute for Computational Science (AICS) in
2060:. 2012 IEEE Hot Chips 24 Symposium (HCS). pp. 1–20.
1513:"Fujitsu, Sun Deliver Joint Sparc Enterprise Server Line"
1919:"Supercomputer "K computer" Takes First Place in World"
1897:"Supercomputer "K computer" Takes First Place in World"
1369:
1367:
1175:
2385:"Fujitsu launches 'Athena' Sparc64-X servers in Japan"
2321:
Krewell, Kevin (25 October 2004). "SPARC Turns 90nm".
2153:
2151:
2149:
2051:
2049:
2312:
Krewell, Kevin (24 June 2004). "SPARC's New Roadmap.
2035:"Fujitsu readies 23 petaflops Sparc FX10 super beast"
166:, and the SPARC64 IXfx in the commercially available
2211:
Fujitsu guns for faster supercomputers with new chip
1691:
1689:
1687:
1685:
1376:
page 56, Fujitsu Limited, Release 1.3, 27 March 2007
3378:
3362:
3334:
3220:
3085:
3074:
3044:
3004:
2995:
2951:
2890:
2881:
2001:
1999:
1543:
1541:
1539:
1318:
1316:
606:
598:
593:
577:
558:
553:
541:
536:
528:
513:
508:
494:
489:
481:
476:
426:
421:
409:
404:
390:
385:
375:
367:
362:
334:
complementary metal–oxide–semiconductor
110:
105:
93:
88:
74:
69:
59:
51:
46:
2460:. Design Automation Conference. pp. 702–705.
2226:"Inside Japan's Future Exascale ARM Supercomputer"
1720:(Press release). Fujitsu Limited. 2 December 2010.
1468:"Fujitsu-Siemens Upgrades PrimePower Unix Servers"
2419:A 1.3 GHz fifth generation SPARC64 microprocessor
2359:"Fujitsu to embiggen iron bigtime with Sparc64-X"
1607:"Sun, Fujitsu launches entry quad-core Sparc box"
793:and has a peak memory bandwidth of 64 GB/s.
2603:. Symposium on VLSI Circuits. pp. 167–168.
2458:A 1.3GHz fifth generation SPARC64 microprocessor
1734:(Press release). Fujitsu Limited. 14 April 2011.
670:(previously called the SPARC64 VI+), code-named
3228:Corporate Headquarters Office Technology System
1871:"Japanese 'K' Computer Is Ranked Most Powerful"
1842:"Japanese supercomputer 'K' is world's fastest"
1626:Morgan, Timothy Prickett (11 September 2009).
2859:
2357:Morgan, Timothy Prickett (4 September 2012).
1698:"Oracle, Fujitsu goose Sparc M3000 entry box"
1395:
1393:
1391:
1232:Morgan, Timothy Prickett (23 February 2006).
1123:ports) and an improved routing architecture.
8:
2383:Morgan, Timothy Prickett (25 January 2013).
2033:Morgan, Timothy Prickett (7 November 2011).
2023:Fujitsu Launches PRIMEHPC FX10 Supercomputer
1668:Morgan, Timothy Prickett (12 January 2010).
1647:Morgan, Timothy Prickett (13 October 2009).
1605:Morgan, Timothy Prickett (28 October 2008).
1345:
1343:
1301:Morgan, Timothy Prickett (9 February 2006).
1258:(15 November 1999). "Hal Makes Sparcs Fly".
1227:
1225:
471:
357:
32:
2370:Morgan, Timothy Prickett (1 October 2012).
1865:
1863:
3082:
3001:
2887:
2866:
2852:
2844:
2810:Fujitsu PRIMEHPC FX100/FX10 Supercomputers
1696:Morgan, Timothy Prickett (12 April 2011).
1570:"Hot Chips: Fujitsu shows off SPARC64 VII"
1511:Morgan, Timothy Prickett (19 April 2007).
1059:Taiwan Semiconductor Manufacturing Company
958:first revealed in the announcement of the
805:and Project Keisoku) initiated by Japan's
38:
2224:Morgan, Timothy Prickett (23 June 2016).
1548:Morgan, Timothy Prickett (17 July 2008).
1466:Morgan, Timothy Prickett (24 June 2004).
1234:"Fujitsu Draws Sparc64 Roadmap Past 2010"
2176:Sparc-Prozessor fĂĽr 100-Petaflop-Rechner
1029:; and the impending introduction of the
202:by Fujitsu in their PRIMEPOWER servers.
1649:"Sun, Fujitsu crank Sparc64-VII clocks"
1441:
1358:
1221:
1133:International Supercomputing Conference
1075:The XIfx has 34 cores, 32 of which are
1921:(Press release). RIKEN. Archived from
1784:
470:
356:
31:
1771:"Fujitsu unveils world's fastest CPU"
1628:"Sun's Sparc server roadmap revealed"
1349:"SPARC64 V Processor For UNIX Server"
1079:used to run user applications, and 2
225:. It was based on the Fujitsu GS8900
7:
3473:
2906:Fujitsu Computer Products of America
2834:High Performance Processor SPARC64 X
2680:IEEE Journal of Solid-State Circuits
1670:"Sun, Fujitsu juice entry Sparc box"
1453:
889:Physical address range: 41 bits
698:The SPARC64 VII was featured in the
332:, eight-layer copper metallization,
2839:Multi Core Processor SPARC64 Series
2827: (archived April 3, 2019), and
2821:V, VI, VII, VIIIfx, IXfx Extensions
2298:SPARC64 V Processor For UNIX Server
2056:Maruyama, Takumi (29 August 2012).
1533:"SPARC's Still Going Strong", p. 1.
828:Financial crisis of 2007–2008
695:CMOS, copper interconnect process.
268:instructions. Unlike its successor
2214:Agam Shah, PC World, 6 August 2014
1497:Fujitsu Limited (27 March 2007). "
1325:"Fujitsu's SPARC64 V Is Real Deal"
1323:Krewell, Kevin (21 October 2002).
27:Microprocessor designed by Fujitsu
25:
3167:
282:single instruction, multiple data
3472:
3461:
3460:
2986:
1501:, Release 1.3". pp. 45–46.
1162:
459:CMOS process with ten levels of
3162:
2969:International Computers Limited
2256:. 20 April 2017. Archived from
2179:Heise Newsticker, 6 August 2014
1951:(Press release). Archived from
1084:are further organized into two
789:. It connects to 64 GB of
631:
537:Architecture and classification
405:Architecture and classification
209:rating of any SPARC processor.
89:Architecture and classification
982:speculative execution of loads
678:(SMT), which replaces two-way
636:coarse-grained multi-threading
400:1.65 GHz to 2.16 GHz
217:The SPARC64 V is a four-issue
84:1.10 GHz to 1.35 GHz
1:
2805:Fujitsu SPARC Servers Roadmap
2066:10.1109/HOTCHIPS.2012.7476503
1135:in June 2016 that its future
680:coarse-grained multithreading
280:(VIS) instructions, a set of
272:, the SPARC64 V performs the
3176:Supercomputers and servers:
2933:Fujitsu Technology Solutions
922:Translation lookaside buffer
884:Miscellaneous specifications
638:(CMT), which Fujitsu called
3511:Superscalar microprocessors
676:simultaneous multithreading
3532:
2652:10.1109/ISSCC.2013.6487637
2609:10.1109/VLSIC.2010.5560313
2431:10.1109/ISSCC.2003.1234286
1309:. Vol. 3, no. 5.
771:high-performance computing
532:4–6 MB per core
3434:
3052:Fujitsu Siemens Computers
2984:
2692:10.1109/JSSC.2013.2284650
2493:10.1109/ICCD.2003.1240896
1791:: CS1 maint: unfit URL (
1288:10.1109/HPCA.2003.1183533
1131:Fujitsu announced at the
156:SPARC Enterprise M-Series
37:
2917:Fujitsu Consulting India
2902:Fujitsu Client Computing
2528:10.1109/DSN.2008.4630071
2190:Next Generation PRIMEHPC
1806:Takumi Maruyama (2009).
1111:were replaced with four
640:vertical multi-threading
3501:Fujitsu microprocessors
3012:General Airconditioners
1374:"SPARC64 VI Extensions"
1045:Fujitsu introduced the
684:vertical multithreading
554:Physical specifications
422:Physical specifications
106:Physical specifications
3516:64-bit microprocessors
1049:in August 2014 at the
758:
751:
722:), referred to as the
349:dissipation to ~45 W.
278:Visual Instruction Set
223:out-of-order execution
3506:SPARC microprocessors
3391:Fujitsu's Application
3113:Global Cloud Platform
2929:Fujitsu Semiconductor
2815:Fujitsu SPARC Servers
2466:10.1145/775832.776010
2425:. pp. 246, 491.
2351:Microprocessor Report
2342:Microprocessor Report
2333:Microprocessor Report
2324:Microprocessor Report
2315:Microprocessor Report
2306:Microprocessor Report
2161:Microprocessor Report
2114:Microprocessor Report
2099:Microprocessor Report
2009:Microprocessor Report
1499:SPARC64 VI Extensions
1410:10.1145/775832.776010
1333:Microprocessor Report
1261:Microprocessor Report
1117:Microprocessor Report
1070:Microprocessor Report
785:for a total of eight
757:
738:
504:2150 - 2400
258:arithmetic logic unit
3370:Shiodome City Center
3201:Business computers:
2964:HAL Computer Systems
2925:Fujitsu Laboratories
2829:X / X+ Specification
2196:4 March 2016 at the
1560:on 20 November 2008.
1404:. pp. 702–705.
1068:(HKMG) process. The
1025:E5 and E7 models by
996:memory controllers,
628:silicon on insulator
543:Instruction set
411:Instruction set
338:silicon on insulator
221:microprocessor with
194:, an L1 instruction
180:HAL Computer Systems
95:Instruction set
2730:10.1109/MM.2013.126
2400:. pp. 141–152.
1523:on 3 December 2008.
1478:on 21 October 2004.
477:General information
473:
461:copper interconnect
363:General information
359:
178:In the late 1990s,
47:General information
34:
3076:Products, services
3045:Former and defunct
2996:Joint ventures and
2952:Former and defunct
2911:Fujitsu Consulting
2898:Amdahl Corporation
2775:10.1109/MM.2015.11
2575:10.1109/MM.2010.40
2263:on 29 August 2017.
2200:Fujitsu Ltd., 2014
1875:The New York Times
1586:. Sun Microsystems
1256:Diefendorff, Keith
1211:20 nm process
1174:. You can help by
1143:architecture. The
1113:Hybrid Memory Cube
1109:memory controllers
1086:Core Memory Groups
783:memory controllers
759:
752:
644:fused multiply-add
190:organization with
3488:
3487:
3416:Fujitsu Frontiers
3411:Kawasaki Frontale
3330:
3329:
3070:
3069:
2982:
2981:
2943:Nifty Corporation
2661:978-1-4673-4515-6
2618:978-1-4244-5454-9
2537:978-1-4244-2397-2
2230:The Next Platform
2075:978-1-4673-8879-5
1822:on 8 October 2010
1554:The Unix Guardian
1517:The Unix Guardian
1472:The Unix Guardian
1307:The Unix Guardian
1244:on 12 March 2006.
1238:The Unix Guardian
1192:
1191:
1066:high-Îş metal gate
978:branch prediction
851:LINPACK benchmark
837:. Located at the
824:vector processors
803:Kei Soku Keisenki
616:
615:
442:
441:
126:
125:
16:(Redirected from
3523:
3476:
3475:
3464:
3463:
3444:Now wholly owned
3421:Fujitsu Red Wave
3386:Atlas Consortium
3302:SPARC Enterprise
3261:
3083:
3037:
3029:
3021:
3002:
2990:
2919:
2888:
2868:
2861:
2854:
2845:
2819:Fujitsu SPARC64
2794:
2749:
2711:
2673:
2630:
2594:
2549:
2514:
2479:
2452:
2282:
2281:
2279:
2271:
2265:
2264:
2262:
2255:
2247:
2241:
2240:
2238:
2236:
2221:
2215:
2207:
2201:
2186:
2180:
2172:
2166:
2165:
2155:
2144:
2143:
2135:
2129:
2128:
2124:
2118:
2117:
2109:
2103:
2102:
2094:
2088:
2087:
2053:
2044:
2031:
2025:
2020:
2014:
2013:
2003:
1994:
1993:
1992:
1990:
1981:, archived from
1971:
1965:
1964:
1962:
1960:
1941:
1935:
1934:
1932:
1930:
1915:
1909:
1908:
1906:
1904:
1893:
1887:
1886:
1884:
1882:
1867:
1858:
1857:
1855:
1853:
1838:
1832:
1831:
1829:
1827:
1821:
1814:
1803:
1797:
1796:
1790:
1782:
1780:
1778:
1767:
1761:
1760:
1758:
1756:
1742:
1736:
1735:
1728:
1722:
1721:
1714:
1708:
1707:
1693:
1680:
1679:
1665:
1659:
1658:
1644:
1638:
1637:
1623:
1617:
1616:
1602:
1596:
1595:
1593:
1591:
1585:
1577:
1571:
1568:
1562:
1561:
1556:. Archived from
1545:
1534:
1531:
1525:
1524:
1519:. Archived from
1508:
1502:
1495:
1489:
1486:
1480:
1479:
1474:. Archived from
1463:
1457:
1451:
1445:
1439:
1433:
1431:
1397:
1386:
1383:
1377:
1371:
1362:
1356:
1350:
1347:
1338:
1337:
1329:
1320:
1311:
1310:
1298:
1292:
1291:
1276:
1270:
1269:
1252:
1246:
1245:
1240:. Archived from
1229:
1187:
1184:
1166:
1159:
877:register windows
700:SPARC Enterprise
656:SPARC Enterprise
474:
360:
229:microprocessor.
192:superspeculation
42:
35:
21:
3531:
3530:
3526:
3525:
3524:
3522:
3521:
3520:
3491:
3490:
3489:
3484:
3430:
3374:
3358:
3326:
3257:
3216:
3077:
3066:
3040:
3035:
3027:
3019:
2997:
2991:
2978:
2974:Ross Technology
2947:
2938:Glovia Services
2915:
2883:
2877:
2872:
2825:Wayback Machine
2801:
2759:
2714:
2676:
2662:
2640:
2619:
2597:
2559:
2538:
2517:
2503:
2482:
2476:
2455:
2441:
2415:
2407:
2405:Further reading
2296:(August 2004).
2294:Fujitsu Limited
2290:
2285:
2277:
2273:
2272:
2268:
2260:
2253:
2249:
2248:
2244:
2234:
2232:
2223:
2222:
2218:
2208:
2204:
2198:Wayback Machine
2187:
2183:
2173:
2169:
2157:
2156:
2147:
2137:
2136:
2132:
2126:
2125:
2121:
2111:
2110:
2106:
2096:
2095:
2091:
2076:
2055:
2054:
2047:
2032:
2028:
2021:
2017:
2005:
2004:
1997:
1988:
1986:
1985:on 23 June 2011
1973:
1972:
1968:
1958:
1956:
1955:on 23 June 2011
1943:
1942:
1938:
1928:
1926:
1925:on 23 June 2011
1917:
1916:
1912:
1902:
1900:
1895:
1894:
1890:
1880:
1878:
1869:
1868:
1861:
1851:
1849:
1840:
1839:
1835:
1825:
1823:
1819:
1812:
1805:
1804:
1800:
1783:
1776:
1774:
1769:
1768:
1764:
1754:
1752:
1744:
1743:
1739:
1730:
1729:
1725:
1716:
1715:
1711:
1695:
1694:
1683:
1667:
1666:
1662:
1646:
1645:
1641:
1625:
1624:
1620:
1604:
1603:
1599:
1589:
1587:
1583:
1579:
1578:
1574:
1569:
1565:
1547:
1546:
1537:
1532:
1528:
1510:
1509:
1505:
1496:
1492:
1487:
1483:
1465:
1464:
1460:
1452:
1448:
1440:
1436:
1420:
1399:
1398:
1389:
1384:
1380:
1372:
1365:
1357:
1353:
1348:
1341:
1327:
1322:
1321:
1314:
1300:
1299:
1295:
1278:
1277:
1273:
1254:
1253:
1249:
1231:
1230:
1223:
1219:
1188:
1182:
1179:
1172:needs expansion
1157:
1129:
1081:assistant cores
1043:
1010:
1002:PCI Express 3.0
969:
948:
905:set-associative
886:
863:
799:
787:memory channels
748:heat exchangers
733:
712:
664:
589:
573:
469:
438:
355:
346:
322:
313:
298:
253:
244:
235:
215:
176:
122:
28:
23:
22:
15:
12:
11:
5:
3529:
3527:
3519:
3518:
3513:
3508:
3503:
3493:
3492:
3486:
3485:
3483:
3482:
3470:
3457:
3456:
3451:
3446:
3441:
3435:
3432:
3431:
3429:
3428:
3423:
3418:
3413:
3408:
3406:Furukawa Group
3403:
3401:Fujitsu Ladies
3398:
3393:
3388:
3382:
3380:
3376:
3375:
3373:
3372:
3366:
3364:
3360:
3359:
3357:
3356:
3354:Naoki Yokoyama
3351:
3346:
3344:David Courtley
3340:
3338:
3332:
3331:
3328:
3327:
3325:
3324:
3319:
3314:
3309:
3304:
3299:
3294:
3289:
3284:
3279:
3274:
3269:
3264:
3263:
3262:
3259:FM Towns games
3253:FM Towns Marty
3250:
3245:
3240:
3235:
3230:
3224:
3222:
3218:
3217:
3215:
3214:
3213:
3212:
3207:
3198:
3197:
3196:
3195:
3192:
3187:
3182:
3173:
3172:
3171:
3170:
3165:
3160:
3155:
3150:
3141:
3140:
3135:
3130:
3125:
3120:
3115:
3110:
3105:
3100:
3095:
3089:
3087:
3080:
3072:
3071:
3068:
3067:
3065:
3064:
3059:
3054:
3048:
3046:
3042:
3041:
3039:
3038:
3030:
3022:
3014:
3008:
3006:
2999:
2993:
2992:
2985:
2983:
2980:
2979:
2977:
2976:
2971:
2966:
2961:
2955:
2953:
2949:
2948:
2946:
2945:
2940:
2935:
2930:
2927:
2922:
2921:
2920:
2908:
2903:
2900:
2894:
2892:
2885:
2879:
2878:
2873:
2871:
2870:
2863:
2856:
2848:
2842:
2841:
2836:
2831:
2817:
2812:
2807:
2800:
2799:External links
2797:
2796:
2795:
2756:
2755:
2751:
2750:
2712:
2674:
2660:
2637:
2636:
2632:
2631:
2617:
2595:
2556:
2555:
2554:SPARC64 VIIIfx
2551:
2550:
2536:
2515:
2501:
2480:
2474:
2453:
2439:
2412:
2411:
2406:
2403:
2402:
2401:
2394:
2381:
2368:
2355:
2346:
2337:
2328:
2319:
2310:
2301:
2289:
2286:
2284:
2283:
2266:
2242:
2216:
2202:
2181:
2167:
2145:
2140:EnterpriseTech
2130:
2119:
2104:
2089:
2074:
2045:
2026:
2015:
1995:
1966:
1936:
1910:
1888:
1877:. 20 June 2011
1859:
1848:. 20 June 2011
1833:
1798:
1762:
1737:
1723:
1709:
1681:
1660:
1639:
1618:
1597:
1572:
1563:
1535:
1526:
1503:
1490:
1481:
1458:
1456:, p. 705.
1446:
1434:
1418:
1387:
1378:
1363:
1351:
1339:
1312:
1293:
1271:
1247:
1220:
1218:
1215:
1190:
1189:
1169:
1167:
1156:
1153:
1128:
1125:
1096:organization.
1042:
1039:
1009:
1006:
968:
965:
947:
944:
943:
942:
938:
937:
936:
935:
932:
926:
925:
918:
917:
916:
915:
908:
894:
893:
890:
885:
882:
862:
859:
853:at 8.162
798:
795:
763:SPARC64 VIIIfx
732:
731:SPARC64 VIIIfx
729:
711:
708:
663:
660:
614:
613:
608:
604:
603:
600:
596:
595:
591:
590:
588:
587:
583:
581:
575:
574:
572:
571:
564:
562:
556:
555:
551:
550:
545:
539:
538:
534:
533:
530:
526:
525:
518:
511:
510:
506:
505:
502:
492:
491:
487:
486:
483:
479:
478:
468:
465:
440:
439:
437:
436:
432:
430:
424:
423:
419:
418:
413:
407:
406:
402:
401:
398:
388:
387:
383:
382:
377:
373:
372:
369:
365:
364:
354:
351:
345:
342:
321:
318:
312:
309:
297:
294:
252:
249:
243:
240:
234:
231:
214:
211:
175:
172:
141:microprocessor
124:
123:
121:
120:
116:
114:
108:
107:
103:
102:
97:
91:
90:
86:
85:
82:
72:
71:
67:
66:
61:
57:
56:
53:
49:
48:
44:
43:
26:
24:
14:
13:
10:
9:
6:
4:
3:
2:
3528:
3517:
3514:
3512:
3509:
3507:
3504:
3502:
3499:
3498:
3496:
3481:
3480:
3471:
3469:
3468:
3459:
3458:
3455:
3452:
3450:
3447:
3445:
3442:
3440:
3437:
3436:
3433:
3427:
3424:
3422:
3419:
3417:
3414:
3412:
3409:
3407:
3404:
3402:
3399:
3397:
3394:
3392:
3389:
3387:
3384:
3383:
3381:
3377:
3371:
3368:
3367:
3365:
3361:
3355:
3352:
3350:
3347:
3345:
3342:
3341:
3339:
3337:
3333:
3323:
3320:
3318:
3315:
3313:
3310:
3308:
3305:
3303:
3300:
3298:
3295:
3293:
3290:
3288:
3285:
3283:
3280:
3278:
3275:
3273:
3270:
3268:
3265:
3260:
3256:
3255:
3254:
3251:
3249:
3246:
3244:
3241:
3239:
3236:
3234:
3231:
3229:
3226:
3225:
3223:
3219:
3211:
3208:
3206:
3203:
3202:
3200:
3199:
3193:
3191:
3188:
3186:
3183:
3181:
3178:
3177:
3175:
3174:
3169:
3166:
3164:
3161:
3159:
3156:
3154:
3151:
3149:
3146:
3145:
3143:
3142:
3139:
3136:
3134:
3131:
3129:
3126:
3124:
3121:
3119:
3116:
3114:
3111:
3109:
3106:
3104:
3101:
3099:
3096:
3094:
3091:
3090:
3088:
3084:
3081:
3079:
3078:and standards
3073:
3063:
3060:
3058:
3055:
3053:
3050:
3049:
3047:
3043:
3034:
3031:
3026:
3023:
3018:
3015:
3013:
3010:
3009:
3007:
3003:
3000:
2998:shareholdings
2994:
2989:
2975:
2972:
2970:
2967:
2965:
2962:
2960:
2957:
2956:
2954:
2950:
2944:
2941:
2939:
2936:
2934:
2931:
2928:
2926:
2923:
2918:
2914:
2913:
2912:
2909:
2907:
2904:
2901:
2899:
2896:
2895:
2893:
2889:
2886:
2882:Divisions and
2880:
2876:
2869:
2864:
2862:
2857:
2855:
2850:
2849:
2846:
2840:
2837:
2835:
2832:
2830:
2826:
2822:
2818:
2816:
2813:
2811:
2808:
2806:
2803:
2802:
2798:
2792:
2788:
2784:
2780:
2776:
2772:
2768:
2764:
2758:
2757:
2753:
2752:
2747:
2743:
2739:
2735:
2731:
2727:
2723:
2719:
2713:
2709:
2705:
2701:
2697:
2693:
2689:
2685:
2681:
2675:
2671:
2667:
2663:
2657:
2653:
2649:
2645:
2639:
2638:
2634:
2633:
2628:
2624:
2620:
2614:
2610:
2606:
2602:
2596:
2592:
2588:
2584:
2580:
2576:
2572:
2568:
2564:
2558:
2557:
2553:
2552:
2547:
2543:
2539:
2533:
2529:
2525:
2521:
2516:
2512:
2508:
2504:
2502:0-7695-2025-1
2498:
2494:
2490:
2486:
2481:
2477:
2475:1-58113-688-9
2471:
2467:
2463:
2459:
2454:
2450:
2446:
2442:
2440:0-7803-7707-9
2436:
2432:
2428:
2424:
2420:
2414:
2413:
2409:
2408:
2404:
2399:
2395:
2392:
2391:
2386:
2382:
2379:
2378:
2373:
2369:
2366:
2365:
2360:
2356:
2353:
2352:
2347:
2344:
2343:
2338:
2335:
2334:
2329:
2326:
2325:
2320:
2317:
2316:
2311:
2308:
2307:
2302:
2299:
2295:
2292:
2291:
2287:
2276:
2270:
2267:
2259:
2252:
2246:
2243:
2231:
2227:
2220:
2217:
2213:
2212:
2206:
2203:
2199:
2195:
2192:
2191:
2185:
2182:
2178:
2177:
2171:
2168:
2163:
2162:
2154:
2152:
2150:
2146:
2141:
2134:
2131:
2123:
2120:
2115:
2108:
2105:
2100:
2093:
2090:
2085:
2081:
2077:
2071:
2067:
2063:
2059:
2052:
2050:
2046:
2042:
2041:
2036:
2030:
2027:
2024:
2019:
2016:
2011:
2010:
2002:
2000:
1996:
1984:
1980:
1976:
1970:
1967:
1954:
1950:
1946:
1940:
1937:
1924:
1920:
1914:
1911:
1898:
1892:
1889:
1876:
1872:
1866:
1864:
1860:
1847:
1846:The Telegraph
1843:
1837:
1834:
1818:
1811:
1810:
1802:
1799:
1794:
1788:
1772:
1766:
1763:
1751:
1747:
1741:
1738:
1733:
1727:
1724:
1719:
1713:
1710:
1705:
1704:
1699:
1692:
1690:
1688:
1686:
1682:
1677:
1676:
1671:
1664:
1661:
1656:
1655:
1650:
1643:
1640:
1635:
1634:
1629:
1622:
1619:
1614:
1613:
1608:
1601:
1598:
1582:
1576:
1573:
1567:
1564:
1559:
1555:
1551:
1544:
1542:
1540:
1536:
1530:
1527:
1522:
1518:
1514:
1507:
1504:
1500:
1494:
1491:
1485:
1482:
1477:
1473:
1469:
1462:
1459:
1455:
1450:
1447:
1443:
1438:
1435:
1429:
1425:
1421:
1415:
1411:
1407:
1403:
1396:
1394:
1392:
1388:
1382:
1379:
1375:
1370:
1368:
1364:
1360:
1355:
1352:
1346:
1344:
1340:
1335:
1334:
1326:
1319:
1317:
1313:
1308:
1304:
1297:
1294:
1289:
1285:
1281:
1275:
1272:
1267:
1263:
1262:
1257:
1251:
1248:
1243:
1239:
1235:
1228:
1226:
1222:
1216:
1214:
1212:
1208:
1204:
1200:
1196:
1186:
1177:
1173:
1170:This section
1168:
1165:
1161:
1160:
1154:
1152:
1150:
1146:
1142:
1138:
1134:
1126:
1124:
1120:
1118:
1114:
1110:
1105:
1102:
1097:
1095:
1091:
1087:
1082:
1078:
1077:compute cores
1073:
1071:
1067:
1064:
1060:
1056:
1055:PRIMEHPC FX10
1052:
1048:
1040:
1038:
1036:
1032:
1028:
1024:
1020:
1015:
1007:
1005:
1003:
999:
995:
991:
987:
983:
979:
974:
966:
964:
961:
960:PRIMEHPC FX10
957:
953:
945:
940:
939:
933:
930:
929:
928:
927:
923:
920:
919:
913:
909:
906:
902:
898:
897:
896:
895:
891:
888:
887:
883:
881:
878:
872:
869:
868:associativity
860:
858:
856:
852:
848:
844:
840:
836:
831:
829:
825:
821:
817:
813:
808:
804:
796:
794:
792:
788:
784:
780:
776:
772:
768:
764:
756:
749:
745:
742:
737:
730:
728:
725:
721:
717:
709:
707:
705:
701:
696:
694:
689:
685:
681:
677:
673:
669:
661:
659:
657:
651:
647:
645:
641:
637:
633:
629:
625:
621:
612:
609:
605:
601:
597:
592:
585:
584:
582:
580:
576:
569:
566:
565:
563:
561:
557:
552:
549:
546:
544:
540:
535:
531:
527:
523:
519:
517:
512:
507:
503:
501:
498:
493:
488:
484:
480:
475:
466:
464:
462:
458:
453:
449:
447:
434:
433:
431:
429:
425:
420:
417:
414:
412:
408:
403:
399:
397:
394:
389:
384:
381:
378:
374:
370:
366:
361:
352:
350:
343:
341:
339:
335:
331:
327:
319:
317:
310:
308:
305:
301:
295:
293:
289:
285:
283:
279:
275:
271:
267:
261:
259:
250:
248:
242:Register read
241:
239:
232:
230:
228:
224:
220:
212:
210:
208:
203:
199:
197:
193:
189:
185:
181:
173:
171:
169:
168:PRIMEHPC FX10
165:
160:
157:
153:
148:
146:
142:
139:
135:
131:
118:
117:
115:
113:
109:
104:
101:
98:
96:
92:
87:
83:
81:
78:
73:
68:
65:
62:
58:
54:
50:
45:
41:
36:
30:
19:
3477:
3465:
3453:
3448:
3443:
3438:
3426:PFU BlueCats
3349:Toshio Ikeda
3168:SPARC64 XIfx
3144:Processors:
2884:subsidiaries
2769:(2): 32–40.
2766:
2762:
2754:SPARC64 XIfx
2724:(6): 16–24.
2721:
2717:
2686:(1): 32–40.
2683:
2679:
2643:
2600:
2569:(2): 30–40.
2566:
2562:
2519:
2484:
2457:
2422:
2418:
2397:
2390:The Register
2388:
2377:The Register
2375:
2364:The Register
2362:
2349:
2340:
2331:
2322:
2313:
2304:
2297:
2269:
2258:the original
2245:
2233:. Retrieved
2229:
2219:
2210:
2205:
2189:
2184:
2175:
2170:
2159:
2139:
2133:
2122:
2113:
2107:
2098:
2092:
2057:
2040:The Register
2038:
2029:
2018:
2007:
1987:, retrieved
1983:the original
1978:
1969:
1957:. Retrieved
1953:the original
1948:
1939:
1927:. Retrieved
1923:the original
1913:
1901:. Retrieved
1891:
1879:. Retrieved
1874:
1850:. Retrieved
1845:
1836:
1824:. Retrieved
1817:the original
1808:
1801:
1775:. Retrieved
1765:
1753:. Retrieved
1750:The Register
1749:
1740:
1726:
1712:
1703:The Register
1701:
1675:The Register
1673:
1663:
1654:The Register
1652:
1642:
1633:The Register
1631:
1621:
1612:The Register
1610:
1600:
1588:. Retrieved
1575:
1566:
1558:the original
1553:
1529:
1521:the original
1516:
1506:
1498:
1493:
1484:
1476:the original
1471:
1461:
1449:
1442:Krewell 2002
1437:
1401:
1381:
1359:Krewell 2002
1354:
1331:
1306:
1296:
1279:
1274:
1265:
1259:
1250:
1242:the original
1237:
1194:
1193:
1183:January 2018
1180:
1176:adding to it
1171:
1149:ARM Holdings
1130:
1121:
1116:
1106:
1098:
1089:
1085:
1080:
1076:
1074:
1069:
1047:SPARC64 XIfx
1046:
1044:
1041:SPARC64 XIfx
1019:speed-binned
1013:
1011:
986:cryptography
972:
970:
952:SPARC64 IXfx
951:
949:
946:SPARC64 IXfx
899:L1: 32
873:
864:
832:
802:
800:
766:
762:
760:
723:
719:
716:SPARC64 VII+
715:
713:
710:SPARC64 VII+
703:
697:
683:
671:
667:
665:
652:
648:
639:
619:
617:
454:
450:
445:
443:
347:
330:0.13 ÎĽm
323:
314:
306:
302:
299:
290:
286:
274:multiply–add
266:multiply–add
262:
254:
245:
236:
216:
204:
200:
177:
161:
149:
143:designed by
133:
129:
127:
29:
3396:Fujitsu Cup
3292:Pocket LOOX
1444:, p. 3
1361:, p. 2
1195:SPARC64 XII
1155:SPARC64 XII
910:L2: 6
861:Description
668:SPARC64 VII
662:SPARC64 VII
611:SPARC64 VII
599:Predecessor
570:transistors
560:Transistors
490:Performance
386:Performance
376:Designed by
219:superscalar
213:Description
196:trace cache
188:superscalar
70:Performance
60:Designed by
18:SPARC64 VII
3495:Categories
3312:TurboSPARC
3194:Primequest
3185:K computer
3163:SPARC64 X+
3123:Macroscope
2763:IEEE Micro
2718:IEEE Micro
2563:IEEE Micro
1979:top500.org
1949:top500.org
1755:3 December
1419:1581136889
1217:References
1063:20 nm
1014:SPARC64 X+
1008:SPARC64 X+
994:DDR3 SDRAM
835:K computer
791:DDR3 SDRAM
775:45 nm
741:K computer
693:65 nm
632:SPARC64 V+
624:SPARC64 V+
620:SPARC64 VI
602:SPARC64 V+
500:clock rate
472:SPARC64 VI
467:SPARC64 VI
457:90 nm
446:SPARC64 V+
396:clock rate
358:SPARC64 V+
353:SPARC64 V+
344:Electrical
326:fabricated
311:System bus
270:SPARC64 VI
184:SPARC64 GP
164:K computer
80:clock rate
3287:Micro 16s
3062:Socionext
3033:Denso Ten
2791:206473367
2783:0272-1732
2738:0272-1732
2700:0018-9200
2670:0193-6530
2635:SPARC64 X
2627:2158-5601
2591:206472881
2583:0272-1732
2546:1530-0889
2511:1063-6404
2449:0193-6530
2410:SPARC64 V
1899:. Fujitsu
1454:Ando 2003
1051:Hot Chips
973:SPARC64 X
967:SPARC64 X
720:Jupiter-E
682:, termed
607:Successor
520:128
251:Execution
227:mainframe
130:SPARC64 V
33:SPARC64 V
3467:Category
3454:Spun off
3248:FM Towns
3210:Lifebook
3190:Primergy
3057:Spansion
2708:32362191
2194:Archived
2084:34868980
1787:cite web
1590:21 April
1137:exascale
998:glueless
990:database
903:two-way
704:Jupiter+
548:SPARC V9
529:L2 cache
524:per core
482:Launched
416:SPARC V9
368:Launched
320:Physical
233:Pipeline
138:SPARC V9
100:SPARC V9
52:Launched
3479:Commons
3307:SPARC64
3221:Defunct
3205:Celsius
3086:Current
3017:TranSys
3005:Current
2891:Current
2875:Fujitsu
2823:at the
2746:8056145
2288:Sources
2235:13 July
1989:20 June
1959:20 June
1929:20 June
1903:20 June
1881:20 June
1852:20 June
1826:30 June
1432:p. 702.
1428:7005187
1061:in its
812:Hitachi
797:History
672:Jupiter
594:History
380:Fujitsu
336:(CMOS)
174:History
145:Fujitsu
136:) is a
64:Fujitsu
3363:Places
3336:People
3322:VP2000
3243:FLEPia
3233:DC/OSx
3180:Fugaku
3138:VM2000
3128:OpenFT
3103:BS2000
3098:BCeSIS
2789:
2781:
2744:
2736:
2706:
2698:
2668:
2658:
2625:
2615:
2589:
2581:
2544:
2534:
2509:
2499:
2472:
2447:
2437:
2082:
2072:
1777:14 May
1426:
1416:
1199:POWER9
1127:Future
1094:ccNUMA
1031:POWER8
924:(TLB):
892:Cache:
855:PFLOPS
847:TOP500
820:scalar
814:, and
779:GFLOPS
152:Oracle
3379:Other
3297:SINIX
3277:FM-11
3238:Eagle
3148:A64FX
3133:SESAM
3036:(14%)
3028:(20%)
3020:(20%)
2959:FANUC
2787:S2CID
2742:S2CID
2704:S2CID
2587:S2CID
2278:(PDF)
2261:(PDF)
2254:(PDF)
2080:S2CID
1820:(PDF)
1813:(PDF)
1584:(PDF)
1424:S2CID
1328:(PDF)
1145:A64FX
1141:ARMv8
1027:Intel
839:RIKEN
767:Venus
744:blade
579:Cores
568:90 nm
516:cache
509:Cache
495:Max.
428:Cores
391:Max.
328:in a
296:Cache
112:Cores
75:Max.
3449:Sold
3282:iPAD
3272:FM-8
3267:FM-7
3158:FR-V
3118:HOAP
3108:Enon
3093:ALiS
2779:ISSN
2734:ISSN
2696:ISSN
2666:ISSN
2656:ISBN
2623:ISSN
2613:ISBN
2579:ISSN
2542:ISSN
2532:ISBN
2507:ISSN
2497:ISBN
2470:ISBN
2445:ISSN
2435:ISBN
2237:2016
2070:ISBN
1991:2011
1961:2011
1931:2011
1905:2011
1883:2011
1854:2011
1828:2019
1793:link
1779:2009
1757:2010
1592:2008
1414:ISBN
1336:: 1.
1268:(5).
1207:TSMC
1101:SIMD
1090:CMGs
1023:Xeon
1012:The
976:for
971:The
950:The
843:Kobe
822:and
761:The
714:The
666:The
618:The
485:2007
444:The
371:2004
207:SPEC
134:Zeus
128:The
55:2001
3025:PFU
2771:doi
2726:doi
2688:doi
2648:doi
2605:doi
2571:doi
2524:doi
2489:doi
2462:doi
2427:doi
2062:doi
1406:doi
1284:doi
1209:'s
1203:TLB
1178:.
1035:IBM
1033:by
956:LSI
816:NEC
688:RAS
514:L1
497:CPU
393:CPU
77:CPU
3497::
3317:VP
3153:FR
2785:.
2777:.
2767:35
2765:.
2740:.
2732:.
2722:33
2720:.
2702:.
2694:.
2684:49
2682:.
2664:.
2654:.
2621:.
2611:.
2585:.
2577:.
2567:30
2565:.
2540:.
2530:.
2505:.
2495:.
2468:.
2443:.
2433:.
2387:.
2374:.
2361:.
2228:.
2148:^
2078:.
2068:.
2048:^
2037:.
1998:^
1977:,
1947:.
1873:.
1862:^
1844:.
1789:}}
1785:{{
1748:.
1700:.
1684:^
1672:.
1651:.
1630:.
1609:.
1552:.
1538:^
1515:.
1470:.
1422:.
1412:.
1390:^
1366:^
1342:^
1330:.
1315:^
1305:.
1266:13
1264:.
1236:.
1224:^
1151:.
1037:.
988:,
980:,
912:MB
901:KB
739:A
724:M3
522:KB
463:.
154:)
2867:e
2860:t
2853:v
2793:.
2773::
2748:.
2728::
2710:.
2690::
2672:.
2650::
2629:.
2607::
2593:.
2573::
2548:.
2526::
2513:.
2491::
2478:.
2464::
2451:.
2429::
2393:.
2380:.
2367:.
2354:.
2345:.
2336:.
2327:.
2318:.
2309:.
2300:.
2280:.
2239:.
2164:.
2142:.
2116:.
2101:.
2086:.
2064::
2043:.
2012:.
1963:.
1933:.
1907:.
1885:.
1856:.
1830:.
1795:)
1781:.
1759:.
1706:.
1678:.
1657:.
1636:.
1615:.
1594:.
1430:.
1408::
1290:.
1286::
1185:)
1181:(
1088:(
765:(
750:)
718:(
586:2
435:1
132:(
119:1
20:)
Text is available under the Creative Commons Attribution-ShareAlike License. Additional terms may apply.