379:, from the beginning of the linear (flat) address space. That is, at 16 byte intervals. Since all segments are 64 KB long, this explains how overlap can occur between segments and why any location in the linear memory address space can be accessed with many segment:offset pairs. The actual location of the beginning of a segment in the linear address space can be calculated with segmentĂ16. A segment value of 0Ch (12) would give a linear address at C0h (192) in the linear address space. The address offset can then be added to this number. 0Ch:0Fh (12:15) would be C0h+0Fh=CFh (192+15=207), CFh (207) being the linear address. Such address translations are carried out by the segmentation unit of the CPU. The last segment, FFFFh (65535), begins at linear address FFFF0h (1048560), 16 bytes before the end of the 20 bit address space, and thus, can access, with an offset of up to 65,536 bytes, up to 65,520 (65536â16) bytes past the end of the 20 bit 8088 address space. On the 8088, these address accesses were wrapped around to the beginning of the address space such that 65535:16 would access address 0 and 65533:1000 would access address 952 of the linear address space. The use of this feature by programmers led to the
627:
segmentation unit is otherwise unchanged. The paging unit may be enabled or disabled; if disabled, operation is the same as on the 80286. If the paging unit is enabled, addresses in a segment are now virtual addresses, rather than physical addresses as they were on the 80286. That is, the segment starting address, the offset, and the final 32-bit address the segmentation unit derived by adding the two are all virtual (or logical) addresses when the paging unit is enabled. When the segmentation unit generates and validates these 32-bit virtual addresses, the enabled paging unit finally translates these virtual addresses into physical addresses. The physical addresses are 32-bit on the
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than 64k in size, however as the
Segment Limit field is only 24-bit long, the maximum segment size that can be created is 16MB (although paging can be used to allocate more memory, no individual segment may exceed 16MB). This method was commonly used on Windows 3.x applications to produce a flat memory space, although as the OS itself was still 16-bit, API calls could not be made with 32-bit instructions. Thus, it was still necessary to place all code that performs API calls in 64k segments.
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603:. Otherwise, address translation continues. The processor then takes the 32-bit or 16-bit offset and compares it against the segment limit specified in the segment descriptor. If it is larger, a GP fault is generated. Otherwise, the processor adds the 24-bit segment base, specified in descriptor, to the offset, creating a linear physical address.
1010:
with the base address, segment limit, and access control information from the segment descriptor pointed to by the segment selector. The information cached in the segment register (visible and hidden) allows the processor to translate addresses without taking extra bus cycles to read the base address and limit from the segment descriptor.
547:
286 protected mode was seldom used as it would have excluded the large body of users with 8086/88 machines. Moreover, it still necessitated dividing memory into 64k segments like was done in real mode. This limitation can be worked around on 32-bit CPUs which permit the use of memory pointers greater
250:
The 16-bit segment selector in the segment register is interpreted as the most significant 16 bits of a linear 20-bit address, called a segment address, of which the remaining four least significant bits are all zeros. The segment address is always added to a 16-bit offset in the instruction to yield
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specified by the segment selector held in the DS register. These may also come from the extra segment specified by the segment selector held in the ES register, if a segment-override prefix precedes the instruction that makes the memory reference. Most, but not all, instructions that use
595:
where CPL is the current privilege level (found in the lower 2 bits of the CS register), RPL is the requested privilege level from the segment selector, and DPL is the descriptor privilege level of the segment (found in the descriptor). All privilege levels are integers in the range 0â3, where
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Every segment register has a âvisibleâ part and a âhiddenâ part. (The hidden part is sometimes referred to as a âdescriptor cacheâ or a âshadow register.â) When a segment selector is loaded into the visible part of a segment register, the processor also loads the hidden part of the segment register
386:
In 16-bit real mode, enabling applications to make use of multiple memory segments (in order to access more memory than available in any one 64K-segment) is quite complex, but was viewed as a necessary evil for all but the smallest tools (which could do with less memory). The root of the problem is
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be 64 KB long. Because there is no protection or privilege limitation in real mode, even if a segment could be defined to be smaller than 64 KB, it would still be entirely up to the programs to coordinate and keep within the bounds of their segments, as any program can always access any
658:
architecture does not use segmentation in long mode (64-bit mode). Four of the segment registers, CS, SS, DS, and ES, are forced to base address 0, and the limit to 2. The segment registers FS and GS can still have a nonzero base address. This allows operating systems to use these segments for
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unit has been added as a second layer of address translation between the segmentation unit and the physical bus. Also, importantly, address offsets are 32-bit (instead of 16-bit), and the segment base in each segment descriptor is also 32-bit (instead of 24-bit). The general operation of the
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The choice of segment is normally defaulted by the processor according to the function being executed. Instructions are always fetched from the code segment. Any stack push or pop or any data reference referring to the stack uses the stack segment. All other references to data use the data
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containing 24-bit base addresses to which the offset is added. To support old software, the processor starts up in "real mode", a mode in which it uses the segmented addressing model of the 8086. There is a small difference though: the resulting physical address is no longer truncated to
528:). With the addition of the HMA, the total address space is approximately 1.06 MB. Though the 80286 does not truncate real-mode addresses to 20 bits, a system containing an 80286 can do so with hardware external to the processor, by gating off the 21st address line, the
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memory (since it can arbitrarily set segment selectors to change segment addresses with absolutely no supervision). Therefore, real mode can just as well be imagined as having a variable length for each segment, in the range 1 to 65,536 bytes, that is just not enforced by the CPU.
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A 386 CPU can be put back into real mode by clearing a bit in the CR0 control register, however this is a privileged operation in order to enforce security and robustness. By way of comparison, a 286 could only be returned to real mode by forcing a processor reset, e.g. by a
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Because of the way the segment address and offset are added, a single linear address can be mapped to up to 2 = 4096 distinct segment:offset pairs. For example, the linear address 08124h can have the segmented addresses 06EFh:1234h, 0812h:0004h, 0000h:8124h, etc.
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must be used with extreme care and has limited usefulness, because it immediately changes the effective address that will be computed from the instruction pointer to fetch the next instruction. Generally, a far jump is much more useful. The existence of
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that no appropriate address-arithmetic instructions suitable for flat addressing of the entire memory range are available. Flat addressing is possible by applying multiple instructions, which however leads to slower programs.
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selector). This is because the current privilege level (CPL) of the processor is stored in the lower 2 bits of the CS register. The only ways to raise the processor privilege level (and reload CS) are through the
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A logical address consists of a 16-bit segment selector (supplying 13+1 address bits) and a 16-bit offset. The segment selector must be located in one of the segment registers. That selector consists of a 2-bit
Requested
340:
This could be confusing to programmers accustomed to unique addressing schemes, but it can also be used to advantage, for example when addressing multiple nested data structures. While real mode segments are always
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standard could feign a reset to the CPU via the standardised keyboard controller, but this was significantly sluggish. Windows 3.x worked around both of these problems by intentionally triggering a
207:, introduced in 1985, adds two additional segment registers, FS and GS, with no specific uses defined by the hardware. The way in which the segment registers are used differs between the two modes.
372:. (Both were packaged in 40-pin DIP packages; even with only 20 address lines, the address and data buses were multiplexed to fit all the address and data lines within the limited pin count.)
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segment. The extra segment is the default destination for string operations (for example MOVS or CMPS). FS and GS have no hardware-assigned uses. The instruction format allows an optional
263:) has a segment selector of 06EFh, representing a segment address of 06EF0h, to which the offset is added, yielding the linear address 06EF0h + 1234h = 08124h.
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extends the processor's address space to 2 bytes (16 megabytes), but not by adjusting the shift value. Instead, the 16-bit segment registers now contain an index into a table of
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instruction on the 8086 or 8088). Of course, in real mode, there are no privilege levels; all programs have absolute unchecked access to all of memory and all CPU instructions.
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Segmentation cannot be turned off on x86-32 processors (this is true for 64-bit mode as well, but beyond the scope of discussion), so many 32-bit operating systems simulate a
1007:"Intel 64 and IA-32 Architectures Software Developer's Manual", Volume 3, "System Programming Guide", published in 2011, Page "Vol. 3A 3-11", the book is written: "
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Segments can be defined to be either code, data, or system segments. Additional permission bits are present to make segments read only, read/write, execute, etc.
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Since the base is set to 0 in all cases and the limit 4 GiB, the segmentation unit does not affect the addresses the program issues before they arrive at the
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memory (click on image to enlarge). There is an overlap between segment 2 and segment 3; the bytes in the turquoise area can be used from both segment selectors.
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The 80386 also introduced two new general-purpose data segment registers, FS and GS, to the original set of four segment registers (CS, DS, ES, and SS).
353:(The leading zeros of the linear address, segmented addresses, and the segment and offset fields are shown here for clarity. They are usually omitted.)
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368:). This derived directly from the hardware design of the Intel 8086 (and, subsequently, the closely related 8088), which had exactly 20
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is probably an accident, as it follows a pattern of PUSH and POP instruction opcodes for the four segment registers on the 8086 and 8088.
969:(interrupt return) instructions. In real mode, code may also modify the CS register by making a far jump (or using an undocumented
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memory model DS=SS, so both data and stack reside in the same segment; CS points to a different code segment of up to 64 KB.
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Once 286 protected mode is invoked, it could not be exited except by performing a hardware reset. Machines following the rising
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532:. The IBM PC AT provided the hardware to do this (for full backward compatibility with software for the original
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694:, which contains information about exception handling, thread-local variables, and other per-thread state. Similarly, the
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in the interrupt-handling mechanisms of the CPU, which would cause the CPU to drop back into real mode, nearly instantly.
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unit. (This, of course, refers to 80386 and later processors, as the earlier x86 processors do not have a paging unit.)
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to derive the actual memory address. In real mode, the registers CS, DS, SS, and ES point to the currently used program
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CS=DS=SS, that is the program's code, data, and stack are all contained within a single 64 KB segment. In the
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long, the practical effect is only that no segment can be longer than 64 KB, rather than that every segment
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compatibility issues in later CPU generations, where the linear address space was expanded past 20 bits.
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by setting all segments' bases to 0 in order to make segmentation neutral to programs. For instance, the
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instructions. Similarly, the only ways to lower the privilege level (and reload CS) are through
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When attempting address translation of a given logical address, the processor reads the 64-bit
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byte which can be used to override the default segment for selected instructions if desired.
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and later, protected mode retains the segmentation mechanism of 80286 protected mode, but a
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in this mode. For instance, the segmented address 06EFh:1234h (here the suffix "h" means
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mechanism used by legacy modes, the base address of these segments is stored in a
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IA-32 Intel
Architecture Software Developer's Manual Volume 1: Basic Architecture
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The privilege check is done only when the segment register is loaded, because
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concept derives from the setup of the segment registers. For example, in the
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pointers (but not 8086 pointers) can now refer to addresses between 100000
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in 1978. It allows programs to address more than 64 KB (65,536
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442: in this section. Unsourced material may be challenged and removed.
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Home of the IA-32 Intel
Architecture Software Developer's Manual
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In protected mode, code may always modify all segment registers
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152:) of memory, the limit in earlier 80xx processors. In 1982, the
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specified by the segment selector held in the ES register.
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specified by the segment selector held in the SS register.
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specified by the segment selector held in the CS register.
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516:. This roughly 64-kilobyte region of memory was known as the
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Each segment begins at a multiple of 16 bytes, called a
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movl $ 42, %fs:(%eax) ; Equivalent to M<-42) in
572:(RPL), a 1-bit Table Indicator (TI), and a 13-bit index.
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In both real and protected modes, the system uses 16-bit
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However, segment registers are usually used implicitly.
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the lowest number corresponds to the highest privilege.
667:. The x86-64 architecture further provides the special
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Memory management as a function of an operating system
631:, but can be larger on newer processors which support
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If the inequality is false, the processor generates a
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All CPU instructions are implicitly fetched from the
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are cached in hidden parts of the segment registers.
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16 bits, shifted 4 bits left (or multiplied by 0x10)
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686:on x86-64 uses the GS segment to point to the
57:. Unsourced material may be challenged and removed.
794:memory accesses using the (E)SP or (E)BP registers
976:For more information about segmentation, see the
721:Logical addresses can be explicitly specified in
587:when TI=1. It then performs the privilege check:
364:to 2 bytes, or 1,048,576 bytes (1
777:DS by default will accept an ES override prefix.
698:uses the GS segment to store per-CPU data.
247:up to 65,536 bytes (using 16-bit offsets).
203:segment determined by the programmer (ES). The
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478:memory (click on image to enlarge), with the
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1470:International Symposium on Memory Management
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830:sets up only 4 general purpose segments:
814:), along with data segment, also use the
458:Learn how and when to remove this message
243:, the size of a segment can range from 1
117:Learn how and when to remove this message
832:
997:
931:Current Linux also uses GS to point to
671:instruction, which allows swapping the
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1001:
770:Most memory references come from the
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1104:The Segment:Offset Addressing Scheme
784:references, either implicitly (e.g.
440:adding citations to reliable sources
55:adding citations to reliable sources
1179:Inputâoutput memory management unit
563:Detailed segmentation unit workflow
690:, a small data structure for each
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980:manuals freely available on the
540:models), and so all subsequent "
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170:, and the new version was named
164:; the original mode was renamed
129:Memory segmentation on Intel x86
31:
1350:Concurrent mark sweep collector
544:-class" PC clones did as well.
427:needs additional citations for
42:needs additional citations for
18:Segment:offset addressing (x86)
1475:Region-based memory management
255:address, which is the same as
1:
792:instructions) or explicitly (
659:special purposes. Unlike the
601:general protection (GP) fault
520:(HMA), and later versions of
1523:Memory management algorithms
1335:Automatic Reference Counting
1173:Translation lookaside buffer
646:or using external hardware.
138:instruction set architecture
1513:Automatic memory management
1312:C dynamic memory allocation
1082:THE multiprogramming system
291:+
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1533:Memory management software
1380:Tracing garbage collection
1213:Virtual memory compression
1022:Intel Corporation (2004).
725:, e.g. (AT&T syntax):
633:Physical Address Extension
579:structure from either the
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1146:
66:"X86 memory segmentation"
1307:Static memory allocation
1299:Manual memory management
740:
688:Thread Environment Block
360:of real mode limits the
321:0000 1000 0001 0010 0100
1365:Garbage-first collector
1340:Boehm garbage collector
1246:x86 memory segmentation
701:GS/FS are also used in
665:model-specific register
661:global descriptor table
581:Global Descriptor Table
1370:Markâcompact algorithm
1167:Memory management unit
585:Local Descriptor Table
483:
480:local descriptor table
232:
1554:X86 memory management
723:x86 assembly language
473:
356:The effective 20-bit
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1317:new and delete (C++)
992:Notes and references
933:thread-local storage
707:thread-local storage
614:80386 protected mode
487:80286 protected mode
436:improve this article
51:improve this article
1223:Memory segmentation
875:Kernel data segment
858:Kernel code segment
804:String instructions
608:segment descriptors
591:max(CPL,âRPL) ⤠DPL
501:segment descriptors
294:0001 0010 0011 0100
273:0000 0110 1110 1111
144:since the original
142:memory segmentation
1465:Automatic variable
1449:Unreachable memory
1375:Reference counting
1345:Cheney's algorithm
1327:Garbage collection
650:Later developments
577:segment descriptor
484:
474:Three segments in
362:addressable memory
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227:Three segments in
195:(DS), the current
191:(CS), the current
156:added support for
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1493:Memory management
1241:Virtual 8086 mode
1140:Memory management
1077:x86 memory models
965:(far return) and
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909:User data segment
892:User code segment
824:flat memory model
713:stack protector.
684:Microsoft Windows
583:when TI=0 or the
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816:extra segment
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425:This section
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62:Find sources:
56:
52:
46:
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40:This article
38:
34:
29:
28:
19:
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1024:
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947:code segment
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828:Linux kernel
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773:data segment
771:
764:code segment
762:
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736:Intel syntax
733:
720:
711:canary-based
700:
696:Linux kernel
681:
668:
653:
644:triple fault
640:
637:
617:
605:
598:
594:
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557:triple fault
550:
546:
490:
479:
454:
445:
434:Please help
429:verification
426:
401:
397:
393:memory model
391:
389:
385:
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370:address pins
355:
352:
346:
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193:data segment
189:code segment
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131:
113:
104:
94:
87:
80:
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61:
49:Please help
44:verification
41:
1444:Memory leak
1087:Split octal
959:(interrupt)
872:__KERNEL_DS
855:__KERNEL_CS
839:Description
673:kernel mode
620:Intel 80386
534:IBM PC
448:August 2015
261:hexadecimal
205:Intel 80386
154:Intel 80286
1208:Page table
1043:"DevBlogs"
988:websites.
915:4 GiB
898:4 GiB
881:4 GiB
864:4 GiB
796:) use the
780:Processor
512:and 10FFEF
398:tiny model
146:Intel 8086
132:The Intel
77:newspapers
1355:Finalizer
1236:Real mode
906:__USER_DS
889:__USER_CS
717:Practices
677:user mode
553:IBM PC/AT
506:real mode
377:paragraph
237:real mode
229:real mode
219:Real mode
167:real mode
136:computer
107:June 2017
1548:Category
1289:ptmalloc
1284:mimalloc
1274:jemalloc
1264:dlmalloc
1160:Hardware
1071:See also
945:CS (the
530:A20 line
381:Gate A20
341:64
330:20 bits
303:16 bits
241:V86 mode
1360:Garbage
1279:libumem
1181:(IOMMU)
618:In the
326:Address
318:
281:Segment
270:
176:. The
91:scholar
1432:Issues
1061:POP CS
1056:POP CS
971:POP CS
943:except
926:paging
806:(e.g.
734:or in
692:thread
669:SWAPGS
656:x86-64
624:paging
299:Offset
253:linear
178:x86-64
93:
86:
79:
72:
64:
1458:Other
1269:Hoard
1175:(TLB)
1169:(MMU)
1029:(PDF)
986:Intel
978:IA-32
952:lcall
845:Limit
782:stack
746:dword
538:PC/XT
493:80286
402:small
201:extra
150:bytes
98:JSTOR
84:books
967:iret
963:lret
842:Base
836:Name
812:movs
808:stos
788:and
786:push
709:and
675:and
654:The
536:and
491:The
390:The
347:must
276:0000
245:byte
160:and
70:news
984:or
982:AMD
957:int
849:DPL
790:pop
743:mov
730:RTL
705:'s
703:gcc
629:386
522:DOS
495:'s
438:by
239:or
235:In
134:x86
53:by
1550::
1000:^
935:.
918:3
901:3
884:0
867:0
810:,
752:42
738::
635:.
542:AT
526:MB
514:16
510:16
366:MB
343:KB
251:a
1132:e
1125:t
1118:v
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1012:"
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482:.
461:)
455:(
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446:(
432:.
120:)
114:(
109:)
105:(
95:¡
88:¡
81:¡
74:¡
47:.
20:)
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