112:
25:
256:(CEI) Interoperability Agreements (IAs), that have defined six generations of the electrical interface of SerDes, at 3.125, 6, 10, 28, 56 and 112 Gb/s. The OIF has announced new projects at 224 Gb/s. The OIF also published three earlier generations of electrical interfaces. These IAs have been adopted or adapted or have influenced high speed electrical interfaces defined by
99:) is a pair of functional blocks commonly used in high speed communications to compensate for limited input/output. These blocks convert data between serial data and parallel interfaces in each direction. The term "SerDes" generically refers to interfaces used in various technologies and applications. The primary use of a SerDes is to provide data transmission over a single line or a
207:. This supports DC-balance, provides framing, and guarantees frequent transitions, allowing a receiver to extract the embedded clock. The control codes allow framing, typically on the start of a packet. The typical 8b/10b SerDes parallel side interfaces have one clock line, one control line and 8 data lines.
119:
The basic SerDes function is made up of two functional blocks: the
Parallel In Serial Out (PISO) block (aka Parallel-to-Serial converter) and the Serial In Parallel Out (SIPO) block (aka Serial-to-Parallel converter). There are 4 different SerDes architectures: (1) Parallel clock SerDes, (2) Embedded
190:
An embedded clock SerDes serializes data and clock into a single stream. One cycle of clock signal is transmitted first, followed by the data bit stream; this creates a periodic rising edge at the start of the data bit stream. As the clock is explicitly embedded and can be recovered from the bit
199:
8b/10b SerDes maps each data byte to a 10-bit code before serializing the data. The deserializer uses the reference clock to monitor the recovered clock from the bit stream. As the clock information is synthesized into the data bit stream, rather than explicitly embedding it, the serializer
155:. The SIPO block then divides the incoming clock down to the parallel rate. Implementations typically have two registers connected as a double buffer. One register is used to clock in the serial stream, and the other is used to hold the data for the slower, parallel side.
142:
The SIPO (Serial Input, Parallel Output) block typically has a receive clock output, a set of data output lines and output data latches. The receive clock may have been recovered from the data by the serial
158:
Some types of SerDes include encoding/decoding blocks. The purpose of this encoding/decoding is typically to place at least statistical bounds on the rate of signal transitions to allow for easier
269:
178:
Parallel clock SerDes is normally used to serialize a parallel bus input along with data address & control signals. The serialized stream is sent along with a reference clock. The clock
191:
stream, the serializer (transmitter) clock jitter tolerance is relaxed to 80–120 ps rms, while the reference clock disparity at the deserializer can be ±50,000 ppm (i.e. 5%).
221:. This scheme statistically delivers DC-balance and transitions through the use of a scrambler. Framing is delivered through the deterministic transitions of the added framing bits.
240:
Bit interleaved SerDes multiplexes several slower serial data streams into faster serial streams, and the receiver demultiplexes the faster bitstreams back to slower streams.
123:
The PISO (Parallel Input, Serial Output) block typically has a parallel clock input, a set of data input lines, and input data latches. It may use an internal or external
54:
232:, and a gearbox that converts the 66b signal to a 16-bit interface. Another serializer then converts this 16-bit interface into a fully serial signal.
131:
that receives the parallel data once per parallel clock, and shifts it out at the higher serial clock rate. Implementations may also make use of a
147:
technique. However, SerDes which do not transmit a clock use reference clock to lock the PLL to the correct Tx frequency, avoiding low
200:(transmitter) clock jitter tolerance is to 5–10 ps rms and the reference clock disparity at the deserializer is ±100 ppm.
76:
324:
Ethernet specification including SerDes combined with 8B/10B encoding/decoding for GE and 64B/66B encoding/decoding for 10GE
249:
355:
136:
37:
163:
47:
41:
33:
323:
303:
315:
58:
287:
127:
to multiply the incoming parallel clock up to the serial frequency. The simplest form of the PISO has a single
298:
100:
253:
111:
340:
225:
148:
124:
224:
Such serializer-plus-64b/66b encoder and deserializer-plus-decoder blocks are defined in the
210:
Such serializer-plus-8b/10b encoder, and deserializer-plus-decoder blocks are defined in the
218:
211:
204:
132:
281:
159:
144:
128:
349:
152:
261:
257:
167:
229:
265:
292:
179:
110:
228:
specification. The transmit side comprises a 64b/66b encoder, a
103:
in order to minimize the number of I/O pins and interconnects.
18:
120:
clock SerDes, (3) 8b/10b SerDes, (4) Bit interleaved SerDes.
335:
295:
list of common protocols that use 8b/10b encoded SerDes
319:by Dave Lewis, National Semiconductor Corporation
217:Another common coding scheme used with SerDes is
16:Serializer/deserializer pair in network equipment
46:but its sources remain unclear because it lacks
139:when transferring data between clock domains.
8:
182:tolerance at the serializer is 5–10 ps rms.
203:A common coding scheme used with SerDes is
341:OIF Common Electrical Interface (CEI) 3.1
77:Learn how and when to remove this message
7:
14:
23:
115:Shows the principle of a SerDes
1:
336:TI SerDes application reports
250:Optical Internetworking Forum
162:in the receiver, to provide
272:and numerous other bodies.
174:Source synchronous clocking
372:
304:Multi-gigabit transceiver
284:- Used to create a SerDes
244:Standardization of SerDes
288:Physical Coding Sublayer
252:(OIF) has published the
32:This article includes a
299:SerDes Framer Interface
125:phase-locked loop (PLL)
93:Serializer/Deserializer
61:more precise citations.
236:Bit-interleaved SerDes
116:
254:Common Electrical I/O
114:
149:harmonic frequencies
356:Digital electronics
317:SerDes Architecture
226:10 Gigabit Ethernet
135:register to avoid
117:
34:list of references
186:Embedded clocking
166:, and to provide
101:differential pair
87:
86:
79:
363:
219:64b/66b encoding
212:Gigabit Ethernet
107:Generic function
82:
75:
71:
68:
62:
57:this article by
48:inline citations
27:
26:
19:
371:
370:
366:
365:
364:
362:
361:
360:
346:
345:
332:
312:
278:
246:
238:
214:specification.
205:8b/10b encoding
197:
188:
176:
151:present in the
133:double-buffered
109:
83:
72:
66:
63:
52:
38:related reading
28:
24:
17:
12:
11:
5:
369:
367:
359:
358:
348:
347:
344:
343:
338:
331:
330:External links
328:
327:
326:
321:
311:
308:
307:
306:
301:
296:
290:
285:
282:Shift register
277:
274:
245:
242:
237:
234:
196:
193:
187:
184:
175:
172:
160:clock recovery
145:clock recovery
129:shift register
108:
105:
85:
84:
42:external links
31:
29:
22:
15:
13:
10:
9:
6:
4:
3:
2:
368:
357:
354:
353:
351:
342:
339:
337:
334:
333:
329:
325:
322:
320:
318:
314:
313:
309:
305:
302:
300:
297:
294:
291:
289:
286:
283:
280:
279:
275:
273:
271:
270:Fibre Channel
267:
263:
259:
255:
251:
243:
241:
235:
233:
231:
227:
222:
220:
215:
213:
208:
206:
201:
195:Data encoding
194:
192:
185:
183:
181:
173:
171:
169:
165:
161:
156:
154:
150:
146:
140:
138:
137:metastability
134:
130:
126:
121:
113:
106:
104:
102:
98:
94:
89:
81:
78:
70:
60:
56:
50:
49:
43:
39:
35:
30:
21:
20:
316:
247:
239:
223:
216:
209:
202:
198:
189:
177:
157:
141:
122:
118:
96:
92:
90:
88:
73:
64:
53:Please help
45:
153:data stream
59:introducing
310:References
262:Infiniband
258:IEEE 802.3
168:DC balance
67:March 2024
230:scrambler
350:Category
276:See also
266:RapidIO
164:framing
55:improve
293:8b/10b
180:jitter
97:SerDes
40:, or
248:The
352::
268:,
264:,
260:,
170:.
91:A
44:,
36:,
95:(
80:)
74:(
69:)
65:(
51:.
Text is available under the Creative Commons Attribution-ShareAlike License. Additional terms may apply.
