833:
EQU 8 R9 EQU 9 R10 EQU 10 R11 EQU 11 R12 EQU 12 R13 EQU 13 R14 EQU 14 R15 EQU 15 * DATA WP,ENTRY,0 * * Workspace (On the 990 we can "preload" registers) * WP DATA 0 R0 DATA 0 R1 DATA >1600 R2 - End of program SVC DATA >0000 R3 - Open I/O opcode DATA >0B00 R4 - Write I/O opcode DATA >0100 R5 - Close I/O opcode DATA STRING R6 - Message address DATA STRLEN R7 - Message length DATA 0 R8 DATA 0 R9 DATA 0 R10 DATA 0 R11 DATA 0 R12 DATA 0 R13 DATA 0 R14 DATA 0 R15 * * Terminal SVC block * TRMSCB BYTE 0 SVC op code (0 = I/O) TRMERR BYTE 0 Error code TRMOPC BYTE 0 I/O OP CODE TRMLUN BYTE TMLUNO LUNO TRMFLG DATA 0 Flags TRMBUF DATA $ -$ Buffer address TRMLRL DATA $ -$ Logical record length TRMCHC DATA $ -$ Character count * * Message * STRING TEXT 'Hello world!' BYTE >D,>A STRLEN EQU $ -STRING EVEN PAGE * * Main program entry * ENTRY MOVB R3,@TRMOPC Set open opcode in SCB SVC @TRMSCB Open terminal MOVB @TRMERR,R0 Check for error JNE EXIT MOVB R4,@TRMOPC Set write opcode MOV R6,@TRMBUF Set buffer address MOV R7,@TRMLRL Set logical record length MOV R7,@TRMCHC and character count SVC @TRMSCB Write message MOVB @TRMERR,R0 Check for error JNE CLOSE CLOSE MOVB R5,@TRMOPC Set close opcode SVC @TRMSCB Close terminal EXIT SVC R2 Exit program * END
843:
R13 EQU 13 R14 EQU 14 R15 EQU 15 * * Terminal CRU bits * TRMCRU EQU >0 Terminal device address XMIT EQU 8 DTR EQU 9 RTS EQU 10 WRQ EQU 11 RRQ EQU 12 NSF EQU 13 * PAGE * * Main program entry * ENTRY LWPI WP Load our workspace pointer BLWP @PRINT Call our print routine DATA STRING DATA STRLEN IDLE * WP BSS 32 Main program workspace * * Message * STRING TEXT 'Hello world!' BYTE >D,>A STRLEN EQU $ -STRING EVEN PAGE * * Print a message * PRINT DATA PRWS,PRENT PRENT EQU $ MOV *R14+,R2 Get buffer address MOV *R14+,R1 Get message length SBO DTR Enable terminal ready SBO RTS PRI010 LDCR *R2+,8 Send out a character TB WRQ Wait until done JNE $ -2 SBZ WRQ DEC R1 JGT PRI010 RTWP * PRWS DATA 0,0,0,0,0,0,0,0 DATA 0,0,0,0,TRMCRU,0,0,0 * END ENTRY
20:
832:
IDT 'HELLO' TITL 'HELLO - hello world program' * DXOP SVC,15 Define SVC TMLUNO EQU 0 Terminal LUNO * R0 EQU 0 R1 EQU 1 R2 EQU 2 R3 EQU 3 R4 EQU 4 R5 EQU 5 R6 EQU 6 R7 EQU 7 R8
842:
IDT 'HELLO' TITL 'HELLO - hello world program' * R0 EQU 0 R1 EQU 1 R2 EQU 2 R3 EQU 3 R4 EQU 4 R5 EQU 5 R6 EQU 6 R7 EQU 7 R8 EQU 8 R9 EQU 9 R10 EQU 10 R11 EQU 11 R12 EQU 12
642:
The first field of the first word is the opcode, the second field of the first word indicates a checkpoint register; the first field of the second word is the byte count field, the second field is the destination operand and the third field is the source operand. These instructions were supported on
98:
The TI-990 had a facility to allow extended operations through the use of plug in hardware. If the hardware is not present the CPU traps to allow software to perform the function. The operation code (XOP) allowed for 15 attached devices on a system. Although, device 15 was reserved in TI's operating
85:
On the TI-990, registers are stored in memory and are referred to through a hardware register called the
Workspace Pointer. The concept behind the workspace is that main memory was based on the new semiconductor RAM chips that TI had developed and ran at the same speed as the CPU. This meant that it
807:
The first field of the first word is the opcode, the second field of the first word specifies the destination length; the first field of the second word specifies the source length, the second field is the destination operand and the third field is the source operand. This instruction is only
725:
The first field of the first word is the opcode, the second field of the first word indicates a width; the first field of the second word is the position, the second field is the destination operand and the third field is the source operand. These instructions supported on the 990/12.
191:
The instructions are grouped according to which addressing modes and how many operands they accept. A group is defined by the layout of bit-fields within the instruction word. The leftmost bits of the instruction word are sufficient to identify its group.
713:
The first field of the first word is the opcode, the second field of the first word indicates a width; the first field of the second word is the position, the second field is the source operand. This instruction supported on the 990/12.
681:
The first word is the opcode; in the second word, the first field is the byte count field, the second field is the shift count and the third field is the source operand. These instructions are supported on the 990/12 and 990/10A.
594:
The first word is the opcode; in the second word, the first field is the byte count field, the second field is the destination operand and the third field is the source operand. These instructions are supported on the 990/12.
792:
The first word is the opcode; the first field of the second word is the condition code field, the second field is the destination operand and the third field is the source operand. These instructions supported on the 990/12.
89:
There are only three hardware registers in the 990: the
Workspace Pointer (WP), the Program Counter (PC) and the Status register (ST). A context switch entailed the saving and restoring of only the hardware registers.
743:
The first word is the opcode; the first field of the second word is the value field and the second field is the register and the third field is the relative offset. These instructions supported on the 990/12.
42:(TI) in the 1970s and 1980s. The TI-990 was a replacement for TI's earlier minicomputer systems, the TI-960 and the TI-980. It had several unique features, and was easier to program than its predecessors.
242:
The first field of the word specifies the operation to be performed, the second field is a relative offset to where to go, for JMP instructions, or the relative offset for CRU bit addressing.
318:
The first field of the word specifies the operation to be performed, the second field is the bit width of the operation, the third field provides information for locating the second operand.
86:
didn't matter if the "registers" were real registers in the CPU or stored in memory. When the
Workspace Pointer is loaded with a memory address, that address is the origin of the registers.
839:
The following program is a standalone version that prints on the serial terminal connected to CRU address 0. It illustrates the CRU I/O and workspace linkage for the PRINT subroutine.
854:
All models supported the
Communications Register Unit (CRU) which is a serial bit addressable I/O bus. Also, supported on higher end models was the TILINE I/O bus which is similar to
890:
TI-990/12 — Schottky TTL processor with memory mapping to 2 MB of ECC Memory, workspace caching, hardware floating point, extended mode instructions and writeable control store
696:
The first word is the opcode; the first field of the second word is the position field and the second field is the source operand. These instructions were supported on the 990/12.
836:
This program can be run on a TI-990 simulator, such as Dave Pitts's "sim990", which emulates the TI-990 and includes software kits for native operating systems (including DX10).
781:
The first word is the opcode; the first field of the second word is the destination operand and the second field is the source operand. This instruction supported on the 990/12.
525:
The first field specifies the operation, the second field specifies the register if applicable. The third field, if applicable, specifies an immediate operand in a second word.
188:
The 990/4, 990/5, 990/9 instruction sets consisted of 69 instructions, the 990/10 had 72 instructions, the 990/10A had 77 instructions and the 990/12 had 144 instructions.
118:. The instruction formats allowed for one, two and three word instructions. The model 990/12 CPU allowed for a four word instruction with the extended mode operations.
563:
The first field of the word specifies the operation, the second field provides the register, the third field provides information for locating the second operand.
298:
The first field of the word specifies the operation, the second field provides the register, the third field provides information for locating the second operand.
577:
The first field specifies the operation, the second field specifies the map file (0=kernel, 1=user) and the third field specifies a register with an address.
332:
The first field of the word specifies the operation to be performed, the second field is the shift count, the third field specifies the register to shift.
636:
The multiple precision instructions allowed for logic and integer arithmetic on operands from 1-15 bytes long. *SM and *AM were supported on the 990/10A.
144:
2. Indexed: OPR @MEM(R); R contains index value (offset in bytes) to add to address MEM. R0 is not used in indexing and allows direct memory addressing
57:
between programs. This was enabled through the use of register values stored in main memory that could be swapped by changing a single pointer.
851:
The TI-990 processors fell into several natural groups depending on the original design upon which they are based and which I/O bus they used.
198:
The first field of the word specifies the operation to be performed, the remaining two fields provide information for locating the operands.
1011:
758:
The first field of the word is the opcode and the second field is the register specification. These instructions supported on the 990/12.
68:. Intended for use in low-end models of the TI-990, it retained the 990's memory-to-memory architecture. This chip was widely used in the
862:. The TILINE also supported a master/slave relationship that allowed multiple CPU boards in a common chassis with arbitration control.
961:
352:
The first field specifies the operation to be performed, the second field provides information for locating the second operand.
147:
3. Indirect
Autoincrement: OPR *R+ ; R contains address of operand. Later, increment R by the length of the operand type
855:
99:
systems for the
Supervisor Call (SVC), through which user programs requested I/O and other operating systems services.
115:
1021:
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1016:
583:
This instruction was supported on the 990/10A and 990/12, or the 990/10 with memory-map option installed.
141:
1. Indirect register - the register contains the address of the operand: OPR *R ; R points to operand
72:
home computer, where details of its minicomputer-style memory model presented significant disadvantages.
826:
981:— Includes a simulator, cross assembler, cross linker, utilities and Operating System images.
822:
363:
989:
155:
R0 - shift counter, extended mode counter, Floating point
Accumulator (FAC) most significant word
50:
39:
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TI-990/10A — TMS-99000 microprocessor with memory mapping support to 1 MB of memory
65:
54:
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0. Register - the value is to or from a register: OPR R ; R contains operand
949:
992:
Site detailing the preservation and restoration of TI 990 series minicomputers
882:
580:
The given map file is loaded with 6 words from the address in the register.
103:
870:
The following models used the TILINE as their principal mass storage bus:
69:
978:
151:
Several registers had defined purposes in many instructions. These are:
938:
904:
881:
TI-990/10 — TTL processor with memory mapping support to 2 MB of
875:
61:
859:
32:
167:
R11 - return linkage, or pointer to operand of XOP (privileged mode)
18:
933:
19:
276:
JOP (jump if odd parity - only relevant after byte operations)
984:
899:
The following models used the CRU as their principal bus:
405:
LDD (long distance destination, 990/10, 990/10A, 990/12)
60:
TI later implemented the TI-990 in a single chip, the
258:
JHE (jump if logically greater than or equal to zero)
556:
BLSK (branch immediate push link onto stack, 990/12)
402:
LDS (long distance source, 990/10, 990/10A, 990/12)
45:Among its core concepts was the ability to support
463:The word specified the operation to be performed.
998:, DeGolyer Library, Southern Methodist University
910:TI-990/9 — The original TTL implementation
515:CED (convert extended integer to double, 990/12)
509:CDE (convert double to extended integer, 990/12)
16:Series of 16-bit computers by Texas Instruments.
512:CER (convert extended integer to real, 990/12)
506:CRE (convert real to extended integer, 990/12)
102:On the 990/12, the XOP instruction could run
8:
825:" program in TI-990 assembler, to run under
106:from the machine's Writable Control Store.
748:SRJ (subtract value from register and jump)
650:CRC (cyclic redundancy code calculation)
356:BLWP (branch and load workspace pointer)
282:JH (jump if logically greater than zero)
252:JLE (jump if less than or equal to zero)
170:R12 - CRU base address (privileged mode)
765:LIM (load interrupt mask from register)
647:SNEB (search string for not equal byte)
553:LWPI (load workspace pointer immediate)
497:CDI (convert double to integer, 990/12)
441:CID (convert integer to double, 990/12)
411:MPYS (multiply signed, 990/10A, 990/12)
408:BIND (branch indirect, 990/10A, 990/12)
686:SRAM (shift right arithmetic multiple)
485:EMD (execute micro diagnostic, 990/12)
817:Assembly Language Programming Example
689:SLAM (shift left arithmetic multiple)
494:CRI (convert real to integer, 990/12)
420:CIR (convert integer to real, 990/12)
414:DIVS (divide signed, 990/10A, 990/12)
279:JL (jump if logically less than zero)
7:
962:990 Computer Family Systems Handbook
941:Distributed Network Operating System
751:ARJ (add value to register and jump)
529:LIMI (load interrupt mask immediate)
134:(R is a general register, 0 to 15.)
907:microprocessor with 56 KB of memory
878:microprocessor with 64 KB of memory
800:SLSP (search list physical address)
659:SEQB (search string for equal byte)
229:SZCB (set zeros corresponding byte)
49:using a software-switchable set of
797:SLSL (search list logical address)
614:DBC (decimal to binary conversion)
611:BDC (binary to decimal conversion)
235:SOCB (set ones corresponding byte)
226:SZC (set zeros corresponding word)
14:
518:XIT (exit floating point, 990/12)
305:CZC (compare zeros corresponding)
232:SOC (set ones corresponding word)
53:that allowed it to perform rapid
703:TCMB (test and clear memory bit)
491:DINT (disable interrupt, 990/12)
302:COC (compare ones corresponding)
990:ti990.co.uk in internet archive
488:EINT (enable interrupt, 990/12)
473:RTWP (return workspace pointer)
261:JGT (jump if greater than zero)
985:Translator of SCI 990 to COBOL
967:990 Assembler Reference Manual
923:were available for the TI-990
706:TSMB (test and set memory bit)
547:STWP (store workspace pointer)
1:
668:MVSK (move string from stack)
173:R13 - Saved Workspace Pointer
164:R3 - FAC+6 (double precision)
161:R2 - FAC+4 (double precision)
158:R1 - FAC+2 (single precision)
771:LWP (load workspace pointer)
671:POPS (pop string from stack)
503:NEGD (negate double, 990/12)
447:MD (multiply double, 990/12)
444:SD (subtract double, 990/12)
372:NEG (twos complement negate)
336:SRA (shift right arithmetic)
273:JNO (jump if overflow clear)
264:JNE (jump if not equal zero)
249:JLT (jump if less than zero)
1012:Texas Instruments computers
762:STPC (store PC in register)
718:IOF (invert order of field)
674:PSHS (push string to stack)
665:MVSR (move string reversed)
482:LREX (load ROM and execute)
342:SLA (shift left arithmetic)
179:R15 - Saved Status Register
176:R14 - Saved Program Counter
1038:
768:LST (load status register)
500:NEGR (negate real, 990/12)
456:STD (store double, 990/12)
450:DD (divide double, 990/12)
426:MR (multiply real, 990/12)
423:SR (subtract real, 990/12)
345:SRC (shift right circular)
246:JMP (jump unconditionally)
116:orthogonal instruction set
110:Orthogonal instruction set
64:, one of the first 16-bit
996:Texas Instruments records
808:supported on the 990/12.
602:RTO (right test for ones)
339:SRL (shift right logical)
288:SBZ (set CRU bit to zero)
267:JNC (jump if carry clear)
114:The TI-990 used a fairly
774:LCS (load control store)
605:LTO (left test for ones)
453:LD (load double, 990/12)
435:STR (store real, 990/12)
429:DR (divide real, 990/12)
311:XOP (extended operation)
285:SBO (set CRU bit to one)
23:TI-990 programmers panel
979:Dave Pitts' TI 990 page
567:MPY (unsigned multiply)
438:AD (add double, 990/12)
399:SETO (set word to ones)
387:DECT (decrement by two)
381:INCT (increment by two)
270:JOC (jump if carry set)
629:SM (subtract multiple)
544:CI (compare immediate)
432:LR (load real, 990/12)
24:
812:EP (extend precision)
789:Group 20 instructions
755:Group 18 instructions
740:Group 17 instructions
722:Group 16 instructions
700:TMB (test memory bit)
693:Group 14 instructions
678:Group 13 instructions
653:TS (translate string)
639:Group 12 instructions
591:Group 11 instructions
570:DIV (unsigned divide)
417:AR (add real, 990/12)
375:INV (ones complement)
122:Architectural details
22:
945:From third parties:
804:Group 21 instruction
778:Group 19 instruction
710:Group 15 instruction
617:SWPM (swap multiple)
574:Group 10 instruction
560:Group 9 instructions
538:ANDI (and immediate)
522:Group 8 instructions
460:Group 7 instructions
393:ABS (absolute value)
390:BL (branch and link)
349:Group 6 instructions
329:Group 5 instructions
315:Group 4 instructions
295:Group 3 instructions
195:Group 1 instructions
785:MOVA (move address)
730:INSF (insert field)
656:CS (compare string)
626:ANDM (and multiple)
620:XORM (xor multiple)
587:LMF (load map file)
550:STST (store status)
532:LI (load immediate)
239:Type 2 instructions
184:TI-990 instructions
51:processor registers
736:XF (extract field)
733:XV (extract value)
662:MOVS (move string)
541:ORI (or immediate)
535:AI (add immediate)
308:XOR (exclusive or)
255:JEQ (jump if zero)
217:SB (subtract byte)
94:Extended operation
25:
921:operating systems
915:Operating systems
903:TI-990/4 —
874:TI-990/5 —
866:TILINE/CRU models
632:AM (add multiple)
623:ORM (or multiple)
608:CNTO (count ones)
396:SWPB (swap bytes)
291:TB (test CRU bit)
223:CB (compare byte)
214:S (subtract word)
127:General register
40:Texas Instruments
1029:
1022:16-bit computers
479:CKOF (clock off)
470:RSET (cpu reset)
369:CLR (clear word)
325:STCR (store CRU)
220:C (compare word)
205:MOVB (move byte)
129:addressing modes
55:context switches
47:multiprogramming
31:was a series of
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599:NRM (normalize)
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476:CKON (clock on)
467:IDLE (cpu idle)
461:
384:DEC (decrement)
378:INC (increment)
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322:LDCR (load CRU)
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202:MOV (move word)
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66:microprocessors
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36:minicomputers
34:
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21:
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821:A complete "
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643:the 990/12.
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208:A (add word)
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950:UCSD Pascal
858:'s popular
1006:Categories
930:TX990/TXDS
883:ECC memory
359:B (branch)
81:Workspaces
926:From TI:
104:microcode
919:Several
76:Features
70:TI-99/4A
38:sold by
956:Sources
905:TMS9900
876:TMS9900
364:execute
62:TMS9900
860:UNIBUS
33:16-bit
29:TI-990
939:DNOS
934:DX10
827:DX10
27:The
856:DEC
362:X (
1008::
829::
366:)
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