535: ; ;************************************************ ; CALL SUBROUTINE ; DEFINE XOP: DXOP CALL,6 ; CALLING METHOD: CALL @SUBROUTINE_ADDRESS ; R10 <=> STACK POINTER ;************************************************* ; ED32 C2AD 0014 XOP6: MOV @2*R10(R13),R10 ;GET STACK POINTER ED36 064A DECT R10 ;DECREMENT STACK POINTER ED38 C68E MOV R14,*R10 ;PUSH RETURN PC ONTO STACK ED3A C38B MOV R11,R14 ;MOVE EA INTO R14 (PC) FOR CALL ED3C CB4A 0014 MOV R10,@2*R10(R13) ;UPDATE STACK POINTER ED40 0380 RTWP ;WE ARE NOW USING THE ORIGINAL WP
873:
711:
Macrostore in the TMS99110A microprocessor contains floating point instructions which are available as part of the machine language instruction set, while the baseline TMS99105A does not. Both chips can implement
Macrostore instructions in an external ROM. A third member of the TMS99000 family, the TMS99120, was announced but may never have been commercially produced. The on-chip ROM Macrostore in the TMS99120 was to contain run-time support routines for the PASCAL high-level language.
629:
155:
518:;*********************************** ; ; THIS INTERRUPT SIMULATES DMA CONTROL ; ORGANISED AS FOLLOWS: ; ; R9 HOLDS CURRENT COMMAND, E.G. ; IOREAD(34B8H): STCR *R8+,BYTEWIDE ;BYTE WIDE FDC DATA READ ; IOWRITE(30B8H):LDCR *R8+,BYTEWIDE ;BYTE WIDE FDC DATA WRITE ; R8 HOLDS THE CURRENT DMA ADDRESS. ; R12 HOLDS THE CURRENT IO PORT - DATREG ;************************************ INTDRQ X R9 ;CAN BE EITHER READ or WRITE RTWP
532:
hardware in future versions of the 990 minicomputer series. An example of such actions can be shown in the code below where a CALL function is implemented using and XOP 6 Instruction. The beauty of this implementation of a CALL function using and XOP, is that it is straightforward to add checks to determine if the Stack has overflowed; for example C R10,@2*R9(R13), where R9 points to the address of the stack limit.
885:
861:
849:
551:
696:
714:
The instruction set for the TMS99000 family extends the 9900 instruction set while keeping compatibility. The additional instructions includes those for signed multiply and divide (first appearing in the TMS9995), long-word shift, add, and subtract; load status register, load workspace pointer, stack
679:
The second generation of the TMS9900 family of microprocessors was the TMS9995 which provided "functional performance at speeds 3 times faster than any previous 9900 family processor", largely due to the inclusion of instruction prefetch technology. In the home computer arena, the TMS9995 only found
483:
Addressing modes include
Immediate (operand in instruction), Direct or "Symbolic" (operand address in instruction), Register (operand in workspace register), Register Indirect (operand address in workspace register) with or without auto-increment, Indexed (operand address in instruction indexed with
524:
The TMS9900 also supports the eXtended OPeration (XOP) instruction. XOP is given a number in the range 0-15 as well as a source address. When invoked, the instruction will perform a context switch through one of sixteen vectors at predefined locations in memory. The XOP instruction also places the
498:
The instruction set also contains a Branch and Link (BL) opcode that only saves PC to register 11 without changing WP. In this case, a branch instruction (B) using WR11 as the destination address can serve as the return opcode, but BL-type subroutines cannot be nested without the programmer taking
463:
There is no dedicated stack pointer register. Instead, branch instructions exist that save the program counter to a register (Branch and Link), or change the register context (Branch and Link
Workspace, or XOP). The 16 hardware and 16 software interrupt vectors each consist of a pair of PC and WP
710:
The TMS99000 family includes two microprocessors, the TMS99105A and the TMS99110A, which are identical except for the contents of on-chip macrostore ROM memory (macrostore memory contains added functions or instructions through emulation routines written in standard machine code). The on-chip ROM
562:
The TMS9900 was implemented in an N-channel silicon gate MOS process, which required +5 V, −5 V and +12 V power supplies and a four-phase (non-overlapping) clock with a maximum frequency of 3 MHz (333 ns cycle), usually generated from a 48 MHz crystal using a TIM9904 (aka
494:
For subroutine calls, the Branch and Load
Workspace Pointer (BLWP) instruction loads new WP and PC values, then saves the values of WP, PC and ST to the (new) registers 13, 14 and 15 respectively. At the end of the subroutine, the Return Workspace Pointer (RTWP) restores these in reverse order.
514:
instruction), for creating indexed-opcode tables as used in byte-code interpreters and can also be used to perform a time critical I/O instruction during an interrupt. An example of its utility is shown in the code below where an interrupt being serviced in a very encapsulated manner that would
226:
The downside to this approach is that accessing these registers is more time-consuming. In a minicomputer implementation with fast memory, the effect is relatively small and the upside in a real-time or multi-tasking environment is significant as context switches are common. In other roles, like
531:
XOP can be used to implement a system call facility. In TI's DX10 operating system, XOP 15 invokes a system call. A programmer might define an assembler macro, for example SVC, which invokes XOP 15. Another use of XOP was to implement instructions in software which might be handled by dedicated
487:
The most important dual-operand instructions (add, subtract, compare, move etc.) contain 2-bit addressing mode and 4-bit register selector fields for both source and destination operands. In the opcode, "Symbolic" mode is represented as
Indexed mode with the register field set to 0, therefore
715:
operations, multiprocessor support, bit manipulation. Members of the family can access 256KB of memory through code/data segmentation, and may use the TIM99610 memory mapper to address up to 16MiB. The architecture contains many other advances over the TMS9900 and TMS9995.
655:
TI developed the TM990 series of computer modules, including CPU, memory, I/O, which when plugged into a card frame could form a 16-bit minicomputer. These were typically used for process control. A microprocessor trainer was released in the form of the TM990/189.
566:
The shortest instructions require eight clock cycles or 2.7 μs to complete (assuming 0 external wait cycles), many others run between 10 and 14 cycles (3.3...4.7 μs); the longest-running instruction (DIV) can take up to 124 cycles (41.3 μs).
223:, which can be accomplished by changing a single register, the Workspace Pointer, to point to the first entry in a list of register values. More traditional designs would require the entire set of internal registers to be stored out to memory or the stack.
488:
workspace register 0 (WR0) cannot be used in
Indexed mode. In less frequently used dual-operand instructions like XOR, the destination operand must be a workspace register (or workspace register pair in the case of multiply and divide instructions).
601:
The hardware interrupt system supports a 4-bit interrupt priority input, which needed to be higher than the priority level stored in the status register (bits 12−15) in order for the interrupt request to be served. In addition, the
242:, he recalled. One factor was the lack of a roadmap for accessing more than 64K of logical memory. The 9900 family could expand its address space to 16MiB only by page-mapping; the 99000 could address 256K through segments.
586:
CPU), keeping external memory connections simple. Contrary to the convention used by many other manufacturers, TI labeled the most significant address and data lines "A0" and "D0", respectively. All internal data paths and the
130:
Microcomputer-on-chip implementations of the 9900 in 40-pin packages included the TMS9940, TMS9980/81, TMS9995. The TMS99105/10 was the last iteration of the 9900 in 1981 and incorporated features of TI's 990/10 minicomputer.
644:
home computers. Unfortunately, to reduce the production costs, TI chose to use in these systems just 128 16-bit words of the fast kind of RAM that the TMS9900 could access directly. The rest of the memory was 16KB of
210:
The minicomputer roots of the TMS9900 give rise to a number of architectural features that are not commonly found on designs that started from a blank sheet. Notable among these was the TMS9900's use of
453:
is entered, only the single workspace register needs to be changed instead of requiring registers to be saved individually. Bits are numbered unconventionally with the most significant bit being 0.
528:
XOP is less flexible than a BLWP, as the transfer vectors have to be at fixed locations, but allows one source operand to be directly addressed rather than passed in a register or otherwise.
491:
Flow control is facilitated through a group of one unconditional and twelve conditional Jump instructions. Jump targets are relative to PC with an offset of -128 to +127 word addresses.
123:
format made it more expensive to implement in smaller machines than the more common 40-pin format, and it saw relatively few design wins outside TI's own use. Among those uses was their
234:
gave a presentation of the TMS99110, then code-named “Alpha”, to an IBM group developing a personal computer. "We wouldn't know until 1981 just what we had lost" because IBM chose the
521:
this common piece of code during the interrupt that could be used by both I/O read and write commands. Similar methods could be employed in any debugging methods wanting to be used.
525:
effective address of the source operand in register 11 of the new workspace. The context saving feature of the XOP instruction can also be used as to implement inline debugging.
613:("CRU") designed for interfacing with external shift registers, with dedicated instructions supporting access to fields of 1−16 bit width out of a total of 4096 addressable bits.
495:
Using BLWP/RTWP, it is possible to nest subroutine calls despite the absence of a stack, however, the programmer needs to assign the appropriate register workspace explicitly.
985:
227:
single-user microcomputers, this tradeoff may not be worthwhile. The 40-pin implementations of the 9900 included 128 or 256 bytes of fast onboard RAM for registers.
938:
1286:
464:
values, so the register context switch is automatically performed by an interrupt as well. Stacks can be implemented atop either of these mechanisms.
707:
minicomputer as a cost reduction. Unfortunately, by the time the 990/10A made it to market, the end of the minicomputer era was already in sight.
1036:
692:: the Powertran Cortex. It was planned to be used in the TI-99/2 & TI-99/8 computer systems, but neither advanced past the prototype stage.
598:(DMA). Memory accesses are always 16 bits wide, with the CPU automatically performing read-before-write operations for byte-wide accesses.
230:
TI used the same architecture across different divisions for corporate synergy: "one company, one computer architecture". In the late 1970s
472:
The TMS9900 has 69 instructions which are one, two or three words long and always word-aligned in memory. The instruction set is fairly
1209:
993:
628:
1291:
1017:
460:
ordering convention. The TMS9900 is a classic 16 bit machine with an address space of 2 bytes (65,536 bytes or 32,768 words).
445:
where the processor's 16 general purpose user registers (each 16 bits wide) are kept. This architecture allows for quick
438:
958:
652:
that was accessible only indirectly through the video display controller, which crippled the performance of the TI-99/4.
649:
872:
826:
TMS99000 family microprocessor with floating point instructions pre-programmed into the on-chip
Macrostore ROM memory
834:
TMS99000 family microprocessor with run-time support routines for the PASCAL high-level language pre-programmed into
473:
1129:
909:
836:
the on-chip
Macrostore ROM memory (microprocessor was announced but may never have been commercially produced)
660:
250:
143:
83:
542:, the TMS9900 had smaller programs. Some disadvantages were the small address space and need for fast RAM.
703:
TI later developed the more powerful TMS99000 family of microprocessors, which was used as the CPU in the
197:
588:
507:
207:, some of which predated the TMS9900, the 9900 was a single-chip, self-contained 16-bit microprocessor.
51:
142:. With no obvious future for the chip, TI turned its attention to special-purpose processors like the
667:
based on the TMS9900 and a full software stack to go with it. They later went on to be co-founders of
595:
571:
555:
442:
120:
503:
154:
1053:
884:
426:
212:
159:
71:
116:
architecture in a single-chip format, and was initially used for low-end models of that lineup.
1281:
1189:
617:
220:
193:
106:
28:
981:
860:
848:
231:
579:
434:
430:
88:
2 internally located in processor (WP, ST) 16 × 16-bit workspace located in external RAM
610:
446:
181:
139:
102:
1275:
582:
to be brought out on dedicated pins without the use of multiplexing (unlike e.g. the
396:
173:
787:
TMS9940 with 8KB ROM, 256B RAM, and an 8-bit external bus, c. 1978 (never released)
189:
185:
169:
113:
476:, meaning that with few exceptions, instructions can use all methods of accessing
1265:
803:
Improved TMS9985-like, no ROM. Used in the TI-99/2 & TI-99/8 prototypes, the
1149:
1109:
808:
685:
575:
401:
216:
134:
By the mid-1980s the microcomputer field was moving to 16-bit systems like the
804:
681:
633:
583:
539:
511:
457:
450:
391:
235:
135:
61:
671:, in part based on software first developed for these TMS9900 based systems.
664:
550:
386:
695:
606:
input provides a non-maskable interrupt facility with a dedicated vector.
668:
641:
594:
The processor can be paused with the address bus tri-stated for external
246:
245:
After dropping out of the personal computer market with products such as
124:
574:. The comparatively large number of pins allowed for the 15-bit (word)
477:
249:, the company microprocessor division eventually switched focus to the
940:
704:
239:
204:
200:
166:
110:
99:
769:
Microcontroller with 2KB ROM, 128B RAM, decrementer, CRU bus, 1979
510:
the instruction in a register. It can be used for debugging (as a
1054:"Using TMS 9000 XOP Instruction to implement a Debugging Function"
761:
Single chip implementation, 1976, used in the TI-99/4(A) computer
694:
646:
627:
549:
177:
153:
1228:
1012:
1010:
986:"The Texas Instruments 99/4: World's First 16-Bit Home Computer"
1169:
127:
home computers, which ultimately sold about 2.8 million units.
570:
The chip was packaged in a (then unusual) 64-pin, 0.9" wide
437:(ST), and Workspace Pointer register (WP). The WP register
484:
workspace register content), and
Program Counter Relative.
1037:"DX10 Operating System Release 3.5 System Design Document"
1251:. Texas Instruments Limited. 1981. pp. 3–25 onwards.
745:
Multi-chip implementation for minicomputer systems, 1975
165:
The TMS9900 was designed as a single chip version of the
98:
was one of the first commercially available, single-chip
1130:"Programmable Calculators - Texas Instruments TM990/189"
196:. Unlike multi-chip 16-bit microprocessors such as the
818:
Baseline member of the TMS99000 microprocessor family
1110:"Stuart's TM 990 Series 16-Bit Microcomputer Modules"
636:, a 1983 home computer based on the TMS9995 processor
737:
Early multi-chip CPU for minicomputer systems, 1974
82:
70:
60:
50:
42:
34:
24:
1096:
1084:
1072:
753:Multi-chip implementation, faster than 990/10
158:TMS9900JL in ceramic package with gold-plated
620:fashion to the regular address and data bus.
8:
1249:Microsystems Designers Handbook, 2nd Edition
1042:. Texas Instruments, Inc. 1982. p. 8.1.
19:
515:otherwise require many more instructions.
684:, an esoteric TI99-4/A upgrade called the
105:. Introduced in June 1976, it implemented
1217:. Texas Instruments Inc. 1981. p. 2.
1025:. Texas Instruments Inc. 1976. p. 3.
946:. Texas Instruments Inc. 1982. p. 1.
795:Improved 9980, used in military hardware
722:
616:Parallel peripherals can be attached in
959:"99000 "Alpha" Performance Comparisons"
925:
901:
841:
609:The TMS9900 CPU also contains a 16-bit
425:The TMS9900 has three internal 16-bit
260:
18:
188:mN601 were both one-chip versions of
138:and newer 16/32-bit designs like the
7:
933:
931:
929:
499:actions to save the return address.
1019:TMS9900 Microprocessor Data Manual
779:8-bit databus versions of TMS9900
675:TMS9900 Family Product Development
554:TMS9900 pin configuration (64-Pin
253:special-purpose processor series.
14:
1287:Texas Instruments microprocessors
883:
871:
859:
847:
699:TMS9900NL in plastic DIP package
538:In typical comparisons with the
506:"X" (eXecute). This instruction
563:74LS362) clock generator chip.
1266:TMS9900 manuals and references
468:Instruction set and addressing
456:Addresses refer to bytes with
441:to a base address in external
1:
640:The TMS9900 was used in the
1150:"Marinchip Systems history"
957:Guttag, Karl (1980-04-14).
688:, and a project printed in
1308:
1211:TMS9995 marketing brochure
368:
357:
912:is close in release date.
910:General Instrument CP1600
411:
408:
371:
360:
77:
807:and the Geneve computer
663:and Dan Drake developed
502:The TMS9900 supports an
144:Texas Instruments TMS320
219:. This allows for fast
1292:16-bit microprocessors
1229:"Powertran Cortex.com"
1097:Texas Instruments 1976
1085:Texas Instruments 1976
1073:Texas Instruments 1976
700:
637:
559:
198:National Semiconductor
172:series, much like the
162:
146:, introduced in 1983.
698:
631:
553:
215:that are mapped into
157:
16:16-bit microprocessor
1170:"Marinchip software"
642:TI-99/4 and TI-99/4A
596:direct memory access
480:(addressing modes).
125:TI-99/4 and TI-99/4A
659:In the late 1970's
504:execute instruction
263:
213:processor registers
21:
701:
638:
591:are 16 bits wide.
560:
375:Workspace Pointer
262:TMS9900 registers
261:
180:(12 bit), and the
176:was a single chip
163:
1190:"Autocad history"
982:Rhines, Walden C.
840:
839:
690:Electronics Today
447:context switching
423:
422:
419:
418:
221:context switching
107:Texas Instruments
92:
91:
29:Texas Instruments
1299:
1253:
1252:
1245:
1239:
1238:
1236:
1235:
1225:
1219:
1218:
1216:
1206:
1200:
1199:
1197:
1196:
1186:
1180:
1179:
1177:
1176:
1166:
1160:
1159:
1157:
1156:
1146:
1140:
1139:
1137:
1136:
1126:
1120:
1119:
1117:
1116:
1106:
1100:
1094:
1088:
1082:
1076:
1070:
1064:
1063:
1061:
1060:
1050:
1044:
1043:
1041:
1033:
1027:
1026:
1024:
1014:
1005:
1004:
1002:
1001:
996:on June 22, 2017
992:. Archived from
978:
972:
971:
969:
968:
963:
954:
948:
947:
945:
935:
913:
906:
887:
875:
863:
851:
723:
415:Status Register
364:Program Counter
268:
267:
264:
232:Walden C. Rhines
22:
1307:
1306:
1302:
1301:
1300:
1298:
1297:
1296:
1272:
1271:
1262:
1257:
1256:
1247:
1246:
1242:
1233:
1231:
1227:
1226:
1222:
1214:
1208:
1207:
1203:
1194:
1192:
1188:
1187:
1183:
1174:
1172:
1168:
1167:
1163:
1154:
1152:
1148:
1147:
1143:
1134:
1132:
1128:
1127:
1123:
1114:
1112:
1108:
1107:
1103:
1095:
1091:
1083:
1079:
1071:
1067:
1058:
1056:
1052:
1051:
1047:
1039:
1035:
1034:
1030:
1022:
1016:
1015:
1008:
999:
997:
980:
979:
975:
966:
964:
961:
956:
955:
951:
943:
937:
936:
927:
922:
917:
916:
907:
903:
898:
891:
888:
879:
876:
867:
864:
855:
852:
835:
775:
721:
677:
626:
548:
536:
519:
470:
435:Status register
431:Program counter
348:
343:
338:
333:
328:
323:
318:
313:
308:
303:
298:
293:
288:
283:
278:
273:
259:
152:
103:microprocessors
84:General-purpose
17:
12:
11:
5:
1305:
1303:
1295:
1294:
1289:
1284:
1274:
1273:
1270:
1269:
1268:from Bitsavers
1261:
1260:External links
1258:
1255:
1254:
1240:
1220:
1201:
1181:
1161:
1141:
1121:
1101:
1089:
1077:
1065:
1045:
1028:
1006:
984:(2017-06-22).
973:
949:
924:
923:
921:
918:
915:
914:
900:
899:
897:
894:
893:
892:
889:
882:
880:
877:
870:
868:
865:
858:
856:
853:
846:
844:
838:
837:
832:
828:
827:
824:
820:
819:
816:
812:
811:
801:
797:
796:
793:
789:
788:
785:
781:
780:
777:
771:
770:
767:
763:
762:
759:
755:
754:
751:
747:
746:
743:
739:
738:
735:
731:
730:
727:
720:
717:
676:
673:
665:S100-bus cards
625:
622:
611:shift register
547:
546:Implementation
544:
534:
517:
469:
466:
449:; e.g. when a
421:
420:
417:
416:
413:
410:
407:
404:
399:
394:
389:
384:
381:
377:
376:
373:
370:
366:
365:
362:
359:
355:
354:
352:(bit position)
349:
346:
344:
341:
339:
336:
334:
331:
329:
326:
324:
321:
319:
316:
314:
311:
309:
306:
304:
301:
299:
296:
294:
291:
289:
286:
284:
281:
279:
276:
274:
271:
258:
255:
182:Fairchild 9440
151:
148:
140:Motorola 68000
90:
89:
86:
80:
79:
75:
74:
68:
67:
64:
58:
57:
54:
48:
47:
44:
40:
39:
36:
32:
31:
26:
15:
13:
10:
9:
6:
4:
3:
2:
1304:
1293:
1290:
1288:
1285:
1283:
1280:
1279:
1277:
1267:
1264:
1263:
1259:
1250:
1244:
1241:
1230:
1224:
1221:
1213:
1212:
1205:
1202:
1191:
1185:
1182:
1171:
1165:
1162:
1151:
1145:
1142:
1131:
1125:
1122:
1111:
1105:
1102:
1098:
1093:
1090:
1087:, p. 28.
1086:
1081:
1078:
1075:, p. 31.
1074:
1069:
1066:
1055:
1049:
1046:
1038:
1032:
1029:
1021:
1020:
1013:
1011:
1007:
995:
991:
990:IEEE Spectrum
987:
983:
977:
974:
960:
953:
950:
942:
941:
934:
932:
930:
926:
919:
911:
905:
902:
895:
886:
881:
874:
869:
862:
857:
850:
845:
842:
833:
830:
829:
825:
822:
821:
817:
814:
813:
810:
806:
802:
799:
798:
794:
791:
790:
786:
783:
782:
778:
773:
772:
768:
765:
764:
760:
757:
756:
752:
749:
748:
744:
741:
740:
736:
733:
732:
728:
725:
724:
718:
716:
712:
708:
706:
697:
693:
691:
687:
683:
674:
672:
670:
666:
662:
657:
653:
651:
648:
643:
635:
630:
623:
621:
619:
618:memory-mapped
614:
612:
607:
605:
599:
597:
592:
590:
585:
581:
577:
573:
568:
564:
557:
552:
545:
543:
541:
533:
529:
526:
522:
516:
513:
509:
505:
500:
496:
492:
489:
485:
481:
479:
475:
467:
465:
461:
459:
454:
452:
448:
444:
440:
436:
432:
428:
414:
405:
403:
400:
398:
395:
393:
390:
388:
385:
382:
379:
378:
374:
367:
363:
356:
353:
350:
345:
340:
335:
330:
325:
320:
315:
310:
305:
300:
295:
290:
285:
280:
275:
270:
269:
266:
265:
256:
254:
252:
248:
243:
241:
237:
233:
228:
224:
222:
218:
214:
208:
206:
202:
199:
195:
191:
187:
183:
179:
175:
174:Intersil 6100
171:
168:
161:
156:
149:
147:
145:
141:
137:
132:
128:
126:
122:
117:
115:
112:
108:
104:
101:
97:
87:
85:
81:
76:
73:
69:
65:
63:
59:
55:
53:
49:
45:
41:
37:
33:
30:
27:
23:
1248:
1243:
1232:. Retrieved
1223:
1210:
1204:
1193:. Retrieved
1184:
1173:. Retrieved
1164:
1153:. Retrieved
1144:
1133:. Retrieved
1124:
1113:. Retrieved
1104:
1099:, p. 6.
1092:
1080:
1068:
1057:. Retrieved
1048:
1031:
1018:
998:. Retrieved
994:the original
989:
976:
965:. Retrieved
952:
939:
904:
729:Description
713:
709:
702:
689:
678:
658:
654:
639:
624:Applications
615:
608:
603:
600:
593:
569:
565:
561:
537:
530:
527:
523:
520:
501:
497:
493:
490:
486:
482:
471:
462:
455:
424:
351:
257:Architecture
244:
229:
225:
209:
190:Data General
186:Data General
170:minicomputer
164:
133:
129:
118:
114:minicomputer
95:
93:
809:Geneve 9640
686:Geneve 9640
680:use in the
661:John Walker
578:and 16-bit
576:address bus
217:main memory
119:Its 64-pin
1276:Categories
1234:2014-03-27
1195:2024-08-25
1175:2024-08-25
1155:2024-08-25
1135:2014-03-25
1115:2014-03-25
1059:2024-01-13
1000:2017-07-08
967:2022-10-26
920:References
843:Die photos
805:Tomy Tutor
682:Tomy Tutor
634:Tomy Tutor
584:Intel 8086
540:Intel 8086
512:breakpoint
474:orthogonal
458:big endian
451:subroutine
236:Intel 8088
136:Intel 8088
78:PC, WP, ST
62:Endianness
43:Introduced
908:Only the
890:TMS99105A
427:registers
412:Int Mask
72:Registers
1282:TI-99/4A
831:TMS99120
823:TMS99110
815:TMS99105
750:TI990/12
742:TI990/10
719:Variants
669:Autodesk
580:data bus
508:executes
478:operands
247:TI-99/4A
238:for the
25:Designer
878:TMS9995
866:TMS9981
854:TMS9900
800:TMS9995
792:TMS9989
784:TMS9985
776:TMS9981
774:TMS9980
766:TMS9940
758:TMS9900
734:TI990/9
705:990/10A
203:or DEC
150:History
96:TMS9900
20:TMS9900
726:Model
439:points
433:(PC),
383:A>
380:L>
251:TMS320
240:IBM PC
205:LSI-11
201:IMP-16
167:TI 990
111:TI-990
100:16-bit
52:Design
38:16-bit
1215:(PDF)
1040:(PDF)
1023:(PDF)
962:(PDF)
944:(PDF)
896:Notes
647:8-bit
604:/LOAD
178:PDP-8
650:DRAM
632:The
194:Nova
184:and
160:pins
94:The
56:CISC
46:1976
35:Bits
589:ALU
572:DIP
556:DIP
443:RAM
369:WP
358:PC
192:'s
121:DIP
66:Big
1278::
1009:^
988:.
928:^
429:—
409:0
406:X
372:0
361:0
109:'
1237:.
1198:.
1178:.
1158:.
1138:.
1118:.
1062:.
1003:.
970:.
558:)
402:P
397:O
392:C
387:=
347:5
342:4
337:3
332:2
327:1
322:0
317:9
312:8
307:7
302:6
297:5
292:4
287:3
282:2
277:1
272:0
Text is available under the Creative Commons Attribution-ShareAlike License. Additional terms may apply.
