258:
rules that modify existing features, insert new features, and check the entire design for process limitations such as layer density. A completed layout consists not only of the geometric representation of the design, but also data that provides support for the manufacture of the design. While design rule checks do not validate that the design will operate correctly, they are constructed to verify that the structure meets the process constraints for a given design type and process technology.
192:
36:
285:
Most design companies require DRC to run in less than a day to achieve reasonable cycle times since the DRC will likely be run several times prior to design completion. With today's processing power, full-chip DRC's may run in much shorter times as quick as one hour depending on the chip complexity and size.
207:. Design rules are specific to a particular semiconductor manufacturing process. A design rule set specifies certain geometric and connectivity restrictions to ensure sufficient margins to account for variability in semiconductor manufacturing processes, so as to ensure that most of the parts work correctly.
284:
DRC is a very computationally intense task. Usually DRC checks will be run on each sub-section of the ASIC to minimize the number of errors that are detected at the top level. If run on a single CPU, customers may have to wait up to a week to get the result of a Design Rule check for modern designs.
265:
standard format and a list of rules specific to the semiconductor process chosen for fabrication. From these it produces a report of design rule violations that the designer may or may not choose to correct. Carefully "stretching" or waiving certain design rules is often used to increase performance
218:
rule specifies the minimum distance between two adjacent objects. These rules will exist for each layer of semiconductor manufacturing process, with the lowest layers having the smallest rules (typically 100 nm as of 2007) and the highest metal layers having larger rules (perhaps 400 nm as
257:
The main objective of design rule checking (DRC) is to achieve a high overall yield and reliability for the design. If design rules are violated the design may not be functional. To meet this goal of improving die yields, DRC has evolved from simple measurement and
Boolean checks, to more involved
237:
are complex rules that check ratios of areas of every layer of a net for configurations that can result in problems when intermediate layers are etched. Many other such rules exist and are explained in detail in the documentation provided by the semiconductor manufacturer.
249:. This simplifies the migration of existing chip layouts to newer processes. Industrial rules are more highly optimized, and only approximate uniform scaling. Design rule sets have become increasingly more complex with each subsequent generation of semiconductor process.
152:(IC) designers to ensure their designs function properly, reliably, and can be produced with acceptable yield. Design rules for production are developed by process engineers based on the capability of their processes to realize design intent.
179:), and antenna checks. The importance of design rules and DRC is greatest for ICs, which have micro- or nano-scale geometries; for advanced processes, some fabs also insist upon the use of more
575:
551:
513:
226:
rule might specify that an object of one type, such as a contact or via, must be covered, with some additional margin, by a metal layer. A typical value as of 2007 might be about 10 nm.
621:
53:
605:
119:
100:
72:
57:
79:
626:
153:
133:
86:
46:
281:-based language. A set of rules for a particular process is referred to as a run-set, rule deck, or just a deck.
200:
68:
180:
449:
172:
400:
347:
357:
176:
165:
210:
The most basic design rules are shown in the diagram on the right. The first are single layer rules. A
145:
462:
93:
149:
601:
270:
222:
A two layer rule specifies a relationship that must exist between two layers. For example, an
537:
474:
273:
to describe the operations needed to be performed in DRC. For example, Mentor
Graphics uses
191:
156:
is used extensively to ensure that designers do not violate design rules; a process called
608:
A survey of the field, from which part of the above summary were derived, with permission.
375:
353:
340:
316:
234:
245:, so that all geometric tolerances in a design may be defined as integer multiples of
615:
168:
141:
35:
277:(SVRF) language in their DRC rules files and Magma Design Automation is using
241:
Academic design rules are often specified in terms of a scalable parameter,
17:
576:"Enhanced Design For Manufacturing Analysis using Python & TCL coding"
413:
204:
422:
361:
365:
262:
190:
214:
rule specifies the minimum width of any shape in the design. A
494:
Opensource 130nm CMOS PDK by Google and SkyWater tech. Foundry
278:
29:
598:
Electronic Design
Automation For Integrated Circuits Handbook
27:
Verification of geometric constraints on electronic designs
552:"Mguide Automation Using SVRF Coding and Bash Scripting"
229:
There are many other rule types not illustrated here. A
203:
that enable the designer to verify the correctness of a
261:
DRC software usually takes as input a layout in the
199:
Design rules are a series of parameters provided by
195:
The basic DRC checks - width, spacing, and enclosure
60:. Unsourced material may be challenged and removed.
266:and component density at the expense of yield.
514:"Antenna Effect Simulation & Application"
489:Microwind -- An educational layout CAD system
8:
307:Metal fill density (for processes using CMP)
288:Some example of DRC's in IC design include:
120:Learn how and when to remove this message
298:Minimum channel length of the transistor
171:on the design, which also involves LVS (
505:
140:is a geometric constraint imposed on
7:
600:, by Lavagno, Martin, and Scheffer,
233:rule is just what the name implies.
58:adding citations to reliable sources
481:Alliance -- A Free VLSI/CAD System
25:
275:Standard Verification Rule Format
34:
622:Electronic circuit verification
538:"Design Rule Complexity Rising"
269:DRC products define rules in a
45:needs additional citations for
164:). DRC is a major step during
1:
154:Electronic design automation
134:electronic design automation
485:Opencircuitdesign software:
463:Electric VLSI Design System
201:semiconductor manufacturers
175:) checks, XOR checks, ERC (
643:
436:-now SmartDRC by Silvaco
292:Active to active spacing
450:Magma Design Automation
428:HyperLynx DRC Free/Gold
173:layout versus schematic
401:Cadence Design Systems
348:Advanced Design System
327:Major products in the
304:Metal to metal spacing
196:
69:"Design rule checking"
358:Keysight Technologies
194:
177:electrical rule check
166:physical verification
295:Well to well spacing
158:design rule checking
146:semiconductor device
54:improve this article
627:Integrated circuits
301:Minimum metal width
580:scholar.google.com
556:scholar.google.com
518:scholar.google.com
430:by Mentor Graphics
197:
183:to improve yield.
150:integrated circuit
313:ESD and I/O rules
130:
129:
122:
104:
16:(Redirected from
634:
590:
589:
587:
586:
572:
566:
565:
563:
562:
548:
542:
541:
540:. 19 April 2018.
534:
528:
527:
525:
524:
510:
181:restricted rules
125:
118:
114:
111:
105:
103:
62:
38:
30:
21:
642:
641:
637:
636:
635:
633:
632:
631:
612:
611:
594:
593:
584:
582:
574:
573:
569:
560:
558:
550:
549:
545:
536:
535:
531:
522:
520:
512:
511:
507:
502:
458:
376:Mentor Graphics
354:PathWave Design
341:Altium Designer
325:
255:
189:
126:
115:
109:
106:
63:
61:
51:
39:
28:
23:
22:
15:
12:
11:
5:
640:
638:
630:
629:
624:
614:
613:
610:
609:
592:
591:
567:
543:
529:
504:
503:
501:
498:
497:
496:
491:
486:
483:
478:
471:
466:
457:
454:
453:
452:
443:
437:
431:
425:
416:
403:
378:
369:
344:
324:
321:
320:
319:
317:Antenna effect
314:
311:
308:
305:
302:
299:
296:
293:
254:
251:
188:
185:
128:
127:
42:
40:
33:
26:
24:
14:
13:
10:
9:
6:
4:
3:
2:
639:
628:
625:
623:
620:
619:
617:
607:
606:0-8493-3096-3
603:
599:
596:
595:
581:
577:
571:
568:
557:
553:
547:
544:
539:
533:
530:
519:
515:
509:
506:
499:
495:
492:
490:
487:
484:
482:
479:
477:
476:
472:
470:
467:
465:
464:
460:
459:
456:Free software
455:
451:
447:
444:
441:
438:
435:
432:
429:
426:
424:
420:
417:
415:
411:
407:
404:
402:
398:
394:
390:
386:
382:
379:
377:
373:
370:
368:EDA division)
367:
363:
359:
355:
351:
349:
345:
343:
342:
338:
337:
336:
334:
330:
322:
318:
315:
312:
309:
306:
303:
300:
297:
294:
291:
290:
289:
286:
282:
280:
276:
272:
267:
264:
259:
252:
250:
248:
244:
239:
236:
235:Antenna rules
232:
227:
225:
220:
217:
213:
208:
206:
202:
193:
186:
184:
182:
178:
174:
170:
167:
163:
159:
155:
151:
147:
143:
142:circuit board
139:
135:
124:
121:
113:
102:
99:
95:
92:
88:
85:
81:
78:
74:
71: –
70:
66:
65:Find sources:
59:
55:
49:
48:
43:This article
41:
37:
32:
31:
19:
597:
583:. Retrieved
579:
570:
559:. Retrieved
555:
546:
532:
521:. Retrieved
517:
508:
493:
488:
480:
473:
468:
461:
445:
439:
433:
427:
418:
410:IC Validator
409:
405:
396:
392:
388:
384:
380:
371:
346:
339:
332:
328:
326:
310:Poly density
287:
283:
274:
268:
260:
256:
246:
242:
240:
231:minimum area
230:
228:
223:
221:
215:
211:
209:
198:
187:Design rules
161:
157:
137:
131:
116:
110:October 2022
107:
97:
90:
83:
76:
64:
52:Please help
47:verification
44:
360:Previously
350:Desktop DRC
138:design rule
18:Design rule
616:Categories
585:2024-02-26
561:2024-02-26
523:2024-02-26
500:References
442:by Silvaco
323:Commercial
219:of 2007).
80:newspapers
335:include:
224:enclosure
440:SmartDRC
434:PowerDRC
419:Guardian
414:Synopsys
406:Hercules
331:area of
271:language
253:Software
205:mask set
469:KLayout
423:Silvaco
397:Pegasus
385:DRACULA
372:Calibre
362:Agilent
216:spacing
169:signoff
94:scholar
604:
446:Quartz
389:Assura
148:, and
96:
89:
82:
75:
67:
475:Magic
366:EEsof
263:GDSII
212:width
101:JSTOR
87:books
602:ISBN
408:and
395:and
381:Diva
136:, a
73:news
448:by
421:by
412:by
399:by
393:PVS
374:by
364:'s
352:by
333:EDA
329:DRC
279:Tcl
162:DRC
132:In
56:by
618::
578:.
554:.
516:.
391:,
387:,
383:,
144:,
588:.
564:.
526:.
356:(
247:λ
243:λ
160:(
123:)
117:(
112:)
108:(
98:·
91:·
84:·
77:·
50:.
20:)
Text is available under the Creative Commons Attribution-ShareAlike License. Additional terms may apply.
