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The PPU is an in-order processor, but it has some unique traits which allow it to achieve some benefits of out-of-order execution without expensive re-ordering hardware. Upon reaching an L1 cache miss – it can execute past the cache miss, stopping only when an instruction is actually dependent on a
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for code execution are duplicated, as are the exception and interrupt-handling registers, and several essential arrays and queues. They can generate exceptions simultaneously, and perform branch prediction on their individual branch histories. The execution engine and caches are not duplicated
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instruction set), can perform a theoretical 12 floating-point operations per cycle, as its floating-point unit can do floating-point multiply-adds, and come no smaller than 64-bits. That gives 3.2 billion clock cycles × 12 = 38.4 billion floating-point operations/second.
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load. It can send up to 8 load instructions to the L2 cache out-of-order. It has an instruction delay pipe – a side path that allows it to execute instructions that would normally cause
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The PPE has a 23-stage general pipeline with an additional 11 stages possible for microcode and an additional 4 stages possible for branch prediction.
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processor to be able to make single cycle double precision floating point operations, tailored for high performance computing in supercomputers.
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which is a version of the Cell BE with enhanced FPU and memory subsystem. It was only manufactured as a single 65 nm version.
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1002:. The instruction delay pipeline is used for the Out-Of-Order Load/Stores: cache misses are put there while it moves on.
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gaming console. It uses the PPE and comes in three versions, a 90 nm, a 65 nm and a 45 nm part.
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which is used in a three-core configuration and a unified 1 MB L2 cache inside
Microsoft's
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803:) and a 512 KB L2 cache. In most instances the PPU is used in a PPE. The PPU is a
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The PPU is used as a main CPU core in three different processor designs:
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837:, but has also found applications in high performance computing in
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Chen, Thomas; Raghavan, Ram; Dale, Jason; Iwata, Eiji.
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and is not entirely compatible with regular AltiVec.
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56:. Unsourced material may be challenged and removed.
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1096:Practical Computing on the Cell Broadband Engine
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929:Compatible with 64-bit PowerPC ISA v.2.02 (
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116:Learn how and when to remove this message
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1065:in the Xbox 360 is enhanced with 128
856:(Cell BE) which is used primarily in
147:NXP (formerly Freescale and Motorola)
7:
1091:"The Power Processing Element (PPE)"
54:adding citations to reliable sources
998:without holding up the rest of the
1089:Koranne, Sandeep (July 15, 2009).
14:
977:Vector Media Extension Unit (VMX)
30:
1101:Springer Science+Business Media
649:Architecture and classification
41:needs additional citations for
1328:Initiative for a Common Engine
1220:Synergistic Processing Element
962:Fixed Point Integer Unit (FXU)
907:3.2 GHz typical clockrate
16:In microprocessor architecture
1:
1282:Toshiba Qosmio F50, G50, G55
628:2.8 GHz to 3.2 GHz
1420:Simultaneous multithreading
1244:Vector Multimedia Extension
1109:10.1007/978-1-4419-0308-2_2
1054:The PPU is enhanced in the
841:such as the record setting
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904:64-bit, dual-threaded core
738:Products, models, variants
65:"Power Processing Element"
18:
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1042:floating-point unit, and
972:Floating-Point Unit (FPU)
967:Load and Store Unit (LSU)
922:512 KB unified L2 cache,
826:for use primarily in the
1379:STI Center of Competence
1232:Power Processing Element
1005:
789:Power Processing Element
673:90 nm to 45 nm
544:Power Processing Element
154:PowerPC e series (2006)
1400:Heterogeneous computing
1031:Floating-point capacity
700:Physical specifications
989:Out-of-order execution
287:PowerPC series (1992)
1022:simultaneously. The
924:8-way set associative
854:Cell Broadband Engine
797:Power Processing Unit
21:Power processing unit
1456:PowerPC architecture
1446:Cell BE architecture
1343:Software development
1183:Cell BE architecture
1061:The VMX unit in the
1046:VMX unit (using the
912:L1 instruction cache
689:Instruction set
669:Technology node
454:OpenPOWER Foundation
50:improve this article
1451:IBM microprocessors
926:in the PPE variant.
886:with an integrated
598:Common manufacturer
549:General information
545:
1287:IBM BladeCenter QS
1265:Sony PlayStation 3
1138:IBM DeveloperWorks
1103:. pp. 17–34.
1006:The PPE's pipeline
888:graphics processor
507:historic in italic
335:RAD series (1997)
191:Qor series (2008)
1461:Xbox 360 hardware
1433:
1432:
1410:Scratchpad memory
1118:978-1-4419-0307-5
1018:The PPU runs two
957:Branch Unit (BRU)
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679:Microarchitecture
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503:Cancelled in gray
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1425:Vector processor
1297:Namco System 357
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1140:. Archived from
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1144:on 2015-12-08.
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1024:main registers
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839:supercomputers
817:microprocessor
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1056:PowerXCell 8i
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869:PowerXCell 8i
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808:dual-threaded
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446:Related links
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67: –
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61:Find sources:
55:
51:
45:
44:
39:This article
37:
33:
28:
27:
22:
1374:Ken Kutaragi
1323:Folding@home
1231:
1213:Architecture
1142:the original
1137:
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822:designed by
814:PowerPC 2.02
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694:PowerPC 2.02
562:Discontinued
506:
459:AIM alliance
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374:IBM/Nintendo
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48:Please help
43:verification
40:
1359:David Bader
1338:PhyreEngine
1260:Fabrication
1225:SpursEngine
935:PowerPC 970
654:Application
614:Performance
588:Designed by
570:Marketed by
1440:Categories
1073:References
624:clock rate
421:PWRficient
106:April 2020
76:newspapers
1405:Power ISA
1395:Gameframe
1067:registers
776:Successor
729:, in the
582:Microsoft
474:Power.org
469:Blue Gene
140:Power ISA
1311:Software
1275:clusters
1000:pipeline
983:In-order
880:Xbox 360
835:Xbox 360
811:in-order
733:variant.
554:Launched
397:Espresso
390:Broadway
1333:OtherOS
1199:Toshiba
1048:AltiVec
1044:128-bit
941:AltiVec
771:History
750:Cell BE
743:Variant
565:Present
494:AltiVec
351:RAD5500
340:RAD6000
324:(2010)
279:Power10
200:Qorivva
136:PowerPC
90:scholar
1352:People
1318:Apulet
1270:models
1115:
1037:64-bit
931:POWER4
916:32 KB
910:32 KB
805:64-bit
780:IBM A2
367:(1996)
365:series
346:RAD750
274:POWER9
269:POWER8
264:POWER7
259:POWER6
253:POWER5
246:POWER4
239:POWER3
232:POWER2
225:POWER1
138:, and
92:
85:
78:
71:
63:
1237:Xenon
890:from
884:XCGPU
758:XCGPU
731:XCGPU
727:Xenos
706:Cores
640:cache
633:Cache
619:Max.
431:Xenon
415:Titan
406:Other
383:Gekko
218:Power
195:QorIQ
183:e6500
178:e5500
132:POWER
97:JSTOR
83:books
1415:SIMD
1388:Misc
1302:Zego
1194:Sony
1113:ISBN
1063:XCPU
1035:Its
944:SIMD
933:and
876:XCPU
874:The
867:The
858:Sony
852:The
833:and
820:core
787:The
754:XCPU
722:GPUs
578:Sony
557:2005
489:CHRP
484:PReP
479:PAPR
464:RISC
437:X704
426:Cell
363:RS64
309:74xx
173:e600
168:e500
163:e300
158:e200
69:news
1204:IBM
1105:doi
892:ATI
860:'s
824:IBM
801:PPU
793:PPE
683:PPU
662:HPC
638:L1
621:CPU
605:IBM
592:IBM
574:IBM
330:A2O
327:A2I
316:970
303:7xx
298:4xx
292:6xx
210:IBM
52:by
1442::
1136:.
1111:.
1099:.
1093:.
1081:^
845:.
760:,
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322:A2
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799:(
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113:(
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104:(
94:·
87:·
80:·
73:·
46:.
23:.
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