723:
317:
Once sizes have been chosen, the logical effort of the output of the gate is the sum of the widths of all transistors whose source or drain is in contact with the output node. The logical effort of each input to the gate is the sum of the widths of all transistors whose gate is in contact with that
313:
The drive at a node is equal to the sum of the drives of all transistors which are enabled and whose source or drain is in contact with the node in question. A PMOS transistor is enabled when its gate voltage is 0. An NMOS transistor is enabled when its gate voltage is 1.
207:, which is the ratio of the input capacitance of a given gate to that of an inverter capable of delivering the same output current (and hence is a constant for a particular class of gate and can be described as capturing the intrinsic properties of the gate), and an
296:
CMOS inverters along the critical path are typically designed with a gamma equal to 2. In other words, the pFET of the inverter is designed with twice the width (and therefore twice the capacitance) as the nFET of the inverter, in order to get roughly the same
215:, which is the ratio of the input capacitance of the load to that of the gate. Note that "logical effort" does not take the load into account and hence we have the term "electrical effort" which takes the load into account. The stage effort is then simply:
641:
It can be shown that in multistage logic networks, the minimum possible delay along a particular path can be achieved by designing the circuit such that the stage efforts are equal. For a given combination of gates and a known load,
575:
835:= 4/3 because a NAND gate with input capacitance 4 can drive the same current as the inverter can, with input capacitance 3. Similarly, the logical effort of a two-input NOR gate can be found to be
47:
circuit. Used properly, it can aid in selection of gates for a given function (including the number of stages necessary) and sizing gates to achieve the minimum delay possible for a circuit.
63:, the delay of an inverter driving an identical inverter without any additional capacitance added by interconnects or other loads; the unitless number associated with this is known as the
1398:
1308:
125:
1213:
821:
1054:
1174:
1146:
1118:
1090:
1018:
990:
962:
934:
399:
700:
286:
620:
194:
451:
245:
304:
Choose sizes for all transistors such that the output drive of the gate is equal to the output drive of an inverter built from a size-2 PMOS and a size-1 NMOS.
329:
A major advantage of the method of logical effort is that it can quickly be extended to circuits composed of multiple stages. The total normalized path delay
71:
delay—the delay of one inverter driving 4 identical inverters). The absolute delay is then simply defined as the product of the normalized delay of the gate,
1421:
307:
The output drive of a gate is equal to the minimum – over all possible combinations of inputs – of the output drive of the gate for that input.
1506:
464:, needs to be taken into account; it is the ratio of total capacitance being driven by the gate to the capacitance on the path of interest:
1223:
Therefore, the normalised delay of a two-input NAND gate driving an identical copy of itself (such that the electrical effort is 1) is
1485:
470:
1530:
321:
The logical effort of the entire gate is the ratio of its output logical effort to the sum of its input logical efforts.
1525:
1475:
250:
Combining these equations yields a basic equation that models the normalized delay through a single logic gate:
1319:
1229:
85:
1496:
151:(which is an intrinsic delay of the gate and can be found by considering the gate driving no load), and
1425:
1180:
758:
1024:
141:
The normalized delay in a logic gate can be expressed as a summation of two primary terms: normalized
1452:
1152:
143:
1124:
1096:
1068:
996:
968:
940:
912:
658:
to be fixed; hence the individual gates should be sized such that the individual stage efforts are
354:
153:
664:
1502:
1481:
587:
which is the product of the individual stage branching efforts; the total path effort is then
40:
421:
For paths where each gate drives only one additional gate (i.e. the next gate in the path),
256:
734:
of an inverter is 1. If the inverter drives an equivalent inverter, the electrical effort
593:
167:
17:
839:= 5/3. Due to the lower logical effort, NAND gates are typically preferred to NOR gates.
427:
221:
32:
301:
as nFET resistance, in order to get roughly equal pull-up current and pull-down current.
1456:
1220:
The normalised parasitic delay of NAND and NOR gates is equal to the number of inputs.
752:
Therefore, the total normalised delay of an inverter driving an equivalent inverter is
310:
The output drive of a gate for a given input is equal to the drive at its output node.
1519:
138:
is about 20 ps. In modern 45 nm processes the delay is approximately 4 to 5 ps.
746:
298:
68:
36:
633:= 1 and causing the formula to reduce to the earlier non-branching version.
722:
411:(the product of the individual logical efforts of the gates), and the
161:(which is dependent on the load as described below). Consequently,
1474:
Sutherland, Ivan E.; Sproull, Robert F.; Harris, David F. (1999).
721:
831:
The logical effort of a two-input NAND gate is calculated to be
44:
846:
Logical effort for inputs of static CMOS gates, with gamma = 2
745:
of an inverter is also 1 (this can be found by considering the
570:{\displaystyle b={\frac {C_{onpath}+C_{offpath}}{C_{onpath}}}}
418:(the ratio of the load of the path to its input capacitance).
292:
Procedure for calculating the logical effort of a single stage
1498:
CMOS VLSI Design: A Circuits and
Systems Perspective, 3rd Ed
1449:
An
Optimal CMOS Structure for the Design of a Cell Library
1424:. University of South Carolina. p. 23. Archived from
67:. (Some authors prefer define the basic delay unit as the
629:= 1 for gates driving only one additional gate, fixing
348:(which is the sum of the individual parasitic delays):
1322:
1232:
1183:
1155:
1127:
1099:
1071:
1027:
999:
971:
943:
915:
761:
667:
596:
473:
430:
357:
259:
224:
170:
88:
842:
For larger gates, the logical effort is as follows:
199:The stage effort is divided into two components: a
55:Delay is expressed in terms of a basic delay unit,
1392:
1302:
1207:
1168:
1140:
1112:
1084:
1048:
1012:
984:
956:
928:
815:
694:
614:
569:
445:
393:
280:
239:
188:
119:
456:However, for circuits that branch, an additional
39:in 1991, is a straightforward technique used to
404:The path effort is expressed in terms of the
8:
1477:Logical Effort: Designing Fast CMOS Circuits
1313:and for a two-input NOR gate, the delay is
1495:Weste, Neil H. E.; Harris, David (2011).
1382:
1350:
1321:
1292:
1260:
1231:
1184:
1182:
1156:
1154:
1128:
1126:
1100:
1098:
1072:
1070:
1028:
1026:
1000:
998:
972:
970:
944:
942:
916:
914:
760:
682:
678:
666:
595:
544:
515:
487:
480:
472:
429:
375:
371:
356:
258:
223:
169:
93:
87:
709:is the number of stages in the circuit.
333:can be expressed in terms of an overall
1447:Dielen, M.; Theeuwen, J. F. M. (1987).
1412:
1393:{\displaystyle d=gh+p=(5/3)(1)+2=11/3}
1303:{\displaystyle d=gh+p=(4/3)(1)+2=10/3}
134:is about 50 ps. For a 250-nm process,
7:
120:{\displaystyle d_{abs}=d\cdot \tau }
51:Derivation of delay in a logic gate
1422:"Fundamentals of VLSI Chip Design"
730:By definition, the logical effort
25:
1208:{\displaystyle {\frac {2n+1}{3}}}
844:
816:{\displaystyle d=gh+p=(1)(1)+1=2}
1049:{\displaystyle {\frac {n+2}{3}}}
1169:{\displaystyle {\frac {11}{3}}}
1367:
1361:
1358:
1344:
1277:
1271:
1268:
1254:
1141:{\displaystyle {\frac {9}{3}}}
1113:{\displaystyle {\frac {7}{3}}}
1085:{\displaystyle {\frac {5}{3}}}
1013:{\displaystyle {\frac {7}{3}}}
985:{\displaystyle {\frac {6}{3}}}
957:{\displaystyle {\frac {5}{3}}}
929:{\displaystyle {\frac {4}{3}}}
798:
792:
789:
783:
1:
394:{\displaystyle D=NF^{1/N}+P}
130:In a typical 600-nm process
827:Delay in NAND and NOR gates
18:Principle of logical effort
1547:
1501:. Pearson/Addison-Wesley.
852:
695:{\displaystyle f=F^{1/N}}
325:Multistage logic networks
749:model of the inverter).
726:A CMOS inverter circuit.
1394:
1304:
1209:
1170:
1142:
1114:
1086:
1050:
1014:
986:
958:
930:
817:
727:
696:
654:are all fixed causing
616:
571:
447:
413:path electrical effort
395:
282:
281:{\displaystyle d=gh+p}
241:
190:
121:
1395:
1305:
1210:
1171:
1143:
1115:
1087:
1051:
1015:
987:
959:
931:
818:
725:
697:
617:
615:{\displaystyle F=GHB}
582:path branching effort
572:
448:
396:
283:
242:
191:
189:{\displaystyle d=f+p}
122:
1531:Electronics concepts
1320:
1230:
1181:
1153:
1125:
1097:
1069:
1025:
997:
969:
941:
913:
759:
741:The parasitic delay
718:Delay in an inverter
665:
625:It can be seen that
594:
471:
446:{\displaystyle F=GH}
428:
355:
343:path parasitic delay
257:
240:{\displaystyle f=gh}
222:
168:
86:
1526:Digital electronics
1480:. Morgan Kaufmann.
1457:1987cmos.rept.....D
847:
406:path logical effort
31:, a term coined by
1428:on 8 November 2011
1390:
1300:
1205:
1166:
1138:
1110:
1082:
1046:
1010:
982:
954:
926:
845:
813:
728:
692:
612:
567:
443:
391:
278:
237:
186:
117:
1508:978-0-321-54774-3
1218:
1217:
1203:
1164:
1136:
1108:
1080:
1044:
1008:
980:
952:
924:
853:Number of Inputs
565:
209:electrical effort
16:(Redirected from
1538:
1512:
1491:
1461:
1460:
1444:
1438:
1437:
1435:
1433:
1420:Bakos, Jason D.
1417:
1399:
1397:
1396:
1391:
1386:
1354:
1309:
1307:
1306:
1301:
1296:
1264:
1214:
1212:
1211:
1206:
1204:
1199:
1185:
1175:
1173:
1172:
1167:
1165:
1157:
1147:
1145:
1144:
1139:
1137:
1129:
1119:
1117:
1116:
1111:
1109:
1101:
1091:
1089:
1088:
1083:
1081:
1073:
1055:
1053:
1052:
1047:
1045:
1040:
1029:
1019:
1017:
1016:
1011:
1009:
1001:
991:
989:
988:
983:
981:
973:
963:
961:
960:
955:
953:
945:
935:
933:
932:
927:
925:
917:
848:
822:
820:
819:
814:
701:
699:
698:
693:
691:
690:
686:
621:
619:
618:
613:
576:
574:
573:
568:
566:
564:
563:
539:
538:
537:
507:
506:
481:
458:branching effort
452:
450:
449:
444:
400:
398:
397:
392:
384:
383:
379:
287:
285:
284:
279:
246:
244:
243:
238:
195:
193:
192:
187:
126:
124:
123:
118:
104:
103:
65:normalized delay
21:
1546:
1545:
1541:
1540:
1539:
1537:
1536:
1535:
1516:
1515:
1509:
1494:
1488:
1473:
1470:
1468:Further reading
1465:
1464:
1446:
1445:
1441:
1431:
1429:
1419:
1418:
1414:
1409:
1403:
1318:
1317:
1228:
1227:
1186:
1179:
1178:
1151:
1150:
1123:
1122:
1095:
1094:
1067:
1066:
1030:
1023:
1022:
995:
994:
967:
966:
939:
938:
911:
910:
829:
757:
756:
720:
715:
674:
663:
662:
639:
592:
591:
540:
511:
483:
482:
469:
468:
426:
425:
367:
353:
352:
327:
299:pFET resistance
294:
255:
254:
220:
219:
166:
165:
144:parasitic delay
89:
84:
83:
53:
33:Ivan Sutherland
23:
22:
15:
12:
11:
5:
1544:
1542:
1534:
1533:
1528:
1518:
1517:
1514:
1513:
1507:
1492:
1486:
1469:
1466:
1463:
1462:
1451:. p. 11.
1439:
1411:
1410:
1408:
1405:
1401:
1400:
1389:
1385:
1381:
1378:
1375:
1372:
1369:
1366:
1363:
1360:
1357:
1353:
1349:
1346:
1343:
1340:
1337:
1334:
1331:
1328:
1325:
1311:
1310:
1299:
1295:
1291:
1288:
1285:
1282:
1279:
1276:
1273:
1270:
1267:
1263:
1259:
1256:
1253:
1250:
1247:
1244:
1241:
1238:
1235:
1216:
1215:
1202:
1198:
1195:
1192:
1189:
1176:
1163:
1160:
1148:
1135:
1132:
1120:
1107:
1104:
1092:
1079:
1076:
1064:
1061:
1057:
1056:
1043:
1039:
1036:
1033:
1020:
1007:
1004:
992:
979:
976:
964:
951:
948:
936:
923:
920:
908:
905:
901:
900:
897:
894:
891:
888:
885:
882:
878:
877:
874:
871:
868:
865:
862:
859:
855:
854:
851:
828:
825:
824:
823:
812:
809:
806:
803:
800:
797:
794:
791:
788:
785:
782:
779:
776:
773:
770:
767:
764:
719:
716:
714:
711:
703:
702:
689:
685:
681:
677:
673:
670:
638:
635:
623:
622:
611:
608:
605:
602:
599:
580:This yields a
578:
577:
562:
559:
556:
553:
550:
547:
543:
536:
533:
530:
527:
524:
521:
518:
514:
510:
505:
502:
499:
496:
493:
490:
486:
479:
476:
454:
453:
442:
439:
436:
433:
402:
401:
390:
387:
382:
378:
374:
370:
366:
363:
360:
326:
323:
293:
290:
289:
288:
277:
274:
271:
268:
265:
262:
248:
247:
236:
233:
230:
227:
201:logical effort
197:
196:
185:
182:
179:
176:
173:
128:
127:
116:
113:
110:
107:
102:
99:
96:
92:
52:
49:
41:estimate delay
29:logical effort
27:The method of
24:
14:
13:
10:
9:
6:
4:
3:
2:
1543:
1532:
1529:
1527:
1524:
1523:
1521:
1510:
1504:
1500:
1499:
1493:
1489:
1487:1-55860-557-6
1483:
1479:
1478:
1472:
1471:
1467:
1458:
1454:
1450:
1443:
1440:
1427:
1423:
1416:
1413:
1406:
1404:
1387:
1383:
1379:
1376:
1373:
1370:
1364:
1355:
1351:
1347:
1341:
1338:
1335:
1332:
1329:
1326:
1323:
1316:
1315:
1314:
1297:
1293:
1289:
1286:
1283:
1280:
1274:
1265:
1261:
1257:
1251:
1248:
1245:
1242:
1239:
1236:
1233:
1226:
1225:
1224:
1221:
1200:
1196:
1193:
1190:
1187:
1177:
1161:
1158:
1149:
1133:
1130:
1121:
1105:
1102:
1093:
1077:
1074:
1065:
1062:
1059:
1058:
1041:
1037:
1034:
1031:
1021:
1005:
1002:
993:
977:
974:
965:
949:
946:
937:
921:
918:
909:
906:
903:
902:
898:
895:
892:
889:
886:
883:
880:
879:
875:
872:
869:
866:
863:
860:
857:
856:
850:
849:
843:
840:
838:
834:
826:
810:
807:
804:
801:
795:
786:
780:
777:
774:
771:
768:
765:
762:
755:
754:
753:
750:
748:
744:
739:
737:
733:
724:
717:
712:
710:
708:
687:
683:
679:
675:
671:
668:
661:
660:
659:
657:
653:
649:
645:
637:Minimum delay
636:
634:
632:
628:
609:
606:
603:
600:
597:
590:
589:
588:
586:
583:
560:
557:
554:
551:
548:
545:
541:
534:
531:
528:
525:
522:
519:
516:
512:
508:
503:
500:
497:
494:
491:
488:
484:
477:
474:
467:
466:
465:
463:
459:
440:
437:
434:
431:
424:
423:
422:
419:
417:
414:
410:
407:
388:
385:
380:
376:
372:
368:
364:
361:
358:
351:
350:
349:
347:
344:
340:
336:
332:
324:
322:
319:
315:
311:
308:
305:
302:
300:
291:
275:
272:
269:
266:
263:
260:
253:
252:
251:
234:
231:
228:
225:
218:
217:
216:
214:
210:
206:
202:
183:
180:
177:
174:
171:
164:
163:
162:
160:
156:
155:
150:
146:
145:
139:
137:
133:
114:
111:
108:
105:
100:
97:
94:
90:
82:
81:
80:
78:
74:
70:
66:
62:
58:
50:
48:
46:
42:
38:
34:
30:
19:
1497:
1476:
1448:
1442:
1430:. Retrieved
1426:the original
1415:
1402:
1312:
1222:
1219:
841:
836:
832:
830:
751:
747:Elmore delay
742:
740:
735:
731:
729:
706:
704:
655:
651:
647:
643:
640:
630:
626:
624:
584:
581:
579:
461:
457:
455:
420:
415:
412:
408:
405:
403:
345:
342:
338:
334:
330:
328:
320:
318:input node.
316:
312:
309:
306:
303:
295:
249:
212:
208:
204:
200:
198:
158:
154:stage effort
152:
148:
142:
140:
135:
131:
129:
76:
72:
64:
60:
56:
54:
28:
26:
738:is also 1.
335:path effort
69:fanout of 4
37:Bob Sproull
1520:Categories
1407:References
341:, and the
881:Inverter
858:Gate type
115:τ
112:⋅
713:Examples
1453:Bibcode
1432:8 March
1505:
1484:
705:where
650:, and
75:, and
904:NAND
43:in a
1503:ISBN
1482:ISBN
1434:2011
1063:N/A
1060:NOR
907:N/A
899:N/A
896:N/A
893:N/A
890:N/A
887:N/A
45:CMOS
35:and
61:3RC
1522::
1380:11
1290:10
1159:11
884:1
876:n
646:,
460:,
337:,
211:,
203:,
157:,
147:,
79::
59:=
1511:.
1490:.
1459:.
1455::
1436:.
1388:3
1384:/
1377:=
1374:2
1371:+
1368:)
1365:1
1362:(
1359:)
1356:3
1352:/
1348:5
1345:(
1342:=
1339:p
1336:+
1333:h
1330:g
1327:=
1324:d
1298:3
1294:/
1287:=
1284:2
1281:+
1278:)
1275:1
1272:(
1269:)
1266:3
1262:/
1258:4
1255:(
1252:=
1249:p
1246:+
1243:h
1240:g
1237:=
1234:d
1201:3
1197:1
1194:+
1191:n
1188:2
1162:3
1134:3
1131:9
1106:3
1103:7
1078:3
1075:5
1042:3
1038:2
1035:+
1032:n
1006:3
1003:7
978:3
975:6
950:3
947:5
922:3
919:4
873:5
870:4
867:3
864:2
861:1
837:g
833:g
811:2
808:=
805:1
802:+
799:)
796:1
793:(
790:)
787:1
784:(
781:=
778:p
775:+
772:h
769:g
766:=
763:d
743:p
736:h
732:g
707:N
688:N
684:/
680:1
676:F
672:=
669:f
656:F
652:H
648:G
644:B
631:B
627:b
610:B
607:H
604:G
601:=
598:F
585:B
561:h
558:t
555:a
552:p
549:n
546:o
542:C
535:h
532:t
529:a
526:p
523:f
520:f
517:o
513:C
509:+
504:h
501:t
498:a
495:p
492:n
489:o
485:C
478:=
475:b
462:b
441:H
438:G
435:=
432:F
416:H
409:G
389:P
386:+
381:N
377:/
373:1
369:F
365:N
362:=
359:D
346:P
339:F
331:D
276:p
273:+
270:h
267:g
264:=
261:d
235:h
232:g
229:=
226:f
213:h
205:g
184:p
181:+
178:f
175:=
172:d
159:f
149:p
136:τ
132:τ
109:d
106:=
101:s
98:b
95:a
91:d
77:τ
73:d
57:τ
20:)
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