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than more coarse-grained architectures due to more elements needing to be addressed and programmed. Therefore, more coarse-grained architectures gain from potential lower energy requirements, as less information is transferred and utilised. Intuitively, the slower the rate of reconfiguration the smaller the power consumption as the associated energy cost of reconfiguration are amortised over a longer period of time. Partial re-configuration aims to allow part of the device to be reprogrammed while another part is still performing active computation. Partial re-configuration allows smaller reconfigurable bit streams thus not wasting energy on transmitting redundant information in the bit stream. Compression of the bit stream is possible but careful analysis is to be carried out to ensure that the energy saved by using smaller bit streams is not outweighed by the computation needed to decompress the data.
708:(ALU), they will perform these computations more quickly and with more power efficiency than a set of interconnected smaller functional units; this is due to the connecting wires being shorter, resulting in less wire capacitance and hence faster and lower power designs. A potential undesirable consequence of having larger computational blocks is that when the size of operands may not match the algorithm an inefficient utilisation of resources can result. Often the type of applications to be run are known in advance allowing the logic, memory and routing resources to be tailored to enhance the performance of the device whilst still providing a certain level of flexibility for future adaptation. Examples of this are domain specific arrays aimed at gaining better performance in terms of power, area, throughput than their more generic finer grained
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the hardware. However, there is a penalty associated with this in terms of increased power, area and delay due to greater quantity of routing required per computation. Fine-grained architectures work at the bit-level manipulation level; whilst coarse grained processing elements (reconfigurable datapath unit, rDPU) are better optimised for standard data path applications. One of the drawbacks of coarse grained architectures are that they tend to lose some of their utilisation and performance if they need to perform smaller computations than their granularity provides, for example for a one bit add on a four bit wide functional unit would waste three bits. This problem can be solved by having a coarse grain array (
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were feasible due to the constant progress of silicon technology that let complex designs be implemented on one chip. Some of these massively parallel reconfigurable computers were built primarily for special subdomains such as molecular evolution, neural or image processing. The world's first commercial reconfigurable computer, the
Algotronix CHS2X4, was completed in 1991. It was not a commercial success, but was promising enough that
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bus to provide a coprocessor like arrangement for the reconfigurable array. However, there have also been implementations where the reconfigurable fabric is much closer to the processor, some are even implemented into the data path, utilising the processor registers. The job of the host processor is to perform the control functions, configure the logic, schedule data and to provide external interfacing.
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360:. A 2008 paper reported speed-up factors of more than 4 orders of magnitude and energy saving factors by up to almost 4 orders of magnitude. Some supercomputer firms offer heterogeneous processing blocks including FPGAs as accelerators. One research area is the twin-paradigm programming tool flow productivity obtained for such heterogeneous systems.
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underlying virtual hardware. This can be relaxed by the concept of threads, allowing different tasks to run concurrently on this virtual hardware to exploit task level parallelism. To allow different processes and threads to coordinate their work, communication and synchronization methods have to be provided by the OS.
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vendors, Xilinx and Altera are the island style layout, where blocks are arranged in an array with vertical and horizontal routing. A layout with inadequate routing may suffer from poor flexibility and resource utilisation, therefore providing limited performance. If too much interconnect is provided
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Often the reconfigurable array is used as a processing accelerator attached to a host processor. The level of coupling determines the type of data transfers, latency, power, throughput and overheads involved when utilising the reconfigurable logic. Some of the most intuitive designs use a peripheral
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Normally, reconfiguring an FPGA requires it to be held in reset while an external controller reloads a design onto it. Partial reconfiguration allows for critical parts of the design to continue operating while a controller either on the FPGA or off of it loads a partial design into a reconfigurable
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In the 1980s and 1990s there was a renaissance in this area of research with many proposed reconfigurable architectures developed in industry and academia, such as: Copacobana, Matrix, GARP, Elixent, NGEN, Polyp, MereGen, PACT XPP, Silicon Hive, Montium, Pleiades, Morphosys, and PiCoGA. Such designs
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The granularity of the reconfigurable logic is defined as the size of the smallest functional unit (configurable logic block, CLB) that is addressed by the mapping tools. High granularity, which can also be known as fine-grained, often implies a greater flexibility when implementing algorithms into
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One of the key challenges for reconfigurable computing is to enable higher design productivity and provide an easier way to use reconfigurable computing systems for users that are unfamiliar with the underlying concepts. One way of doing this is to provide standardization and abstraction, usually
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Configuration of these reconfigurable systems can happen at deployment time, between execution phases or during execution. In a typical reconfigurable system, a bit stream is used to program the device at deployment time. Fine grained systems by their own nature require greater configuration time
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Abstraction is a powerful mechanism to handle complex and different (hardware) tasks in a well-defined and common manner. One of the most elementary OS abstractions is a process. A process is a running application that has the perception (provided by the OS) that it is running on its own on the
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In addition to abstraction, resource management of the underlying hardware components is necessary because the virtual computers provided to the processes and threads by the operating system need to share available physical resources (processors, memory, and devices) spatially and temporarily.
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supports partial reconfiguration of their FPGA devices on 28 nm devices such as
Stratix V, and on the 20 nm Arria 10 devices. The Intel FPGA partial reconfiguration flow for Arria 10 is based on the hierarchical design methodology in the Quartus Prime Pro software where users create
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language to be compiled and executed on FPGA-based computers. The
Mitrion-C software language and Mitrion processor enable software developers to write and execute applications on FPGA-based computers in the same manner as with other computing technologies, such as graphical processing units
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Campi, F.; Toma, M.; Lodi, A.; Cappelli, A.; Canegallo, R.; Guerrieri, R., "A VLIW processor with reconfigurable instruction set for embedded applications", Solid-State
Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International, vol., no., pp. 250–491 vol. 1,
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Partial reconfiguration is not supported on all FPGAs. A special software flow with emphasis on modular design is required. Typically the design modules are built along well defined boundaries inside the FPGA that require the design to be specially mapped to the internal hardware.
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One of the major tasks of an operating system is to hide the hardware and present programs (and their programmers) with nice, clean, elegant, and consistent abstractions to work with instead. In other words, the two main tasks of an operating system are abstraction and
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As an emerging field, classifications of reconfigurable architectures are still being developed and refined as new architectures are developed; no unifying taxonomy has been suggested to date. However, several recurring parameters can be used to classify these systems.
115:'s paper proposed the concept of a computer made of a standard processor and an array of "reconfigurable" hardware. The main processor would control the behavior of the reconfigurable hardware. The latter would then be tailored to perform a specific task, such as
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J. M. Arnold and D. A. Buell, "VHDL programming on Splash 2," in More FPGAs, Will Moore and Wayne Luk, editors, Abingdon EE & CS Books, Oxford, England, 1994, pp. 182–191. (Proceedings, International
Workshop on Field-Programmable Logic, Oxford,
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physical partitions of the FPGA that can be reconfigured at runtime while the remainder of the design continues to operate. The
Quartus Prime Pro software also support hierarchical partial reconfiguration and simulation of partial reconfiguration.
289:) migration results in reported speed-up factors of up to more than four orders of magnitude, as well as a reduction in electricity consumption by up to almost four orders of magnitude—although the technological parameters of FPGAs are behind the
512:. It consists of reconfigurable chassis housing the user-programmable FPGA, hot swappable I/O modules, real-time controller for deterministic communication and processing, and graphical LabVIEW software for rapid RT and FPGA programming.
123:, as quickly as a dedicated piece of hardware. Once the task was done, the hardware could be adjusted to do some other task. This resulted in a hybrid computer structure combining the flexibility of software with the speed of hardware.
407:, can be designed modularly, by creating subcomponents and then higher-level components to instantiate them. In many cases it is useful to be able to swap out one or several of these subcomponents while the FPGA is still operating.
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T.J. Todman, G.A. Constantinides, S.J.E. Wilton, O. Mencer, W. Luk and P.Y.K. Cheung, "Reconfigurable
Computing: Architectures and Design Methods", IEEE Proceedings: Computer & Digital Techniques, Vol. 152, No. 2, March 2005,
438:- the device is not active during the reconfiguration process. While the partial data is sent into the FPGA, the rest of the device is stopped (in the shutdown mode) and brought up after the configuration is completed.
135:, FPGA) bought the technology and hired the Algotronix staff. Later machines enabled first demonstrations of scientific principles, such as the spontaneous spatial self-organisation of genetic coding with MereGen.
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or implement more novel architectures. Such projects are built with reconfigurable hardware (FPGAs), and some devices support emulation of multiple vintage computers using a single reconfigurable hardware
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J. M. Arnold, D. A. Buell, D. Hoang, D. V. Pryor, N. Shirazi, M. R. Thistle, "Splash 2 and its applications, "Proceedings, International
Conference on Computer Design, Cambridge, 1993, pp. 482–486.
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McCaskill, John S.; Chorongiewski, Harald; Mekelburg, Karsten; Tangen, Uwe; Gemm, Udo (1994-09-01). "NGEN — Configurable computer hardware to simulate long-time self-organization of biopolymers".
704:) are intended for the implementation for algorithms needing word-width data paths (rDPU). As their functional blocks are optimized for large computations and typically comprise word wide
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The increase of logic in an FPGA has enabled larger and more complex algorithms to be programmed into the FPGA. The attachment of such an FPGA to a modern CPU over a high speed bus, like
95:(ASICs) is the possibility to adapt the hardware during runtime by "loading" a new circuit on the reconfigurable fabric, thus providing new computational blocks without the need to
941:. Sipper, Moshe., Mange, Daniel, 1940-, Pérez-Uribe, Andrés., International Conference on Evolvable Systems (2nd : 1998 : Lausanne, Switzerland). Berlin: Springer. 1998.
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A common example for when partial reconfiguration would be useful is the case of a communication device. If the device is controlling multiple connections, some of which require
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has a center for high-performance reconfigurable computing (CHREC). In April 2011 the fourth Many-core and
Reconfigurable Supercomputing Conference was held in Europe.
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N. Voros, R. Nikolaos, A. Rosti, M. Hübner (editors): Dynamic System
Reconfiguration in Heterogeneous Platforms - The MORPHEUS Approach; Springer Verlag, 2009
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Evolvable systems : from biology to hardware : second International Conference, ICES 98, Lausanne, Switzerland, September 23-25, 1998: proceedings
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Esam El-Araby; Ivan Gonzalez; Tarek El-Ghazawi (January 2009). "Exploiting Partial Runtime Reconfiguration for High-Performance Reconfigurable Computing".
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A. Zomaya (editor): Handbook of Nature-Inspired and Innovative Computing: Integrating Classical Models with Emerging Technologies; Springer Verlag, 2006
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by about four orders of magnitude, and the clock frequency is substantially lower than that of microprocessors. This paradox is partly explained by the
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module. Partial reconfiguration also can be used to save space for multiple designs by only storing the partial designs that change between designs.
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A fully FPGA-based computer is the COPACOBANA, the Cost Optimized Codebreaker and Analyzer and its successor RIVYERA. A spin-off company
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combining some of the flexibility of software with the high performance of hardware by processing with flexible hardware platforms like
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of the COPACOBANA-Project of the Universities of Bochum and Kiel in Germany continues the development of fully FPGA-based computers.
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The flexibility in reconfigurable devices mainly comes from their routing interconnect. One style of interconnect made popular by
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is the ability to add custom computational blocks using FPGAs. On the other hand, the main difference from custom hardware, i.e.
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1130:(Munich, Germany). W. Nebel and A. Jerraya, Eds. Design, Automation, and Test in Europe. IEEE Press, Piscataway, NJ, 642–649.
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261:'s following classification scheme of computing paradigms (see "Table 1: Nick Tredennick's Paradigm Classification Scheme").
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systems to be produced where several computational devices can concurrently operate on different data, which is highly
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N. Tredennick: The Case for Reconfigurable Computing; Microprocessor Report, Vol. 10 No. 10, 5 August 1996, pp 25–27.
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Furthermore, by replicating an algorithm on an FPGA or the use of a multiplicity of FPGAs has enabled reconfigurable
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this requires more transistors than necessary and thus more silicon area, longer wires and more power consumption.
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Commercial high-performance reconfigurable computing systems are beginning to emerge with the announcement of
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Estrin, G (2002). "Reconfigurable computer origins: the UCLA fixed-plus-variable (F+V) structure computer".
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is well illustrated by the differences to other machine paradigms that were introduced earlier, as shown by
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Tarek El-Ghazawi; et al. (February 2008). "The promise of high-performance reconfigurable computing".
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Wanta, Damian; Smolik, Waldemar T.; Kryszyn, Jacek; Wróblewski, Przemysław; Midura, Mateusz (2022).
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Hauser, John R. and Wawrzynek, John, "Garp: A MIPS Processor with a Reconfigurable Coprocessor",
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that, according to him, represents a fundamental paradigm shift away from the more conventional
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With the advent of affordable FPGA boards, students' and hobbyists' projects seek to recreate
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From the functionality of the design, partial reconfiguration can be divided into two groups:
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The fundamental model of the reconfigurable computing machine paradigm, the data-stream-based
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J. Teich (editor) et al.: Reconfigurable Computing Systems. Special Topic Issue of Journal
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Estrin, G., "Organization of Computer Systems—The Fixed Plus Variable Structure Computer",
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Hartenstein, R. 2001. A decade of reconfigurable computing: a visionary retrospective. In
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Computer scientist Reiner Hartenstein describes reconfigurable computing in terms of an
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This heterogeneous systems technique is used in computing research and especially in
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1456:"Stratix V FPGAs: Ultimate Flexibility Through Partial and Dynamic Reconfiguration"
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Proceedings of the Conference on Design, Automation and Test in Europe (DATE 2001)
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Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines
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C. Bobda: Introduction to Reconfigurable Computing: Architectures; Springer, 2007
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D. A. Buell and Kenneth L. Pocek, "Custom computing machines: An introduction,"
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ReCoBus-Builder project for easily implementing complex reconfigurable systems
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Reconfigurable Computing: The Theory and Practice of FPGA-Based Computing
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Eckert, Marcel; Meyer, Dominik; Haase, Jan; Klauer, Bernd (2016-11-30).
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1386:"The Design of a RISC Architecture and its Implementation with an FPGA"
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has developed two styles of partial reconfiguration of FPGA devices:
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permits to reconfigure distinct modular parts of the design, while
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An FPGA board is being used to recreate the Vector-06C computer
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combining reconfigurable computing-based accelerators like
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Creative Commons Attribution 4.0 International (CC BY 4.0)
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1230:"NSF center for High-performance Reconfigurable Computing"
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has developed a SDK that enables software written using a
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ACM Transactions on Reconfigurable Technology and Systems
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have developed a hybrid embedded computing system called
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Table 1: Nick Tredennick's Paradigm Classification Scheme
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Lectures on Reconfigurable Computing at Brown University
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987:. Hoffmann, K.-H. (Karl-Heinz). Berlin: Springer. 2002.
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Berichte der Bunsengesellschaft für Physikalische Chemie
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are often used as a support to partial reconfiguration.
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while the other portion keeps its former configuration.
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1285:"Altera and IBM Unveil FPGA-Accelerated POWER Systems"
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Füchslin, Rudolf M.; McCaskill, John S. (2001-07-31).
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can be used when a small change is made to a design.
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may be too technical for most readers to understand
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893:(FCCM '97, April 16–18, 1997), pp. 24–33.
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306:High-Performance Reconfigurable Computing
64:Learn how and when to remove this message
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133:Field-Programmable Gate Array
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236:Configware (configuration)
144:Tredennick's Classification
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847:10.1109/MAHC.2002.1114865
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1261:. 2011. Archived from
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1503:. Intel. pp. 4–1
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131:(the inventor of the
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1983:Microchip Technology
1783:High-level synthesis
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583:improve this article
506:National Instruments
501:National Instruments
295:Von Neumann syndrome
265:Hartenstein's Xputer
241:Algorithms variable
210:Algorithms variable
2242:Digital electronics
2052:Intel Quartus Prime
1773:Soft microprocessor
1265:on October 12, 2010
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283:von Neumann machine
233:Resources variable
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259:Nick Tredennick
247:(data streams)
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89:microprocessors
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789:iLAND project
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630:This section
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316:with CPUs or
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113:Gerald Estrin
106:
104:
102:
98:
94:
90:
86:
82:
78:
68:
65:
57:
47:
43:
37:
34:This article
32:
23:
22:
19:
2121:LatticeMico8
2111:ARM Cortex-M
2087:Intellectual
1760:
1606:
1592:
1584:
1538:
1534:
1505:. Retrieved
1492:
1480:. Retrieved
1471:
1459:. Retrieved
1450:
1438:. Retrieved
1429:
1417:. Retrieved
1404:
1392:. Retrieved
1379:
1367:. Retrieved
1358:
1339:
1333:
1314:
1310:
1300:
1289:. Retrieved
1279:
1267:. Retrieved
1263:the original
1258:
1249:
1237:. Retrieved
1233:
1224:
1199:
1195:
1189:
1157:(2): 69–76.
1154:
1150:
1144:
1135:
1127:
1122:
1113:
1060:
1056:
1046:
1035:
1025:
984:
979:
938:
933:
908:
904:
898:
890:
885:
876:
868:
863:
838:
834:
828:
799:One chip MSX
766:
762:
754:
750:
737:
728:
719:
699:
687:
678:
663:
657:January 2015
654:
631:
601:
595:January 2015
592:
581:Please help
576:verification
573:
546:
536:
532:
528:
525:module-based
524:
519:
504:
488:
476:
459:
435:
429:
424:
420:
413:
409:
399:
386:
385:
369:
362:
355:
344:
325:
308:(HPRC) is a
305:
304:
278:anti-machine
276:
274:
255:anti machine
252:
218:
187:
156:
149:
125:
110:
99:and add new
76:
75:
60:
51:
35:
18:
2151:Open-source
2098:Proprietary
1907:Flow to HDL
1724:Logic block
1507:15 November
1482:15 November
1461:15 November
1440:15 November
1311:Electronics
1202:(4): 1–23.
911:(9): 1114.
684:Granularity
332:coprocessor
328:PCI express
97:manufacture
2231:Categories
2126:MicroBlaze
2077:Simulators
2057:Xilinx ISE
1409:Jan Gray.
1317:(4): 545.
1291:2014-12-14
1269:August 19,
1239:August 19,
841:(4): 3–9.
821:References
641:improve it
510:CompactRIO
490:Mitrionics
485:Mitrionics
473:COPACOBANA
416:encryption
336:peripheral
321:processors
318:multi-core
2196:Microwatt
2191:Libre-SOC
2186:Power ISA
2169:OpenCores
2131:PicoBlaze
1938:Accellera
1931:Companies
1798:Languages
1557:1687-7195
1159:CiteSeerX
1087:0027-8424
1011:cite book
965:cite book
925:0005-9021
804:PipeRench
645:verifying
391:circuitry
2174:OpenRISC
2089:property
2067:ModelSim
2045:Software
2019:Hardware
2012:Products
1998:Synopsys
1968:Infineon
1943:Achronix
1902:C to HDL
1897:OpenVera
1862:Handel-C
1702:Concepts
1570:license.
1541:: 1–11.
1216:10270587
1181:14469864
1105:11470896
1003:49750250
957:39655211
814:Sprinter
772:See also
405:software
342:sphere.
245:Flowware
139:Theories
54:May 2009
2141:Nios II
2031:Stratix
1993:Siemens
1978:Lattice
1963:Cadence
1852:SystemC
1806:Verilog
1599:, 2008.
1065:Bibcode
855:7923912
639:Please
403:, like
363:The US
225:
194:
163:
107:History
40:Please
2203:RISC-V
2062:Vivado
2036:Virtex
1922:Chisel
1882:PALASM
1766:Xputer
1623:1993.)
1555:
1346:
1214:
1179:
1161:
1103:
1093:
1085:
1001:
991:
955:
945:
923:
853:
794:M-Labs
521:Xilinx
516:Xilinx
271:Xputer
129:Xilinx
1973:Intel
1953:Aldec
1912:MyHDL
1833:VITAL
1501:(PDF)
1419:6 Sep
1414:(PDF)
1394:6 Sep
1389:(PDF)
1369:6 Sep
1212:S2CID
1177:S2CID
1096:55395
851:S2CID
740:FPGAs
548:Intel
543:Intel
467:C-One
205:none
182:none
174:none
101:chips
79:is a
2179:1200
2136:Nios
2116:LEON
1917:ELLA
1892:CUPL
1887:ABEL
1867:Lola
1857:AHDL
1823:VHDL
1756:PSoC
1736:EPLD
1731:CPLD
1719:FPGA
1709:ASIC
1553:ISSN
1539:2016
1509:2016
1484:2016
1463:2016
1442:2016
1421:2012
1396:2012
1371:2012
1344:ISBN
1271:2011
1241:2011
1101:PMID
1083:ISSN
1030:2003
1017:link
999:OCLC
989:ISBN
971:link
953:OCLC
943:ISBN
921:ISSN
809:PSoC
710:FPGA
702:rDPA
695:FPGA
527:and
347:SIMD
287:FPGA
2208:Zet
2159:JOP
2106:ARC
2072:VTR
2026:iCE
1988:NXP
1958:Arm
1948:AMD
1877:UPF
1872:PSL
1845:DPI
1828:AMS
1816:AMS
1751:GAL
1746:PAL
1741:PLA
1714:SoC
1543:doi
1319:doi
1204:doi
1169:doi
1091:PMC
1073:doi
913:doi
843:doi
643:by
585:by
469:).
372:IBM
119:or
44:to
2233::
1595:,
1551:.
1537:.
1533:.
1517:^
1315:11
1313:.
1309:.
1257:.
1232:.
1210:.
1198:.
1175:.
1167:.
1155:41
1153:.
1099:.
1089:.
1081:.
1071:.
1061:98
1059:.
1055:.
1013:}}
1009:{{
997:.
967:}}
963:{{
951:.
919:.
909:98
907:.
849:.
839:24
837:.
760:.
531:.
378:.
353:.
323:.
297:.
1811:A
1687:e
1680:t
1673:v
1559:.
1545::
1511:.
1486:.
1465:.
1444:.
1423:.
1398:.
1373:.
1352:.
1327:.
1321::
1294:.
1273:.
1243:.
1218:.
1206::
1200:1
1183:.
1171::
1107:.
1075::
1067::
1019:)
1005:.
973:)
959:.
927:.
915::
857:.
845::
670:)
664:(
659:)
655:(
637:.
608:)
602:(
597:)
593:(
579:.
465:(
67:)
61:(
56:)
52:(
38:.
Text is available under the Creative Commons Attribution-ShareAlike License. Additional terms may apply.