25:
246:
512:
stack pointers for user and system modes. Normally, only a set of 8 registers can be addressed from a 3-bit code; addressing all registers requires an additional 6/8-bit code byte that can only be inserted in the prefixed addressing mode operand, restricting which combinations of registers can be used for the source and destination operands.
226:
506:
In maximum mode, there are 4 banks of four 32-bit registers, each of which can be split into two 16-bit halves or four 8-bit quarters. In the minimum mode of early models, there are 8 banks of four 16-bit registers, which can be split into 8-bit halves. The processor can use the current bank (pointed
530:
The TLCS-900 also includes 4 "microDMA" transfer channels, each of which have programmable source and destination addresses, transfer counts, data sizes (byte, word, and longword), and various transfer modes. These are triggered the same way as normal interrupts, and interrupt program execution upon
511:
field in the 16-bit status register SR), the previous bank to be compatible with the alternate register scheme of the TLCS-90, or any arbitrary bank number from 0 to 7. There is also a fixed set of four 32-bit registers, with one of them dedicated as the stack pointer. Early models had two separate
498:
The instruction set is mostly upward-compatible with the TLCS-90, although the binary encoding differs. The same scheme of encoding the addressing mode before the instruction's opcode and additional operands is implemented. The early models supported both a "minimum mode" where the banked registers
312:
There are, however, significant differences. It omits the separate I/O address space of the Z80, but adds more flexibility to operand combinations, some new operations (notably multiply and divide), and several additional
707:
As demand for these features differs widely depending on the requirements for a specific project (low energy consumption; high number of I/O ports; etc.), customers can choose from a wide range of different versions.
478:
The TLCS-900 family inherits most features from the TLCS-90 architecture, and includes 32-bit registers and a 24-bit address bus. Most implementations (TLCS-900, TLCS-900/L, TLCS-900/H and TLCS-900/L1 series) have
416:
are prefixes which begin an extended instruction. The instruction encoding is unusual in that the prefix specifies one operand of the extended instruction, and unlike the single-byte prefixes used by the Z80 or
393:
TLCS-90 SoC packages include the 4-bit BX and BY registers, which get concatenated with effective addresses based on the IX or IY register, allowing the processor to address up to one
788:
994:
432:, where the first two bytes specify the destination address, the third byte specifies the operation, and the fourth byte provides the source operand.
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architecture, may itself be followed by operand bytes. After the prefix bytes, the second opcode byte specifies the operation and second operand.
942:
100:
architectures. Individual components generally have a part number beginning with "TMP". E.g. the TMP8048AP is a member of the TLCS-48 family.
839:
Encyclopedia of
Computer Science and Technology: Volume 10 - Linear and Matrix Algebra to Microorganisms: Computer-Assisted Identification
779:
46:
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68:
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instructions, which are useful for performing 20-bit pointer arithmetic using the IX and BX registers or the IY and BY registers.
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Most of the functionality of 8-bit accumulator A has also been implemented for the 16-bit HL register pair, such as the missing
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were 16 bits wide, and a "maximum mode" which had all 32-bit general purpose registers. Later models omitted the minimum mode.
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addressing without a displacement, enabling a single byte of machine code to be saved and the execution time to be decreased
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The microcontrollers in the TLCS-870 family (TLCS-870, TLCS-870/X, TLCS-870/C and TLCS-870/C1 series) use a
122:
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The TLCS-870 is the original, with a 16-bit address space, which was extended in two different directions:
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The F register (low 8-bit half of the 16-bit register SR) has an alternate register called F'. Executing
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PC-relative long (-32768 to +32767 bytes from the program counter, rather than the shorter -128 to +127)
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is a free assembler supporting the TLCS-47, TLCS-870, TLCS-90, TLCS-900 and TLCS-9000 families.
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642:), thus allowing either low-power low-frequency modes or high-performance high-frequency modes
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manufactured by
Toshiba. It began development in 1971, and was completed in 1973. It was a 32
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Instructions are divided into one-byte basic and two-byte extended instructions. Opcodes E0
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six 16-bit registers (BC, DE, HL, IX, IY, and SP), three of which are 8-bit register pairs,
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system, which began production in 1974 and went into mass production in 1975. The
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multifunction, bi-directional general purpose I/O ports with optional built-in
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TLCS-870/C1 is an upward-compatible variant of the 870/C with minor extensions.
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TLCS-870/X extends the architecture to 20 bits in an upward-compatible way.
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TLCS-870/C retains the 16-bit address space, and provides a compatible
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dual clock inputs and on-line clock switching by selecting different
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Current TLCS processors offer some or all of the following features:
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systems. These are no longer advertised on the
Toshiba website.
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924:. Toshiba Corporation Semiconductor Company. 16 December 2008.
611:
418:
266:
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18:
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architecture inspired by the TLCS-90, but less like the Z80.
249:
Development version of a TLCS-90 family microcontroller with
193:, an improved version of the TLCS-12, was announced in 1975.
462:, but changes the instruction encoding so that a different
386:
flag quirk from the Z80 is implemented. Furthermore, the
269:. These are no longer advertised on the Toshiba website.
892:"MAME soure code: src/devices/cpu/tlcs870/tlcs870d.cpp"
948:. Toshiba corporation. 1994 – via Bitsavers.org.
943:"TLCS-900 Series 16-bit Microcontroller User's Manual"
836:
Belzer, Jack; Holzman, Albert G.; Kent, Allen (1978).
809:"1973: 12-bit engine-control microprocessor (Toshiba)"
534:
The TLCS-900/H model was most prominently used in the
390:
instruction was added to ease 16-bit loop counting.
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16:Prefix applied to microcontrollers made by Toshiba
272:The TLCS-90 inherits most Z80 features, such as:
257:The microcontrollers in the TLCS-90 family use a
201:The microcontrollers in the TLCS-47 category are
92:. The product line includes multiple families of
276:seven 8-bit registers (A, B, C, D, E, H and L),
988:
590:Synchronous/Asynchronous Serial Peripherals (
8:
774:
772:
770:
768:
766:
764:
963:Toshiba Japan website about the TLCS series
342:" addressing of memory from FF00–FFFF
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1100:
995:
981:
973:
968:Toshiba USA website about the TLCS series
937:
935:
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519:from the TLCS-90 requires executing both
69:Learn how and when to remove this message
648:8-bit and 16-bit timers (may be used as
32:This article includes a list of general
760:
885:
883:
748:Alfred Arnold's The Macroassembler AS
731:. Neither tool is available for free.
397:of memory. The processor includes the
213:The TLCS-48 family were clones of the
816:Semiconductor History Museum of Japan
328:indexed modes operating similarly to
7:
919:"TLCS-870/C1 Series Instruction Set"
781:8-Bit Microcontroller: TLCS-48, -90
487:, while the TLCS-900/H1 series is
282:the combined parity/overflow flag,
38:it lacks sufficient corresponding
14:
1617:High voltage parallel programming
743:project for porting GNU assembler
670:supply range between 1.8 and 5.5
297:16-bit exchange instructions, and
794:from the original on 2020-03-28.
582:a variety of serial interfaces:
265:architecture reminiscent of the
23:
1701:List of common microcontrollers
1611:High-voltage serial programming
606:Serial Peripheral Interface Bus
1731:List of Wi-Fi microcontrollers
483:internal data paths, like the
1:
1752:Programmable logic controller
1593:In-circuit serial programming
661:programmable pulse generation
424:For example, the instruction
237:compatible microcontrollers.
1018:Single-board microcontroller
650:Programmable Interval Timers
1605:Program and Debug Interface
579:versions are also available
1799:
787:. Toshiba. November 1988.
531:the transferring process.
491:wide internally (like the
382:bitwise instructions. The
107:
1023:Special function register
868:"新HPCの歩み（第54回）－1975年(b)－"
308:memory copy instructions.
745:to the TLCS-900 family.
546:Features and differences
217:(8048) microcontroller.
1757:List of microprocessors
1654:Joint Test Action Group
736:Small Device C Compiler
233:These were a series of
123:central processing unit
84:is a prefix applied to
53:more precise citations.
738:supports the TLCS-90.
657:pulse-width modulation
370:instructions, and the
254:
230:
133:chip with about 2,800
131:MOS integrated circuit
1599:In-system programming
565:one time programmable
248:
228:
149:. It was used in the
108:Further information:
1668:In-circuit debugging
540:Neo Geo Pocket Color
1724:Renesas Electronics
1674:In-circuit emulator
624:multiplexed 10-bit
594:/USART) (used with
154:engine control unit
716:Toshiba offers an
255:
231:
114:The TLCS-12 was a
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1764:
1689:
1688:
1574:
1573:
1255:PIC10/12/16/17/18
712:Development tools
684:pattern generator
655:8-bit and 16-bit
640:frequency divider
561:mask programmable
556:pull-up resistors
460:assembly language
160:included 512-bit
79:
78:
71:
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1778:Microcontrollers
1705:By manufacturer
1649:Nexus (standard)
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1101:
1004:Microcontrollers
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890:Haywood, David.
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694:Chip select/wait
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86:microcontrollers
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49:this article by
40:inline citations
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1680:In-target probe
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846:. p. 402.
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686:, suitable for
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501:program counter
476:
474:TLCS-900 family
438:
436:TLCS-870 family
415:
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403:DECX ($ FF00+n)
399:INCX ($ FF00+n)
345:
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221:TLCS-Z80 family
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45:Please help to
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957:External links
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630:D/A converters
626:A/D converters
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619:watchdog timer
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536:Neo Geo Pocket
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426:ADD (IX+127),5
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119:microprocessor
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1033:Architectures
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688:stepper motor
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669:
665:
662:
658:
654:
651:
647:
644:
641:
637:
633:
631:
627:
623:
620:
617:
613:
610:
607:
604:
601:
597:
593:
589:
587:
584:
583:
581:
578:
575:type of ROM.
574:
570:
566:
562:
559:
557:
553:
552:
551:
545:
543:
541:
537:
532:
528:
517:EX AF,AF'
513:
504:
502:
496:
494:
490:
486:
482:
473:
468:
465:
461:
457:
454:
453:
452:
449:
447:
443:
435:
433:
422:
420:
406:
396:
391:
357:
347:
341:
338:single-byte "
337:
320:
319:
318:
316:
299:
291:EX AF,AF'
284:
281:
278:
275:
274:
273:
270:
268:
264:
260:
252:
247:
240:
238:
236:
227:
220:
218:
216:
208:
206:
204:
196:
194:
190:
185:
181:
173:
170:
163:
159:
158:system memory
155:
152:
148:
144:
140:
136:
135:silicon gates
132:
124:
120:
117:
111:
103:
101:
99:
95:
91:
87:
83:
73:
70:
62:
52:
48:
42:
41:
35:
30:
21:
20:
1561:ARM Cortex-R
1512:
1432:ARM Cortex-R
1363:
1289:
1135:
913:
901:. Retrieved
895:
871:. Retrieved
862:
838:
831:
819:. Retrieved
815:
803:
780:
747:
740:
733:
715:
706:
701:chip carrier
663:(PPG) output
635:
569:flash memory
549:
533:
529:
514:
505:
497:
477:
466:is required.
450:
439:
423:
407:
392:
388:DJNZ BC,addr
361:
311:
271:
256:
232:
215:Intel MCS-48
212:
200:
143:6 μm process
113:
81:
80:
65:
56:
37:
1586:Programming
1349:PIC24/dsPIC
1285:Rabbit 2000
1096:Word length
741:There is a
720:compatible
646:prescalable
636:gear values
602:, and more)
525:EX F,F'
521:EX A,A'
464:object code
430:F4 7F 68 05
187: [
51:introducing
1772:Categories
1623:Bootloader
1579:Interfaces
873:2023-11-20
755:References
699:different
696:controller
659:(PWM) and
507:to by the
412:through FE
147:NMOS logic
139:fabricated
34:references
1660:debugWIRE
1642:Debugging
1566:PowerPC64
1503:Propeller
1211:MELPS 740
844:CRC Press
734:The free
729:assembler
678:interrupt
676:external
384:ADD HL,rr
340:zero page
235:Zilog Z80
59:July 2009
1740:See also
1719:Infineon
1513:TLCS-900
1479:ColdFire
1400:Cortex-M
1364:TLCS-900
1290:TLCS-870
903:25 April
789:Archived
725:compiler
395:megabyte
287:EX DE,HL
184:TLCS-12A
151:Ford EEC
110:Ford EEC
88:made by
1783:Toshiba
1662:(Atmel)
1656:(JTAG)
1518:TriCore
1491:PowerPC
1387:Am29000
1260:ST6/ST7
1141:TMS1000
1136:TLCS-47
821:27 June
797:Alt URL
727:and an
703:formats
690:control
680:control
668:voltage
577:ROMless
493:MC68020
489:32 bits
485:MC68000
104:TLCS-12
90:Toshiba
47:improve
1619:(HVPP)
1613:(HVSP)
1595:(ICSP)
1548:64-bit
1538:Z80000
1533:Xtensa
1508:SuperH
1496:MPC5xx
1379:32-bit
1344:MSP430
1334:CR16/C
1315:68HC12
1310:65C816
1302:16-bit
1206:65C265
1201:65C134
1179:68HC11
1174:68HC08
1169:68HC05
1146:μCOM-4
1118:COP400
1113:Am2900
1081:RISC-V
1071:MPS430
897:GitHub
850:
718:ANSI C
666:power
600:RS-485
596:RS-232
573:EEPROM
481:16-bit
446:16-bit
378:, and
334:(IY+d)
330:(IX+d)
326:(HL+A)
322:(SP+d)
263:16-bit
253:socket
182:. The
176:
166:
127:
116:12-bit
36:, but
1709:Intel
1694:Lists
1682:(ITP)
1676:(ICE)
1670:(ICD)
1633:aWire
1607:(PDI)
1601:(ISP)
1486:PIC32
1474:68000
1469:MN103
1437:AVR32
1420:STM32
1405:EFM32
1369:Z8000
1324:80186
1233:XC800
1156:8-bit
1131:S1C6x
1126:PPS-4
1122:MARC4
1105:4-bit
1041:68000
946:(PDF)
922:(PDF)
812:(PDF)
792:(PDF)
785:(PDF)
621:(WDT)
608:(SPI)
442:8-bit
259:8-bit
251:EPROM
203:4-bit
191:]
180:EPROM
174:and 2
145:with
141:on a
1523:V850
1464:M32R
1459:H8SX
1452:FR-V
1359:RL78
1329:C166
1280:eZ80
1265:STM8
1245:COP8
1228:8051
1223:8048
1196:6502
1189:RS08
1164:6800
1066:MIPS
1046:8051
1011:Main
905:2020
848:ISBN
823:2019
672:Volt
592:UART
538:and
523:and
499:and
401:and
366:and
353:(IY)
351:and
349:(IX)
332:and
324:and
306:LDDR
304:and
302:LDIR
300:the
293:and
285:the
121:and
98:RISC
96:and
94:CISC
82:TLCS
1628:ROM
1556:ARC
1442:CRX
1425:XMC
1415:SAM
1410:LPC
1397:ARM
1392:ARC
1354:R8C
1339:H8S
1275:Z80
1240:AVR
1218:78K
1184:S08
1086:x86
1076:PIC
1061:AVR
1056:ARM
1051:ARC
612:USB
586:I²C
571:or
509:RFP
495:).
419:x86
376:XOR
372:AND
364:SUB
295:EXX
267:Z80
178:kb
172:ROM
164:, 2
162:RAM
129:mm
1774::
1528:RX
1447:FR
1319:16
1270:Z8
1250:H8
930:^
894:.
882:^
842:.
814:.
763:^
628:;
598:,
567:,
563:,
542:.
527:.
414:16
410:16
380:OR
374:,
368:CP
344:16
317::
289:,
189:jp
169:kb
137:,
1317:/
996:e
989:t
982:v
907:.
876:.
856:.
825:.
722:C
652:)
638:(
444:/
261:/
72:)
66:(
61:)
57:(
43:.
Text is available under the Creative Commons Attribution-ShareAlike License. Additional terms may apply.
