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NVAX

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The NVAX+, introduced at the same time, was identical in terms of the processor design but used a different bus, cache system and its external connection was a 431-pin array. These were identical to those on the Alpha, allowing an NVAX+ machine to be upgraded to an Alpha simply by changing the CPU.
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In 1994, the NVAX++ (also known as NV5) was introduced in VAX 7000 Model 7x0 and VAX 10000 Model 7x0 systems. It operated at 133 MHz (7.5 ns) and was fabricated in Digital's fifth-generation CMOS process, CMOS-5, a 0.50 μm process. It improved performance to 50 VUPs. In 1996, a 170.9 MHz NV5 was
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The I-box fetches and decodes VAX instructions. It also contains the 2 KB direct-mapped virtual instruction cache (VIC) and the 512-entry by 4-bit branch history table. The I-box aimed to fetch eight bytes of instruction data from the VIC during every cycle.
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The NVAX is partitioned into five semi-autonomous units, the I-box, E-box, F-box, M-box and C-box. The NVAX is macropipelined. Multiple VAX macroinstructions are processed in parallel by autonomous units, which have their own micropipelines.
56:(ISA). A variant of the NVAX, the NVAX+, differed in the bus interface and external cache supported, but was otherwise identical in regards to microarchitecture. The NVAX+ was designed to have the same bus as the 176:
The F-box executes floating-point instructions as well as 32-bit integer multiply instructions. It has a four-stage floating-point and integer multiply pipeline and a non-pipelined floating-point divider.
133:. The NVAX was offered at a variety of clock speeds, 83.3 MHz (12 ns), 71 MHz (14 ns) and 62.5 MHz (16 ns), while the NVAX+ is clocked at a frequency of 90.9 MHz (11 ns). The NVAX offered about 25 94:
The NVAX was offered at a variety of clock speeds, 83.3 MHz (12 ns), 71 MHz (14 ns) and 62.5 MHz (16 ns), while the NVAX+ is clocked at a frequency of 90.9 MHz (11 ns). The NVAX offered about 25
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These changes also allowed it to operate with slightly higher performance, and the NVAX+ ran at roughly 35 VUPs. This was only slightly less than the
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The final model in the series was the NVAX++, or NV5, offering 50 VUPs. This was the last VAX processor, DEC had moved entirely to the
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Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors
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in Digital's fourth-generation CMOS process, CMOS-4, a 0.75 μm process with three layers of
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Fox, Thomas F. (1994). "The design of high-performance microprocessors at Digital".
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The NVAX and NVAX+ was used in late-model VAX systems released in 1991 such as the
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The E-box executes most non-floating-point instructions. It is controlled by
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Badeau, R.W. et al. (1992). "A 100-MHz macropipelined VAX microprocessor".
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Digital Technical Journal: special issue on NVAX-microprocessor VAX systems
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Anderson, W. (1992). "Logical verification of the NVAX CPU chip design".
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mainframe's roughly 40 VUPs, but available in a desktop form factor.
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Proceedings of the 31st Annual ACM-IEEE Design Automation Conference
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measuring 16.2 by 14.6 mm in size (236.52 mm²). The die was
188:"The NVAX and NVAX+ High-performance VAX Microprocessors" 16:
CMOS microprocessor by Digital Equipment Corporation
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Booting a 71 MHz VAXstation 4000 Model 90 to NetBSD
201:, Volume 4, Number 3, Summer 1992. pp. 11–23. 149:introduced, used in the VAX 7000/10000 Model 8x0. 293:"NVAX" at The Computer History Simulation Project 318: 8: 267:, Volume 27, Issue 11. pp. 1585–1598. 117:NVAX contained 1.3 million transistors on a 397: 375: 325: 311: 303: 173:with the capability to patch 20 words. 7: 1241: 934:Digital Storage Systems Interconnect 265:IEEE Journal of Solid-State Circuits 129:. The NVAX is packaged in a 339-pin 19:For the company traded as NVAX, see 1008:Dynamically Redefined Character Set 954:Synchronous Backplane Interconnect 14: 233:. (Digital Equipment Corporation) 1240: 1231: 1230: 1221: 1220: 60:, allowing drop-in replacement. 1148:Maintenance Operations Protocol 1: 1038:Mass Storage Control Protocol 334:Digital Equipment Corporation 145:mainframe's roughly 40 VUPs. 47:Digital Equipment Corporation 1128:Digital Federal Credit Union 350:(founder and CEO, 1957–1992) 54:instruction set architecture 1172:Sequence and Batch Language 1133:Dynamic debugging technique 49:(DEC) that implemented the 1288: 1163:Record Management Services 949:Standard Disk Interconnect 45:developed and produced by 18: 1216: 1197:The Ultimate Entrepreneur 373: 199:Digital Technical Journal 186:Uhler, Michael G. et al. 860:DIGITAL Command Language 1186:Systems Research Center 1181:System Reference Manual 237: (3). Summer 1992. 207:"VAX CPU Model Summary" 135:VAX Unit of Performance 96:VAX Unit of Performance 1272:32-bit microprocessors 1153:On-line Debugging Tool 127:aluminium interconnect 31: 252:. pp. 306–309. 29: 1143:Local Area Transport 901:National Replacement 282:. pp. 586–591. 1267:DEC microprocessors 1003:Digital Linear Tape 362:(VP of engineering) 1226:Computers template 214:2022-03-28 at the 193:2014-11-29 at the 169:from a 1,600-word 109:after that point. 32: 1254: 1253: 557: 556: 205:Nuessgen, Marco. 153:Microarchitecture 30:DEC NVAX die shot 1279: 1244: 1243: 1234: 1233: 1224: 1223: 1018:Flip-Chip module 911:Special Graphics 398: 379: 368:(CEO, 1992–1998) 327: 320: 313: 304: 210: 1287: 1286: 1282: 1281: 1280: 1278: 1277: 1276: 1257: 1256: 1255: 1250: 1212: 1077: 973: 920: 880:(Multinational) 864: 816: 809: 704: 697: 564: 553: 532: 477: 425: 391: 387: 386:Instruction set 380: 371: 354:Harlan Anderson 336: 331: 289: 225: 223:Further reading 216:Wayback Machine 204: 195:Wayback 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Index

Novavax

CMOS
microprocessor
Digital Equipment Corporation
VAX
instruction set architecture
DECchip 21064
MicroVAX 3100
VAXstation 4000
VAX 4000
VAX 6000
VAX 7000/10000
VAXft
DECchip 21064
VAX Unit of Performance
VAX 9000
DEC Alpha
die
fabricated
aluminium interconnect
pin grid array
VAX Unit of Performance
VAX 9000
microcode
control store
"The NVAX and NVAX+ High-performance VAX Microprocessors"
Archived
Wayback Machine
"VAX CPU Model Summary"

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