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The NVAX+, introduced at the same time, was identical in terms of the processor design but used a different bus, cache system and its external connection was a 431-pin array. These were identical to those on the Alpha, allowing an NVAX+ machine to be upgraded to an Alpha simply by changing the CPU.
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In 1994, the NVAX++ (also known as NV5) was introduced in VAX 7000 Model 7x0 and VAX 10000 Model 7x0 systems. It operated at 133 MHz (7.5 ns) and was fabricated in
Digital's fifth-generation CMOS process, CMOS-5, a 0.50 μm process. It improved performance to 50 VUPs. In 1996, a 170.9 MHz NV5 was
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The I-box fetches and decodes VAX instructions. It also contains the 2 KB direct-mapped virtual instruction cache (VIC) and the 512-entry by 4-bit branch history table. The I-box aimed to fetch eight bytes of instruction data from the VIC during every cycle.
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The NVAX is partitioned into five semi-autonomous units, the I-box, E-box, F-box, M-box and C-box. The NVAX is macropipelined. Multiple VAX macroinstructions are processed in parallel by autonomous units, which have their own micropipelines.
56:(ISA). A variant of the NVAX, the NVAX+, differed in the bus interface and external cache supported, but was otherwise identical in regards to microarchitecture. The NVAX+ was designed to have the same bus as the
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The F-box executes floating-point instructions as well as 32-bit integer multiply instructions. It has a four-stage floating-point and integer multiply pipeline and a non-pipelined floating-point divider.
133:. The NVAX was offered at a variety of clock speeds, 83.3 MHz (12 ns), 71 MHz (14 ns) and 62.5 MHz (16 ns), while the NVAX+ is clocked at a frequency of 90.9 MHz (11 ns). The NVAX offered about 25
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The NVAX was offered at a variety of clock speeds, 83.3 MHz (12 ns), 71 MHz (14 ns) and 62.5 MHz (16 ns), while the NVAX+ is clocked at a frequency of 90.9 MHz (11 ns). The NVAX offered about 25
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87:. Although Digital updated the design throughout the early 1990s, the processors, and the VAX platform itself, were ultimately superseded by the introduction of the
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These changes also allowed it to operate with slightly higher performance, and the NVAX+ ran at roughly 35 VUPs. This was only slightly less than the
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The final model in the series was the NVAX++, or NV5, offering 50 VUPs. This was the last VAX processor, DEC had moved entirely to the
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Proceedings 1992 IEEE International
Conference on Computer Design: VLSI in Computers & Processors
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Fox, Thomas F. (1994). "The design of high-performance microprocessors at
Digital".
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The NVAX and NVAX+ was used in late-model VAX systems released in 1991 such as the
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Badeau, R.W. et al. (1992). "A 100-MHz macropipelined VAX microprocessor".
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Digital
Technical Journal: special issue on NVAX-microprocessor VAX systems
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Anderson, W. (1992). "Logical verification of the NVAX CPU chip design".
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mainframe's roughly 40 VUPs, but available in a desktop form factor.
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Proceedings of the 31st Annual ACM-IEEE Design
Automation Conference
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measuring 16.2 by 14.6 mm in size (236.52 mm²). The die was
188:"The NVAX and NVAX+ High-performance VAX Microprocessors"
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CMOS microprocessor by
Digital Equipment Corporation
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Booting a 71 MHz VAXstation 4000 Model 90 to NetBSD
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149:introduced, used in the VAX 7000/10000 Model 8x0.
293:"NVAX" at The Computer History Simulation Project
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267:, Volume 27, Issue 11. pp. 1585–1598.
117:NVAX contained 1.3 million transistors on a
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173:with the capability to patch 20 words.
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934:Digital Storage Systems Interconnect
265:IEEE Journal of Solid-State Circuits
129:. The NVAX is packaged in a 339-pin
19:For the company traded as NVAX, see
1008:Dynamically Redefined Character Set
954:Synchronous Backplane Interconnect
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233:. (Digital Equipment Corporation)
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60:, allowing drop-in replacement.
1148:Maintenance Operations Protocol
1:
1038:Mass Storage Control Protocol
334:Digital Equipment Corporation
145:mainframe's roughly 40 VUPs.
47:Digital Equipment Corporation
1128:Digital Federal Credit Union
350:(founder and CEO, 1957–1992)
54:instruction set architecture
1172:Sequence and Batch Language
1133:Dynamic debugging technique
49:(DEC) that implemented the
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1163:Record Management Services
949:Standard Disk Interconnect
45:developed and produced by
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1197:The Ultimate Entrepreneur
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199:Digital Technical Journal
186:Uhler, Michael G. et al.
860:DIGITAL Command Language
1186:Systems Research Center
1181:System Reference Manual
237: (3). Summer 1992.
207:"VAX CPU Model Summary"
135:VAX Unit of Performance
96:VAX Unit of Performance
1272:32-bit microprocessors
1153:On-line Debugging Tool
127:aluminium interconnect
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252:. pp. 306–309.
29:
1143:Local Area Transport
901:National Replacement
282:. pp. 586–591.
1267:DEC microprocessors
1003:Digital Linear Tape
362:(VP of engineering)
1226:Computers template
214:2022-03-28 at the
193:2014-11-29 at the
169:from a 1,600-word
109:after that point.
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153:Microarchitecture
30:DEC NVAX die shot
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544:MicroPRISM
393:processors
341:Key people
181:References
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998:DECwriter
969:VAXBI bus
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892:(Turkish)
855:VAX MACRO
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348:Ken Olsen
273:0018-9200
243:0898-901X
167:microcode
107:DEC Alpha
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980:hardware
906:RADIX 50
845:MACRO-11
840:MACRO-10
563:Computer
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785:VAX/VMS
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512:21164PC
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978:Other
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775:DSM-11
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758:RSTS/E
748:DOS-11
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718:4K DMS
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687:VT520
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617:VT103
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483:Alpha
461:Rigel
85:VAXft
38:is a
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800:MICA
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473:NVAX
449:CVAX
439:V-11
421:J-11
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412:F-11
269:ISSN
254:ISBN
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36:NVAX
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