736:(Xbox 360) and called this enhancement VMX128. The enhancements comprise new routines targeted at gaming (accelerating 3D graphics and game physics) and a total of 128 registers. VMX128 is not entirely compatible with VMX/Altivec, as a number of integer operations were removed to make space for the larger register file and additional application-specific operations.
626:" declares a 128-bit vector variable named "foo" containing sixteen 8-bit unsigned chars. The full complement of arithmetic and binary operators is defined on vector types so that the normal C expression language can be used to manipulate vector variables. There are also overloaded intrinsic functions such as "
647:
The Power Vector Media
Extension (VMX) was developed between 1996 and 1998 by a collaborative project between Apple, IBM, and Motorola. Apple was the primary customer for Power Vector Media Extension (VMX) until Apple switched to Intel-made, x86-based CPUs on June 6, 2005. They used it to accelerate
578:
design, the vector registers, like the scalar registers, can only be loaded from and stored to memory. However, VMX/AltiVec provides a much more complete set of "horizontal" operations that work across all the elements of a vector; the allowable combinations of data type and operations are much more
790:
AltiVec prior to Power ISA 2.06 with VSX lacks loading from memory using a type's natural alignment. For example, the code below requires special handling for Power6 and below when the effective address is not 16-byte aligned. The special handling adds 3 additional instructions to a load operation
634:
based on the type of the elements within the vector, and very strong type checking is enforced. In contrast, the Intel-defined data types for IA-32 SIMD registers declare only the size of the vector register (128 or 64 bits) and in the case of a 128-bit register, whether it contains integers or
774:
class template due to the treatment of "vector" as a reserved word when the compiler does not implement the context-sensitive keyword version of vector. However, it may be possible to combine them using compiler-specific workarounds; for instance, in GCC one may do
621:
capabilities that attempt to intelligently create VMX/Altivec accelerated binaries without the need for the programmer to use intrinsics directly. The "vector" type keyword is introduced to permit the declaration of native vector types, e.g.,
515:
While AltiVec refers to an instruction set, the implementations in CPUs produced by IBM and
Motorola are separate in terms of logic design. To date, no IBM core has included an AltiVec logic design licensed from Motorola or vice versa.
594:, in which each byte of a resulting vector value can be taken from any byte of either of two other vectors, parametrized by yet another vector. This allows for sophisticated manipulations in a single instruction.
747:
introduced VSX vector-scalar instructions which extend SIMD processing for the Power ISA to support up to 64 registers, with support for regular floating point, decimal floating point and vector execution.
1092:
AltiVec prior to Power ISA 2.06 with VMX lacks 64-bit integer support. Developers who wish to operate on 64-bit data will develop routines from 32-bit components. For example, below are examples of 64-bit
2220:
672:. Motorola was the first to supply AltiVec enabled processors starting with their G4 line. AltiVec was also used in some embedded systems for high-performance digital signal processing.
421:
2178:
2150:
2164:
1105:. The permutes move the carry and borrow bits from columns 1 and 3 to columns 0 and 2 like in school-book math. A little-endian machine would need a different mask.
2360:
758:
New integer vector instructions were introduced by IBM following the VMX encodings as part of the VSX extension in Power ISA v3.0. Shall be introduced with
543:
feature 128-bit vector registers that can represent sixteen 8-bit signed or unsigned chars, eight 16-bit signed or unsigned shorts, four 32-bit ints or four
414:
755:
New instructions are introduced by IBM under the Vector Media
Extension category for integer operations as part of the VSX extension in Power ISA 2.07.
2313:
2191:
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2126:
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407:
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Power ISA 2.07 used in Power8 finally provided the 64-bit double words. A developer working with Power8 needs only to perform the following.
369:
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583:), and most VMX/AltiVec instructions take three register operands compared to only two register/register or register/memory operands on
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570:" data type, but it does not operate on 64-bit double-precision floats, and there is no way to move data directly between scalar and
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specification. This category is also known as VMX (used by IBM), and "Velocity Engine" (a brand name previously used by Apple).
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2346:
713:, also supports Power Vector Media Extension (VMX) in its PPU, with the SPU ISA being enhanced but architecturally similar.
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770:
In C++, the standard way of accessing AltiVec support is mutually exclusive with the use of the
Standard Template Library
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complete. Thirty-two 128-bit vector registers are provided, compared to eight for SSE and SSE2 (extended to 16 in
523:
specification. It was never formally a part of the PowerPC architecture until this specification although it used
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floating-point values. The programmer must select the appropriate intrinsic for the data types in use, e.g., "
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microprocessor, introduced in 2007, implements AltiVec. The last desktop microprocessor from IBM, the
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668:. Other companies such as Adobe used AltiVec to optimize their image-processing programs such as
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The following software applications are known to leverage AltiVec or VMX hardware acceleration.
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2242:"Peter Bergner - [PATCH, COMMITTED] Add full Power ISA 3.0 / POWER9 binutils support"
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687:(dubbed the "G5" by Apple) also implemented AltiVec with hardware similar to that of the
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Implementing instruction set architectures with non-contiguous register file specifiers
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AltiVec is a brandname trademarked by
Freescale (previously Motorola) for the standard
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Using data-parallel SIMD architecture in video games and supercomputers
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1437:/* Performs a-b as if the vector held two 64-bit double words */
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VMX/AltiVec is also unique in its support for a flexible vector
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owned solely by
Freescale, so the system is also referred to as
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Helios has a native POWER9 / POWER10 port with support for VMX.
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is the first Power ISA processor to implement Power ISA v2.06.
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2167:. IBM. October 2015. Archived from the original on 2008-01-20.
1952:
The following processors have AltiVec, VMX or VMX128 included
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2294:
Unrolling AltiVec, Part 1: Introducing the PowerPC SIMD unit
874:/* Natural alignment of vals is 4; and not 16 as required */
639:" for adding two vectors containing eight 16-bit integers.
1882:/* Performs a-b using native vector 64-bit double words */
1819:/* Performs a+b using native vector 64-bit double words */
716:
Freescale is bringing an enhanced version of AltiVec to
2132:. Power.org. Archived from the original on 2011-07-27
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Broadband Engine, used in (amongst other things) the
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16:SIMD instruction set extension for the PowerPC ISA
617:programs. As of version 4, the GCC also includes
609:to access VMX/AltiVec instructions directly from
2177:: CS1 maint: bot: original URL status unknown (
2149:: CS1 maint: bot: original URL status unknown (
1101:in C using a vector with four 32-bit words on a
558:They also exhibit important differences. Unlike
527:instruction formats and syntax and occupied the
675:IBM consistently left VMX out of their earlier
2617:(ABM: 2007, BMI1: 2012, BMI2: 2013, TBM: 2012)
531:space expressly allocated for such purposes.
464:'s Semiconductor Products Sector) — the
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472:processor architecture, including Motorola's
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8:
925:#if defined(__VSX__) || defined(_ARCH_PWR8)
551:-control instructions intended to minimize
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547:floating-point variables. Both provide
468:. It is implemented on versions of the
2677:(2008); ARMv8 also has AES instructions
2334:SIMD history and performance comparison
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783:keyword, and then use the GCC-specific
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605:compiler and other compilers provide
38:NXP (formerly Freescale and Motorola)
7:
2165:"The Microsoft Xbox 360 CPU story"
519:AltiVec is a standard part of the
14:
562:, VMX/AltiVec supports a special
555:when working on streams of data.
2777:Suspended extensions' dates are
2248:from the original on 2016-03-07
2223:from the original on 2022-01-25
2306:at Freescale; archived at the
1:
740:VSX (Vector Scalar Extension)
732:IBM enhanced VMX for use in
630:" that emit the appropriate
791:when VSX is not available.
510:Vector Multimedia Extension
2825:
2326:at Apple; archived at the
666:Quartz graphics compositor
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660:and key parts of Apple's
624:vector unsigned char foo;
2574:(FMA4: 2011, FMA3: 2012)
2316:at IBM; archived at the
2296:at IBM; archived at the
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535:Comparison to x86-64 SSE
512:) by IBM and P.A. Semi.
45:PowerPC e series (2006)
2632:Compressed instructions
599:GNU Compiler Collection
597:Recent versions of the
458:Freescale Semiconductor
787:keyword in its place.
448:designed and owned by
437:is a single-precision
178:PowerPC series (1992)
2809:Power microprocessors
2097:Software Applications
677:POWER microprocessors
652:applications such as
539:Both VMX/AltiVec and
2804:Cell BE architecture
2722:Transactional memory
2304:AltiVec Technologies
496:PA6T. AltiVec is a
345:OpenPOWER Foundation
2219:. IBM. 2016-03-01.
2206:US Patent 7,421,566
643:Development history
592:permute instruction
2127:"Power ISA v.2.03"
1982:MPC7447/7447A/7457
1956:Motorola/Freescale
1103:big-endian machine
637:_mm_add_epi16(x,y)
619:auto-vectorization
398:historic in italic
226:RAD series (1997)
82:Qor series (2008)
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2012:T4080/T4160/T4240
1792:<altivec.h>
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664:including in the
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2250:. Retrieved
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2211:
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2194:IBM Research
2187:
2159:
2134:. Retrieved
2100:
1977:MPC7445/7455
1951:
1783:
1091:
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769:
762:processors.
757:
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724:processors.
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698:part of the
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689:PowerPC 7400
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466:AIM alliance
441:and integer
434:
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265:IBM/Nintendo
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121:
114:
2645:MIPS16e ASE
2029:PowerPC 970
2017:B4420/B4860
2007:T2081/T2080
685:PowerPC 970
2793:Categories
2373:extensions
2276:2021-07-09
2252:2016-12-24
2227:2017-05-02
2136:2024-08-09
2110:References
1909:uint64x2_p
1897:uint64x2_p
1885:uint64x2_p
1846:uint64x2_p
1834:uint64x2_p
1822:uint64x2_p
1810:uint64x2_p
1665:uint32x4_p
1629:uint32x4_p
1590:uint32x4_p
1479:uint8x16_p
1464:uint32x4_p
1452:uint32x4_p
1440:uint32x4_p
1344:uint32x4_p
1308:uint32x4_p
1197:uint8x16_p
1182:uint32x4_p
1170:uint32x4_p
1158:uint32x4_p
1146:uint32x4_p
1128:uint8x16_p
1054:uint32x4_p
1018:uint8x16_p
988:uint8x16_p
958:uint8x16_p
916:uint32x4_p
832:uint32x4_p
814:uint8x16_p
650:multimedia
607:intrinsics
494:PWRficient
460:(formerly
312:PWRficient
2462:Power ISA
2443:MIPS SIMD
2085:P.A. Semi
2049:Cell B.E.
654:QuickTime
498:trademark
490:P.A. Semi
365:Power.org
360:Blue Gene
31:Power ISA
2768:(AMD-Vi)
2246:Archived
2221:Archived
2173:cite web
2145:cite web
1801:unsigned
1798:__vector
1789:#include
1722:vec_perm
1698:vec_andc
1674:vec_subc
1377:vec_perm
1353:vec_addc
1140:unsigned
1137:__vector
1122:unsigned
1119:__vector
1110:#include
1099:subtract
1060:vec_perm
967:vec_lvsl
877:unsigned
826:unsigned
823:__vector
808:unsigned
805:__vector
796:#include
785:__vector
662:Mac OS X
462:Motorola
288:Espresso
281:Broadway
2669:PadLock
2584:AVX-512
2450:PA-RISC
2433:MIPS-3D
2079:Power10
2002:MPC8610
1987:MPC7448
1972:MPC7450
1967:MPC7410
1962:MPC7400
1924:vec_sub
1861:vec_add
1795:typedef
1755:vec_sub
1749:vec_sub
1410:vec_add
1404:vec_add
1134:typedef
1116:typedef
820:typedef
802:typedef
628:vec_add
601:(GCC),
525:PowerPC
470:PowerPC
435:AltiVec
385:AltiVec
242:RAD5500
231:RAD6000
215:(2010)
170:Power10
91:Qorivva
27:PowerPC
2762:(2006)
2756:(2005)
2732:(2013)
2713:(2021)
2707:(2015)
2701:(2015)
2695:(2013)
2689:(2012)
2687:RDRAND
2683:(2010)
2675:AES-NI
2671:(2003)
2623:(2014)
2598:(2023)
2592:(2022)
2586:(2015)
2580:(2013)
2568:(2009)
2562:(2009)
2556:(2008)
2549:(2007)
2542:(2006)
2536:(2006)
2530:(2004)
2524:(2001)
2518:(1999)
2512:(1998)
2510:3DNow!
2506:(1996)
2271:Helios
2074:POWER9
2069:POWER8
1921:return
1858:return
1746:return
1401:return
1084:#endif
1027:vec_ld
997:vec_ld
934:vec_xl
781:vector
766:Issues
760:POWER9
750:POWER7
728:VMX128
720:based
681:POWER6
658:iTunes
632:opcode
581:x86-64
572:vector
545:32-bit
529:opcode
486:POWER6
456:, and
258:(1996)
256:series
237:RAD750
165:POWER9
160:POWER8
155:POWER7
150:POWER6
144:POWER5
137:POWER4
130:POWER3
123:POWER2
116:POWER1
29:, and
2760:AMD-V
2681:CLMUL
2640:Thumb
2596:AVX10
2534:SSSE3
2474:SPARC
2394:Alpha
2130:(PDF)
2044:Xenon
1906:const
1894:const
1888:sub64
1843:const
1831:const
1825:add64
1740:bmask
1704:amask
1626:const
1593:amask
1587:const
1482:bmask
1476:const
1461:const
1449:const
1443:sub64
1395:cmask
1305:const
1200:cmask
1194:const
1179:const
1167:const
1161:add64
1015:const
985:const
955:const
952:#else
734:Xenon
722:QorIQ
718:e6500
585:IA-32
568:pixel
549:cache
450:Apple
322:Xenon
306:Titan
297:Other
274:Gekko
109:Power
86:QorIQ
74:e6500
69:e5500
23:POWER
2766:VT-d
2754:VT-x
2578:AVX2
2560:F16C
2546:SSE5
2540:SSE4
2528:SSE3
2522:SSE2
2491:SIMD
2428:MDMX
2423:MIPS
2411:NEON
2385:RISC
2381:SIMD
2179:link
2151:link
2091:PA6T
1807:long
1804:long
1767:vec2
1761:vec1
1734:zero
1686:vec2
1680:vec1
1632:zero
1422:vec2
1416:vec1
1389:zero
1365:vec2
1359:vec1
1311:zero
1125:char
1097:and
1078:perm
1072:high
1039:vals
1021:high
1009:vals
979:vals
961:perm
946:vals
883:vals
865:argv
859:char
853:argc
844:main
811:char
707:Cell
705:The
613:and
576:RISC
560:SSE2
484:and
443:SIMD
380:CHRP
375:PReP
370:PAPR
355:RISC
328:X704
317:Cell
254:RS64
200:74xx
64:e600
59:e500
54:e300
49:e200
2736:ASF
2730:TSX
2711:TDX
2705:SGX
2699:MPX
2693:SHA
2650:RVC
2621:ADX
2615:BMI
2590:AMX
2572:FMA
2566:XOP
2554:AVX
2516:SSE
2504:MMX
2495:x86
2479:VIS
2467:VMX
2455:MAX
2438:MXU
2416:SVE
2406:ARM
2399:MVI
2023:IBM
1816:...
1152:...
1143:int
1095:add
1066:low
1045:vec
991:low
928:vec
919:vec
880:int
850:int
841:int
838:...
829:int
615:C++
564:RGB
541:SSE
506:VMX
492:'s
480:'s
478:IBM
454:IBM
221:A2O
218:A2I
207:970
194:7xx
189:4xx
183:6xx
101:IBM
2795::
2269:.
2244:.
2175:}}
2171:{{
2147:}}
2143:{{
2118:^
1939:);
1876:);
1776:);
1773:bw
1770:),
1743:);
1728:bw
1716:bw
1713:);
1710:bw
1692:bw
1689:);
1668:bw
1662:};
1623:};
1584:};
1581:16
1575:16
1569:16
1563:16
1557:15
1551:14
1545:13
1539:12
1533:16
1527:16
1521:16
1515:16
1431:);
1428:cy
1425:),
1398:);
1383:cy
1371:cy
1368:);
1347:cy
1341:};
1302:};
1299:16
1293:16
1287:16
1281:16
1275:15
1269:14
1263:13
1257:12
1251:16
1245:16
1239:16
1233:16
1081:);
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1012:);
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913:};
691:.
656:,
587:.
482:G5
476:,
474:G4
452:,
396:,
213:A2
25:,
2781:.
2497:)
2493:(
2387:)
2383:(
2362:e
2355:t
2348:v
2279:.
2255:.
2230:.
2181:)
2153:)
2139:.
1942:}
1936:b
1933:,
1930:a
1927:(
1918:{
1915:)
1912:b
1903:,
1900:a
1891:(
1879:}
1873:b
1870:,
1867:a
1864:(
1855:{
1852:)
1849:b
1840:,
1837:a
1828:(
1813:;
1779:}
1764:,
1758:(
1752:(
1737:,
1731:,
1725:(
1719:=
1707:,
1701:(
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1683:,
1677:(
1671:=
1659:0
1656:,
1653:0
1650:,
1647:0
1644:,
1641:0
1638:{
1635:=
1620:1
1617:,
1614:1
1611:,
1608:1
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1602:1
1599:{
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1578:,
1572:,
1566:,
1560:,
1554:,
1548:,
1542:,
1536:,
1530:,
1524:,
1518:,
1512:,
1509:7
1506:,
1503:6
1500:,
1497:5
1494:,
1491:4
1488:{
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1473:{
1470:)
1467:b
1458:,
1455:a
1446:(
1434:}
1419:,
1413:(
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1392:,
1386:,
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1362:,
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1290:,
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1227:7
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1206:{
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1191:{
1188:)
1185:b
1176:,
1173:a
1164:(
1149:;
1131:;
1087:}
1075:,
1069:,
1063:(
1057:)
1051:(
1048:=
1036:,
1030:(
1024:=
1006:,
1003:0
1000:(
994:=
976:,
973:0
970:(
964:=
943:,
940:0
937:(
931:=
922:;
910:4
907:,
904:3
901:,
898:2
895:,
892:1
889:{
886:=
871:{
868:)
862:*
856:,
847:(
835:;
817:;
622:"
611:C
566:"
508:(
423:e
416:t
409:v
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