488:. While no one admitted or denied wrongdoing, all individuals settled. All were ordered to pay disgorgements representing losses avoided as well as fines and interest accrued. Burkhardt paid some $ 1.1 million; MacCormack over $ 31,000. Though Wassman was ordered to pay in excess of $ 200,000, and Appleton Jones in excess of $ 300,000, they had spent their illicit gains in the meanwhile and all fines but $ 40,000 each were waived "on demonstrated inability to pay a greater amount."
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KSR used a proprietary processor because 64-bit processors were not commercially available. However, this put the small company in the difficult position of doing both processor design and system design. The KSR processors were introduced in 1991 at 20 MHz and 40 MFlops. At that time, the
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The first KSR1 system was installed in 1991. With new processor hardware, new memory hardware and a novel memory architecture, a new compiler port, a new port of a relatively new operating system, and exposed memory hazards, early systems were noted for frequent system crashes. KSR called their
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of I-cache and D-cache, essentially primary cache. At each node was 32 MB of memory for main cache. The system level architecture was shared virtual memory, which was physically distributed in the machine. The programmer or application only saw one contiguous address space, which was spanned by a
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behavior of the subsequent two instructions that would be initiated during the branch. The choices were: always retain the results, retain results if branch test is true, or retain results if branch test is false. Memory control provided synchronization primitives. I/O instructions were provided.
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or "COMA". Being all cache, memory dynamically migrated and replicated in a coherent manner based on the access pattern of individual processors. The processors were arranged in a hierarchy of rings, and the operating system mediated process migration and device access. Instruction decode was
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KSR refocused its efforts from the scientific to the commercial marketplace, with emphasis on parallel relational databases and OLTP operations. It then got out of the hardware business, but continued to market some of its data warehousing and analysis software products.
314:, and the external I/O unit (XIO). The CEU handled instruction fetch (two per clock), and all operations involving memory, such as loads and stores. 40-bit addresses were used, going to full 64-bit addresses later. The integer unit had 32, 64-bit-wide registers. The
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The KSR processor was a 2-wide VLIW, with instructions of 6 types: memory reference (load and store), execute, control flow, memory control, I/O, and inserted. Execute instructions included arithmetic, logical, and type conversion. They were usually triadic
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KSR, along with many of its competitors (see below), went bankrupt during the collapse of the supercomputer market in the early 1990s. KSR went out of business in
February 1994, when their stock was delisted from the stock exchange.
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In April of 1996, the SEC filed a complaint against the company and several officers (Burkhardt III, the CEO and
President; Peter Appleton Jones, the highest-ranked sales executive; and Karl G Wassman III, the CFO and CAO) for
449:, although memory was not necessarily the root cause of crashes. A few KSR1 models were sold, and as the KSR2 was being rolled out, the company collapsed amid accounting irregularities involving the overstatement of revenue.
219:). Up to 1088 of these processors could be arranged in a single system, with a minimum of eight. The KSR2 doubled the clock rate to 40 MHz and supported over 5000 processors. The KSR-1 chipset was fabricated by
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finop ; movb8_8 %i2,%c10 finop ; cxnop finop ; cxnop add8.ntr 75,%i31,%i31 ; ld8 8(%c10),%c4 finop ; st8 %fp,504(%sp) finop ; cxnop movi8 3, %i0 ; jsr %c14,16(%c4)
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The following example of KSR assembly performs an indirect procedure call to an address held in the procedure's constant block, saving the return address in register
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40-bit address. Traffic between nodes traveled at up to 4 gigabytes per second. The 32 megabytes per node, in aggregate, formed the physical memory of the machine.
347:(DMA) transfers. Inserted memory instructions were used to maintain cache coherency. New coprocessors could be interfaced with the inserted instruction mechanism.
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for six quarters in 1992 and 1993. These individuals and Thomas J MacCormack, director of contracts administration, were also accused of selling KSR stock while
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uses. The TUXEDO transaction monitor for OLTP was also provided. The KAP program (Kuck & Associate
Preprocessor) provided for pre-processing for
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processors could be used in the system, providing scalable I/O. A 1088 node KSR1 could have 510 I/O channels with an aggregate in excess of 15
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location- to reduce storage overheads and to software transparently, dynamically migrate/replicate memory based on where it was utilized; a
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was introduced in 1992, it ran at up to 192 MHz and 192 MFlops, while the 1992 KSR2 ran at 40 MHz and 80 MFlops.
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facility, purchased an enormous number of spare parts, and kept their machines running for years after the demise of KSR.
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243:, addressed the massively parallel database market for commercial applications. The KSR-1 and -2 supported Micro Focus
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The KSR-1 processor was implemented as a four-chip set in 1.2 micrometer complementary metal–oxide–semiconductor (
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from ADB, Inc. Their own product, the KSR Query
Decomposer, complemented the functions of the Oracle product for
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625:"BUSINESS TECHNOLOGY; Pools of Memory, Waves of Dispute" John Markoff, The New York Times - 29 January 1992
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561:"COMPLAINT AGAINST KENDALL SQUARE RESEARCH CORP., HENRY BURKHARDT III, PETER JONES AND KARL WASSMANN III"
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As the company scaled up quickly to enter production, they moved in the late 1980s to 170 Tracer Lane,
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152:(MIT). It was co-founded by Steven Frank and Henry Burkhardt III, who had formerly helped found
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164:. KSR produced two models of supercomputer, the KSR1 and KSR2. It went bankrupt in 1994.
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In the KSR design, all of the memory was treated as cache. The design called for no
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KSR2 ALLCACHE Processor, Router and
Directory (APRD) board with two APRD cells
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were two cycles. The programmer (or compiler) could implicitly control the
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arithmetic was supported. Sixty-four 64-bit wide registers were included.
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for instructions and memory was used. Each node board contained 256
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variant, with programs compiled by a KSR-specific port of the
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in format. Control flow refers to branches and jumps. Branch
215:(MIPS) and 40 million floating-point operations per second (M
508:, and various old-line (and still surviving) companies like
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issuing materially false and misleading financial statements
593:"FINAL JUDGEMENTS ENTERED IN SEC v. KENDALL SQUARE, ET AL"
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The KSR systems ran a specially customized version of the
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unit is discussed below. The XIO had the capacity of 30
278:. The runtime environment was termed PRESTO, and was a
366:, so must be scheduled explicitly, else the resulting
457:ran at 50 MHz and 50 MFlops. When the 64-bit
339:Inserted instructions were forced into a flow by a
160:and was one of the original team that designed the
49:. Unsourced material may be challenged and removed.
306:). These chips were: the cell execution unit, the
675:Defunct computer companies based in Massachusetts
680:Defunct computer companies of the United States
486:in possession of material nonpublic information
16:Former American manufacturer of supercomputers
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670:Companies based in Cambridge, Massachusetts
204:was used. Each KSR1 processor was a custom
665:Computer companies disestablished in 1994
655:American companies disestablished in 1994
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370:means wrong values are sometimes loaded.
109:Learn how and when to remove this message
362:of 2 cycles and the delay slots are not
343:. Inserted load and store were used for
645:1994 disestablishments in Massachusetts
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660:Computer companies established in 1986
650:American companies established in 1986
466:Pacific Northwest National Laboratory
223:while the KSR-2 chipset was built by
150:Massachusetts Institute of Technology
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640:1986 establishments in Massachusetts
602:. No. 96–215. November 12, 1996
140:company headquartered originally in
47:adding citations to reliable sources
685:Defunct computer hardware companies
690:Defunct computer systems companies
470:United States Department of Energy
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534:"Virtual Shared Memory Symposium"
209:reduced instruction set computing
570:. No. 96–79. April 29, 1996
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255:programming languages, and the
213:million instructions per second
34:needs additional citations for
464:One customer of the KSR2, the
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197:cache-only memory architecture
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187:C and FORTRAN compilers. The
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498:MasPar Computer Corporation
496:KSR's competitors included
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441:(COMA) by the trade name
58:"Kendall Square Research"
235:Besides the traditional
146:Cambridge, Massachusetts
405:/s. Interfaces such as
237:scientific applications
130:Kendall Square Research
427:Waltham, Massachusetts
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312:arithmetic logic unit
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383:Harvard architecture
345:direct memory access
185:Green Hills Software
43:improve this article
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241:Oracle Corporation
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502:Thinking Machines
221:Sharp Corporation
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54:Find sources:
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32:This article
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604:. Retrieved
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572:. Retrieved
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537:. Retrieved
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399:input/output
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189:architecture
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154:Data General
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41:Please help
36:verification
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492:Competition
455:Intel 80486
385:, separate
364:interlocked
341:coprocessor
269:source code
239:, KSR with
634:Categories
539:2009-01-23
520:References
360:delay slot
282:compliant
202:pipelining
168:Technology
99:March 2010
69:newspapers
606:August 1,
574:August 1,
459:DEC Alpha
286:manager.
125:KSR1 logo
447:Allcrash
443:Allcache
407:Ethernet
336:quashing
328:register
298:Hardware
272:analysis
231:Software
136:) was a
453:32-bit
421:History
83:scholar
413:, and
368:hazard
310:, the
261:OODBMS
206:64-bit
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596:(PDF)
564:(PDF)
514:Intel
415:HIPPI
280:POSIX
245:COBOL
217:FLOPS
174:OSF/1
162:PDP-8
90:JSTOR
76:books
608:2024
576:2024
512:and
468:, a
411:FDDI
379:home
304:CMOS
274:and
247:and
191:was
181:Unix
179:, a
156:and
62:news
510:IBM
387:bus
356:c14
265:SQL
253:C++
144:in
134:KSR
45:by
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