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LISA' is not focused on the modeling of other on-chip components around the processor core itself, such as peripherals, hardware accelerators, buses and memories; Other languages such as
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did already exist and legacy compiled software images could be executed on the newly created hardware. Another application has been to generate the ISS (
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C Compiler Aided Design of
Application-specific Instruction-set Processors Using the Machine Description Language LISA (Berichte Aus Der Electrotechnik)
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One noticeable branch called LISA+ has been created for handling the modeling of peripherals such as interrupt controllers, timers, etc.
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LISA was initially developed at
Institute for Integrated Signal Processing Systems (ISS) Aachen, belonging to
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LISA: A Uniform ADL for
Embedded Processor Modeling, Implementation and Software Toolsuite Generation
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is LISA 2.0. The language is still in evolution to cover research on processors, including
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LISA has been used to re-implement the hardware of existing processor cores, keeping the
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LISA – machine description language and generic machine model for HW/SW co-design
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https://www.ice.rwth-aachen.de/research/tools-projects/closed-projects/lisa
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Architecture
Exploration for Embedded Processors with LISA
87:. LISA captures the information required to generate
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18:LISA (Language for Instruction Set Architecture)
408:to create processors from LISA 2.0 descriptions
315:V. Zivojnovic, S. Pees, Ch. Schläger, H. Meyr,
144:The language has not been yet standardised by
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319:, Electronic Engineering Times, Oct 7, 1996
331:A. Chattopadhyay, H. Meyr and R. Leupers:
302:search for LISA+ Reference Language Manual
205:Alphabetical list of programming languages
39:Vojin Zivojnovic, Stefan Pees, version 1.0
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337:Processor Description Languages, Volume 1
280:Learn how and when to remove this message
317:LISA bridges gaps in high-tech languages
243:This article includes a list of general
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103:, ...) and implementation hardware (in
176:. The current official version from
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398:project page at RWTH Aachen, Germany
356:A. Hoffmann, H. Meyr, R. Leupers:
249:it lacks sufficient corresponding
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378:GmbH, Germany (August 13, 2004).
335:appearing in P. Mishra, N. Dutt,
324:V. Zivojnovic, S. Pees, H. Meyr,
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118:with the legacy version, as all
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81:instruction set architecture
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152:and is currently owned by
339:, Morgan Kaufmann, 2008.
124:instruction set simulator
101:instruction set simulator
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182:Reconfigurable computing
111:) of a given processor.
422:Specification languages
264:more precise citations.
141:can be used for these.
48:1997, last revised 2007
154:RWTH Aachen University
190:parallel programming
130:processors such the
116:binary compatibility
45:First appeared
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404:is a tool sold by
402:Processor Designer
360:, Springer, 2010.
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16:(Redirected from
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132:ARM architecture
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370:O. Wahlen:
262:introducing
178:RWTH Aachen
170:RWTH Aachen
270:April 2009
245:references
226:References
186:multi-core
97:assembler
85:processor
416:Category
406:Synopsys
199:See also
93:compiler
64:Dialects
258:improve
215:Verilog
210:SystemC
174:Germany
164:History
158:Germany
139:SystemC
134:ISSes.
109:Verilog
53:Website
382:
364:
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310:Papers
247:, but
126:) for
351:Books
156:, in
83:of a
396:LISA
380:ISBN
362:ISBN
341:ISBN
220:VHDL
146:IEEE
128:RISC
105:VHDL
77:LISA
28:LISA
150:ISO
148:or
107:or
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