235:. Obviously there are some advantages over the bulk MOSFETs. The film is very thin in FDSOI devices so that the depletion region covers the whole channel region. In FDSOI the front gate (GOX) supports fewer depletion charges than the bulk so an increase in inversion charges occurs resulting in higher switching speeds. The limitation of the depletion charge by the BOX induces a suppression of the depletion capacitance and therefore a substantial reduction of the subthreshold swing allowing FD SOI MOSFETs to work at lower gate bias resulting in lower power operation. The
261:
463:. The crystalline silicon layer on insulator can be used to fabricate optical waveguides and other optical devices, either passive or active (e.g. through suitable implantations). The buried insulator enables propagation of infrared light in the silicon layer on the basis of total internal reflection. The top surface of the waveguides can be either left uncovered and exposed to air (e.g. for sensing applications), or covered with a cladding, typically made of silica
253:
77:, or SOS). The choice of insulator depends largely on intended application, with sapphire being used for high-performance radio frequency (RF) and radiation-sensitive applications, and silicon dioxide for diminished short-channel effects in other microelectronics devices. The insulating layer and topmost silicon layer also vary widely with application.
165:
451:(SOS) process is widely used in high-performance RF applications. The intrinsic benefits of the insulating sapphire substrate allow for high isolation, high linearity and electro-static discharge (ESD) tolerance. Multiple other companies have also applied SOI technology to successful RF applications in smartphones and cellular radios.
356:
Seed methods - wherein the topmost Si layer is grown directly on the insulator. Seed methods require some sort of template for homoepitaxy, which may be achieved by chemical treatment of the insulator, an appropriately oriented crystalline insulator, or vias through the insulator from the underlying
239:
can reach the minimum theoretical value for MOSFET at 300K, which is 60mV/decade. This ideal value was first demonstrated using numerical simulation. Other drawbacks in bulk MOSFETs, like threshold voltage roll off, etc. are reduced in FDSOI since the source and drain electric fields can't interfere
150:
requirements to account for the buried oxide layer and concerns about differential stress in the topmost silicon layer. The threshold voltage of the transistor depends on the history of operation and applied voltage to it, thus making modeling harder. The primary barrier to SOI implementation is the
471:
The major disadvantage of SOI technology when compared to conventional semiconductor industry is increased cost of manufacturing. As of 2012 only IBM and AMD used SOI as basis for high-performance processors and the other manufacturers (Intel, TSMC, Global
Foundries etc.) used conventional silicon
230:
designs. There are two types of SOI devices: PDSOI (partially depleted SOI) and FDSOI (fully depleted SOI) MOSFETs. For an n-type PDSOI MOSFET the sandwiched n-type film between the gate oxide (GOX) and buried oxide (BOX) is large, so the depletion region can't cover the whole n region. So to some
145:
From a manufacturing perspective, SOI substrates are compatible with most conventional fabrication processes. In general, an SOI-based process may be implemented without special equipment or significant retooling of an existing factory. Among challenges unique to SOI are novel
925:
1268:
710:
881:
862:
151:
drastic increase in substrate cost, which contributes an estimated 10–15% increase to total manufacturing costs. FD-SOI (Fully
Depleted Silicon On Insulator) has been seen as a potential low cost alternative to FinFETs.
729:
225:
is formed on an insulator layer which may be a buried oxide (BOX) layer formed in a semiconductor substrate. SOI MOSFET devices are adapted for use by the computer industry. The buried oxide layer can be used in
637:
322:– the insulating layer is formed by directly bonding oxidized silicon with a second substrate. The majority of the second substrate is subsequently removed, the remnants forming the topmost Si layer.
214:
790:
648:
1269:"Silicon on Insulator (SoI) Market is Anticipated to Surpass USD 2.40 Billion By 2026 | APAC Region to Remain Forerunner in Global Silicon on Insulator Industry"
424:
to improve transistor performance. In
January 2005, Intel researchers reported on an experimental single-chip silicon rib waveguide Raman laser built using SOI.
61:
within the device, thereby improving performance. SOI-based devices differ from conventional silicon-built devices in that the silicon junction is above an
923:, Bajor, George & et al., "Using a rapid thermal process for manufacturing a wafer bonded soi semiconductor", issued 1988-09-13
1366:
990:
484:
As of 2020 the market utilizing the SOI process was projected to grow up by ~15% for the next 5 years according to Market
Research Future group.
388:
7455 CPU in late 2001, currently
Freescale is shipping SOI products in 180 nm, 130 nm, 90 nm and 45 nm lines. The 90 nm
1190:
904:
841:
602:
447:
began development of an SOI process technology utilizing a standard 0.5 ÎĽm CMOS node and an enhanced sapphire substrate. Its patented
1055:
Rong, Haisheng; Liu, Ansheng; Jones, Richard; Cohen, Oded; Hak, Dani; Nicolaescu, Remus; Fang, Alexander; Paniccia, Mario (January 2005).
1143:
1346:
1341:
577:
200:
380:'s 130 nm, 90 nm, 65 nm, 45 nm and 32 nm single, dual, quad, six and eight core processors since 2001.
341:
is a technology developed by
Silicon Genesis Corporation that separates the silicon via stress at the interface of silicon and
1180:
1322:- The 7th session of MIGAS International Summer School on Advanced Microelectronics, devoted to SOI technology and devices
1105:
54:
1214:
335:
which uses ion implantation followed by controlled exfoliation to determine the thickness of the uppermost silicon layer.
1328:- 12th session of the International Summer School on Advanced Microelectronics: "Silicon on Insulator (SOI) Nanodevices"
175:
227:
38:
708:, "SOI wafers with 30-100 Ang. Buried OX created by wafer bonding using 30-100 Ang. thin oxide as bonding layer"
533:
1361:
1351:
260:
1301:
1030:
1243:
376:"Istar" PowerPC-AS microprocessor in 2000. Other examples of microprocessors built on SOI technology include
444:
432:
743:
Yang-Kyu Choi; Asano, K.; Lindert, N.; Subramanian, V.; Tsu-Jae King; Bokor, J.; Chenming Hu (May 2000).
58:
986:
920:
879:, Hiroshi Fujioka, "Method of manufacturing semiconductor on insulator", issued 1991-10-29
876:
857:
785:
724:
705:
1130:
542:
241:
62:
1056:
795:
describes SOI buried oxide (BOX) structures and methods for implementing enhanced SOI BOX structures
85:
SOI technology is one of several manufacturing strategies to allow the continued miniaturization of
504:
448:
421:
138:
116:
74:
744:
102:
93:" (or "More Moore", abbreviated "MM"). Reported benefits of SOI relative to conventional silicon (
1087:
767:
619:
499:
236:
1005:
1186:
1079:
900:
837:
598:
573:
460:
342:
31:
821:
665:
1371:
1356:
1071:
965:
829:
759:
550:
301:
252:
1154:
493:
86:
66:
1108:. Fabtech: The online information source for semiconductor professionals. Archived from
546:
361:
An exhaustive review of these various manufacturing processes may be found in reference
90:
1335:
860:, Atsushi Ogura, "Method of fabricating SOI substrate", issued 1999-03-30
509:
401:
319:
218:
771:
1091:
691:
351:
is a technology developed by Canon which is based on porous silicon and water cut.
620:"Silicon-on-insulator — SOI technology and ecosystem — Emerging SOI applications"
833:
232:
1109:
531:
Celler, G. K.; Cristoloveanu, S. (2003). "Frontiers of silicon-on-insulator".
763:
413:
393:
381:
327:
222:
147:
94:
1083:
416:
technology for each process node, instead focusing on other venues such as
1307:
1006:"Chip Architect: Intel and Motorola/AMD's 130 nm processes to be revealed"
807:
Characterization and
Simulation of SOI MOSFETs with Back Potential Control
17:
397:
70:
1313:
1075:
389:
385:
109:
50:
727:, "Ultra-thin body super-steep retrograde well (SSRW) FET devices"
554:
332:
1298:- a site with extensive information and education for SOI technology
1131:
Chartered expands foundry market access to IBM's 90nm SOI technology
134:
Lower leakage currents due to isolation thus higher power efficiency
409:
304:
process followed by high temperature annealing to create a buried
284:
1325:
1319:
1215:"Silicon-on-Insulator Substrates: The Basis of Silicon Photonics"
822:"1.5 Challenges to Ultralow-Power Semiconductor Device Operation"
473:
428:
417:
373:
244:(FBE)" since the film is not connected to any of the supplies.
405:
377:
369:
158:
53:
semiconductor devices in a layered silicon–insulator–silicon
1310:- a site with extensive information regarding SOI technology
1295:
141:(resistant to soft errors), reducing the need for redundancy
826:
125:
Better yield due to high density, better wafer utilization
1316:- a newsletter about the SOI industry, produced by Soitec
745:"Ultrathin-body SOI MOSFET for deep-sub-tenth micron era"
439:
Use in high-performance radio frequency (RF) applications
112:
due to complete isolation of the n- and p-well structures
105:, which improves power consumption at matched performance
1146:
MMPAs, Envelope
Tracking, Antenna Tuning, FEMs, and MIMO
939:
325:
One prominent example of a wafer bonding process is the
408:
use SOI technology as well. Competitive offerings from
182:
279:-based SOI wafers can be produced by several methods:
101:
Lower parasitic capacitance due to isolation from the
1179:
Reed, Graham T.; Knights, Andrew P. (5 March 2004).
897:
SemiConductor Wafer
Bonding: Science and Technology
595:Silicon-on-Insulator Technology: Materials to VLSI
240:due to the BOX. The main problem in PDSOI is the "
570:SOI design: analog, memory and digital techniques
215:metal–oxide–semiconductor field-effect transistor
1106:"TSMC has no customer demand for SOI technology"
1031:"NXP Semiconductors - Automotive, Security, IoT"
89:devices, colloquially referred to as "extending
427:As for the traditional foundries, on July 2006
122:Reduced temperature dependency due to no doping
568:Marshall, Andrew; Natarajan, Sreedhar (2002).
30:For silicon on insulator optical devices, see
824:. In Lury, S.; Xu, J.; Zaslavsky, A. (eds.).
8:
638:"Silicon On Insulator (SOI) Implementation"
201:Learn how and when to remove this message
27:Technology in semiconductor manufacturing
526:
524:
259:
251:
520:
1267:Future, Market Research (2021-02-17).
1237:
1235:
412:however continue to use conventional
7:
966:"ELTRAN® Novel SOI Wafer Technology"
431:claimed no customer wanted SOI, but
365:Use in the microelectronics industry
331:method developed by the French firm
636:Kodeti, Narayan M. (October 2010).
73:(these types of devices are called
1182:Silicon Photonics: An Introduction
25:
788:, "Vertical MOSFET SRAM cell"
666:"IBM touts chipmaking technology"
372:began to use SOI in the high-end
115:Higher performance at equivalent
1367:Semiconductor device fabrication
1153:. Mobile Experts. Archived from
895:Tong, Q.-Y.; Gösele, U. (1998).
163:
496:- similar technology from Intel
131:No body or well taps are needed
49:) technology is fabrication of
618:Mendez, Horacio (April 2009).
459:SOI wafers are widely used in
396:-based processors used in the
174:comply with Knowledge (XXG)'s
172:This section needs editing to
1:
593:Colinge, Jean-Pierre (1991).
1304:- A search engine for SOI IP
1244:"Silicon on Insulator (SOI)"
1057:"An all-silicon Raman laser"
752:IEEE Electron Device Letters
435:devoted a whole fab to SOI.
300:ygen – uses an oxygen
964:Yonehara, T; Sakaguchi, K.
834:10.1002/9781119069225.ch1-5
217:(MOSFET) device in which a
39:semiconductor manufacturing
1388:
647:. Infotech. Archived from
625:. SOI Industry Consortium.
534:Journal of Applied Physics
231:extent PDSOI behaves like
29:
1202:– via Google Books.
828:. Wiley. pp. 69–81.
692:"Samsung, GF Ramp FD-SOI"
248:Manufacture of SOI wafers
221:layer such as silicon or
1347:Semiconductor technology
1342:Semiconductor structures
764:10.1109/IEDM.1999.824298
1314:Advanced Substrate News
1296:SOI Industry Consortium
1273:GlobeNewswire News Room
445:Peregrine Semiconductor
433:Chartered Semiconductor
472:wafers to build their
265:
257:
128:Reduced antenna issues
119:. Can work at low VDDs
97:) processing include:
820:Balestra, F. (2016).
805:Balestra, F. (1985).
384:adopted SOI in their
302:ion beam implantation
263:
255:
59:parasitic capacitance
1112:on 28 September 2007
809:(PhD). INP-Grenoble.
422:tri-gate transistors
242:floating body effect
63:electrical insulator
43:silicon on insulator
1076:10.1038/nature03723
547:2003JAP....93.4955C
505:Wafer (electronics)
449:silicon on sapphire
213:An SOI MOSFET is a
183:improve the content
75:silicon on sapphire
1010:chip-architect.com
500:Strain engineering
266:
258:
237:subthreshold swing
139:radiation hardened
1192:978-0-470-87034-1
1035:www.freescale.com
906:978-0-471-57481-1
843:978-1-119-06922-5
604:978-0-7923-9150-0
555:10.1063/1.1558223
461:silicon photonics
343:silicon-germanium
264:Smart Cut process
211:
210:
203:
32:silicon photonics
16:(Redirected from
1379:
1284:
1283:
1281:
1280:
1264:
1258:
1257:
1255:
1254:
1242:McLellan, Paul.
1239:
1230:
1229:
1227:
1225:
1210:
1204:
1203:
1201:
1199:
1176:
1170:
1169:
1167:
1165:
1159:
1152:
1144:"Handset RFFEs:
1139:
1133:
1128:
1122:
1121:
1119:
1117:
1102:
1096:
1095:
1061:
1052:
1046:
1045:
1043:
1041:
1027:
1021:
1020:
1018:
1016:
1004:Vries, Hans de.
1001:
995:
994:
993:
989:
983:
977:
976:
970:
961:
955:
954:
952:
950:
936:
930:
929:
928:
924:
917:
911:
910:
892:
886:
885:
884:
880:
873:
867:
866:
865:
861:
854:
848:
847:
817:
811:
810:
802:
796:
794:
793:
789:
782:
776:
775:
749:
740:
734:
733:
732:
728:
721:
715:
714:
713:
709:
702:
696:
695:
694:. 27 April 2018.
688:
682:
681:
679:
677:
662:
656:
655:
653:
642:
633:
627:
626:
624:
615:
609:
608:
590:
584:
583:
565:
559:
558:
528:
455:Use in photonics
315:
314:
313:
278:
277:
276:
206:
199:
195:
192:
186:
167:
166:
159:
21:
1387:
1386:
1382:
1381:
1380:
1378:
1377:
1376:
1362:Nanoelectronics
1352:Microtechnology
1332:
1331:
1292:
1287:
1278:
1276:
1275:(Press release)
1266:
1265:
1261:
1252:
1250:
1241:
1240:
1233:
1223:
1221:
1213:Rigny, Arnaud.
1212:
1211:
1207:
1197:
1195:
1193:
1178:
1177:
1173:
1163:
1161:
1160:on 4 March 2016
1157:
1150:
1141:
1140:
1136:
1129:
1125:
1115:
1113:
1104:
1103:
1099:
1070:(7042): 292–4.
1059:
1054:
1053:
1049:
1039:
1037:
1029:
1028:
1024:
1014:
1012:
1003:
1002:
998:
991:
985:
984:
980:
968:
963:
962:
958:
948:
946:
938:
937:
933:
926:
919:
918:
914:
907:
894:
893:
889:
882:
875:
874:
870:
863:
856:
855:
851:
844:
819:
818:
814:
804:
803:
799:
791:
784:
783:
779:
747:
742:
741:
737:
730:
723:
722:
718:
711:
704:
703:
699:
690:
689:
685:
675:
673:
672:. 29 March 2001
664:
663:
659:
651:
640:
635:
634:
630:
622:
617:
616:
612:
605:
592:
591:
587:
580:
567:
566:
562:
530:
529:
522:
518:
494:Intel TeraHertz
490:
482:
469:
457:
441:
367:
312:
309:
308:
307:
305:
275:
272:
271:
270:
268:
250:
207:
196:
190:
187:
180:
176:Manual of Style
168:
164:
157:
155:SOI transistors
87:microelectronic
83:
67:silicon dioxide
35:
28:
23:
22:
15:
12:
11:
5:
1385:
1383:
1375:
1374:
1369:
1364:
1359:
1354:
1349:
1344:
1334:
1333:
1330:
1329:
1323:
1317:
1311:
1305:
1299:
1291:
1290:External links
1288:
1286:
1285:
1259:
1231:
1205:
1191:
1171:
1134:
1123:
1097:
1047:
1022:
996:
978:
973:Cutting Edge 2
956:
931:
912:
905:
887:
868:
849:
842:
812:
797:
777:
735:
716:
697:
683:
657:
654:on 2013-04-18.
628:
610:
603:
585:
578:
560:
519:
517:
514:
513:
512:
507:
502:
497:
489:
486:
481:
478:
468:
465:
456:
453:
440:
437:
366:
363:
359:
358:
354:
353:
352:
346:
336:
317:
310:
296:plantation of
273:
249:
246:
209:
208:
171:
169:
162:
156:
153:
143:
142:
135:
132:
129:
126:
123:
120:
113:
108:Resistance to
106:
82:
79:
26:
24:
14:
13:
10:
9:
6:
4:
3:
2:
1384:
1373:
1370:
1368:
1365:
1363:
1360:
1358:
1355:
1353:
1350:
1348:
1345:
1343:
1340:
1339:
1337:
1327:
1324:
1321:
1318:
1315:
1312:
1309:
1306:
1303:
1302:SOI IP portal
1300:
1297:
1294:
1293:
1289:
1274:
1270:
1263:
1260:
1249:
1245:
1238:
1236:
1232:
1220:
1219:Photonics.com
1216:
1209:
1206:
1194:
1188:
1184:
1183:
1175:
1172:
1156:
1149:
1147:
1142:Madden, Joe.
1138:
1135:
1132:
1127:
1124:
1111:
1107:
1101:
1098:
1093:
1089:
1085:
1081:
1077:
1073:
1069:
1065:
1058:
1051:
1048:
1036:
1032:
1026:
1023:
1011:
1007:
1000:
997:
988:
982:
979:
974:
967:
960:
957:
945:
944:www.sigen.com
941:
935:
932:
922:
916:
913:
908:
902:
898:
891:
888:
878:
872:
869:
859:
853:
850:
845:
839:
835:
831:
827:
823:
816:
813:
808:
801:
798:
787:
781:
778:
773:
769:
765:
761:
757:
753:
746:
739:
736:
726:
720:
717:
707:
701:
698:
693:
687:
684:
671:
667:
661:
658:
650:
646:
639:
632:
629:
621:
614:
611:
606:
600:
596:
589:
586:
581:
579:0-7923-7640-4
575:
571:
564:
561:
556:
552:
548:
544:
540:
536:
535:
527:
525:
521:
515:
511:
510:Wafer bonding
508:
506:
503:
501:
498:
495:
492:
491:
487:
485:
479:
477:
475:
467:Disadvantages
466:
464:
462:
454:
452:
450:
446:
438:
436:
434:
430:
425:
423:
419:
415:
411:
407:
403:
402:PlayStation 3
399:
395:
391:
387:
383:
379:
375:
371:
364:
362:
355:
350:
347:
344:
340:
337:
334:
330:
329:
324:
323:
321:
320:Wafer bonding
318:
303:
299:
295:
292:eparation by
291:
287:
286:
282:
281:
280:
262:
256:SIMOX process
254:
247:
245:
243:
238:
234:
229:
224:
220:
219:semiconductor
216:
205:
202:
194:
184:
179:
177:
170:
161:
160:
154:
152:
149:
140:
136:
133:
130:
127:
124:
121:
118:
114:
111:
107:
104:
100:
99:
98:
96:
92:
88:
81:Industry need
80:
78:
76:
72:
68:
64:
60:
56:
52:
48:
44:
40:
33:
19:
1277:. Retrieved
1272:
1262:
1251:. Retrieved
1247:
1222:. Retrieved
1218:
1208:
1196:. Retrieved
1181:
1174:
1162:. Retrieved
1155:the original
1145:
1137:
1126:
1114:. Retrieved
1110:the original
1100:
1067:
1063:
1050:
1038:. Retrieved
1034:
1025:
1013:. Retrieved
1009:
999:
981:
972:
959:
947:. Retrieved
943:
934:
915:
896:
890:
871:
852:
825:
815:
806:
800:
780:
758:(5): 254–5.
755:
751:
738:
719:
700:
686:
674:. Retrieved
669:
660:
649:the original
644:
631:
613:
597:. Springer.
594:
588:
569:
563:
538:
532:
483:
470:
458:
442:
426:
368:
360:
348:
338:
326:
297:
293:
289:
283:
267:
212:
197:
188:
181:Please help
173:
144:
103:bulk silicon
84:
65:, typically
57:, to reduce
46:
42:
36:
940:"SIGEN.COM"
645:White Paper
541:(9): 4955.
233:bulk MOSFET
191:August 2023
137:Inherently
91:Moore's Law
1336:Categories
1279:2021-03-07
1253:2021-03-07
987:US 5417180
921:US 4771016
877:US 5061642
858:US 5888297
786:US 7138685
725:US 7002214
706:US 6835633
572:. Kluwer.
516:References
480:SOI market
357:substrate.
339:NanoCleave
18:SOI MOSFET
1326:MIGAS '09
1320:MIGAS '04
1185:. Wiley.
899:. Wiley.
443:In 1990,
414:bulk CMOS
394:Power ISA
382:Freescale
328:Smart Cut
223:germanium
148:metrology
95:bulk CMOS
55:substrate
1308:AMDboard
1248:Semiwiki
1198:22 April
1116:22 April
1084:15931210
1040:22 April
1015:22 April
975:. Canon.
949:22 April
772:43561939
676:22 April
670:cnet.com
488:See also
398:Xbox 360
71:sapphire
1372:Silicon
1357:MOSFETs
1092:4423069
543:Bibcode
476:chips.
390:PowerPC
386:PowerPC
374:RS64-IV
110:latchup
51:silicon
1189:
1090:
1082:
1064:Nature
992:
927:
903:
883:
864:
840:
792:
770:
731:
712:
601:
576:
404:, and
392:- and
349:ELTRAN
345:alloy.
333:Soitec
316:layer.
1224:7 May
1164:2 May
1158:(PDF)
1151:(PDF)
1088:S2CID
1060:(PDF)
969:(PDF)
768:S2CID
748:(PDF)
652:(PDF)
641:(PDF)
623:(PDF)
410:Intel
285:SIMOX
1226:2023
1200:2018
1187:ISBN
1166:2012
1118:2018
1080:PMID
1042:2018
1017:2018
951:2018
901:ISBN
838:ISBN
678:2018
599:ISBN
574:ISBN
474:CMOS
429:TSMC
420:and
418:HKMG
228:SRAM
1072:doi
1068:433
830:doi
760:doi
551:doi
406:Wii
378:AMD
370:IBM
306:SiO
269:SiO
117:VDD
69:or
47:SOI
37:In
1338::
1271:.
1246:.
1234:^
1217:.
1086:.
1078:.
1066:.
1062:.
1033:.
1008:.
971:.
942:.
836:.
766:.
756:21
754:.
750:.
668:.
643:.
549:.
539:93
537:.
523:^
400:,
298:OX
294:IM
288:-
41:,
1282:.
1256:.
1228:.
1168:.
1148:"
1120:.
1094:.
1074::
1044:.
1019:.
953:.
909:.
846:.
832::
774:.
762::
680:.
607:.
582:.
557:.
553::
545::
311:2
290:S
274:2
204:)
198:(
193:)
189:(
185:.
178:.
45:(
34:.
20:)
Text is available under the Creative Commons Attribution-ShareAlike License. Additional terms may apply.
