172:% a simple AHDL up counter, released to public domain 13 November 2006 % % % % like c, ahdl functions must be prototyped % % PROTOTYPE: FUNCTION COUNTER (CLK) RETURNS (CNTOUT); % % function declaration, where inputs, outputs, and bidirectional pins are declared % % also like c, square brackets indicate an array % SUBDESIGN COUNTER ( CLK :INPUT; CNTOUT :OUTPUT; ) % variables can be anything from flip-flops (as in this case), tri-state buffers, state machines, to user defined functions % VARIABLE TIMER: DFF; % as with all hardware description languages, think of this less as an algorithm and more as wiring nodes together % BEGIN DEFAULTS TIMER.prn = VCC; % this takes care of d-ff resets % TIMER.clrn = VCC; END DEFAULTS; TIMER.d = TIMER.q + H"1"; END;
789:
24:
163:
hardware description languages. In contrast to HDLs such as
Verilog and VHDL, AHDL is a design-entry language only; all of its language constructs are synthesizable. By default, Altera software expects AHDL source files to have a .tdf extension (Text Design Files).
41:
189:
243:
826:
88:
845:
266:
60:
67:
444:
74:
288:
140:
107:
236:
56:
429:
819:
45:
474:
355:
276:
144:
128:
469:
229:
850:
81:
812:
293:
252:
711:
449:
335:
318:
303:
298:
152:
688:
34:
629:
515:
639:
530:
520:
345:
703:
650:
535:
434:
340:
748:
604:
330:
308:
624:
540:
132:
555:
402:
424:
271:
658:
796:
760:
155:-like syntax, while its feature set is comparable to the synthesizable portions of the
148:
839:
731:
716:
588:
510:
397:
136:
673:
663:
313:
459:
373:
281:
23:
788:
678:
609:
578:
390:
743:
738:
721:
683:
490:
368:
726:
619:
550:
495:
454:
419:
385:
693:
583:
545:
409:
363:
156:
755:
614:
439:
323:
221:
525:
505:
464:
668:
380:
160:
225:
197:(6.0 ed.). San Jose, CA: Altera Corporation. November 1995
500:
17:
800:
702:
649:
638:
597:
571:
564:
483:
354:
259:
48:. Unsourced material may be challenged and removed.
147:(FPGAs). It is supported by Altera's MAX-PLUS and
820:
237:
8:
216:VHDL and AHDL Digital System Implementation
827:
813:
646:
568:
244:
230:
222:
108:Learn how and when to remove this message
181:
151:series of design software. AHDL has an
795:This electronics-related article is a
57:"Altera Hardware Description Language"
7:
785:
783:
121:Altera Hardware Description Language
46:adding citations to reliable sources
141:complex programmable logic devices
14:
787:
22:
33:needs additional citations for
846:Hardware description languages
145:field-programmable gate arrays
1:
129:hardware description language
799:. You can help Knowledge by
867:
782:
218:. Prentice Hall PTR, 1998.
139:design entry for Altera's
336:Circuit underutilization
319:Reconfigurable computing
346:Hardware acceleration
536:Microchip Technology
341:High-level synthesis
214:Scarpino, Frank A.,
42:improve this article
605:Intel Quartus Prime
331:Soft microprocessor
135:. AHDL is used for
131:(HDL) developed by
127:) is a proprietary
253:Programmable logic
133:Altera Corporation
851:Electronics stubs
808:
807:
777:
776:
773:
772:
769:
768:
556:Texas Instruments
118:
117:
110:
92:
858:
829:
822:
815:
791:
784:
647:
569:
246:
239:
232:
223:
207:
206:
204:
202:
196:
191:MAX+PLUS II AHDL
186:
113:
106:
102:
99:
93:
91:
50:
26:
18:
866:
865:
861:
860:
859:
857:
856:
855:
836:
835:
834:
833:
780:
778:
765:
698:
641:
634:
593:
560:
479:
350:
255:
250:
211:
210:
200:
198:
194:
188:
187:
183:
178:
173:
170:
114:
103:
97:
94:
51:
49:
39:
27:
12:
11:
5:
864:
862:
854:
853:
848:
838:
837:
832:
831:
824:
817:
809:
806:
805:
792:
775:
774:
771:
770:
767:
766:
764:
763:
758:
753:
752:
751:
746:
736:
735:
734:
724:
719:
714:
708:
706:
700:
699:
697:
696:
691:
686:
681:
676:
671:
666:
661:
655:
653:
644:
636:
635:
633:
632:
627:
622:
617:
612:
607:
601:
599:
595:
594:
592:
591:
586:
581:
575:
573:
566:
562:
561:
559:
558:
553:
548:
543:
538:
533:
528:
523:
518:
513:
508:
503:
498:
493:
487:
485:
481:
480:
478:
477:
472:
467:
462:
457:
452:
447:
442:
437:
432:
427:
422:
417:
412:
407:
406:
405:
395:
394:
393:
388:
378:
377:
376:
371:
360:
358:
352:
351:
349:
348:
343:
338:
333:
328:
327:
326:
316:
311:
306:
301:
296:
291:
286:
285:
284:
274:
269:
263:
261:
257:
256:
251:
249:
248:
241:
234:
226:
220:
219:
209:
208:
180:
179:
177:
174:
171:
169:
166:
116:
115:
30:
28:
21:
13:
10:
9:
6:
4:
3:
2:
863:
852:
849:
847:
844:
843:
841:
830:
825:
823:
818:
816:
811:
810:
804:
802:
798:
793:
790:
786:
781:
762:
759:
757:
754:
750:
747:
745:
742:
741:
740:
737:
733:
730:
729:
728:
725:
723:
720:
718:
717:LatticeMico32
715:
713:
710:
709:
707:
705:
701:
695:
692:
690:
687:
685:
682:
680:
677:
675:
672:
670:
667:
665:
662:
660:
657:
656:
654:
652:
648:
645:
643:
637:
631:
628:
626:
623:
621:
618:
616:
613:
611:
608:
606:
603:
602:
600:
596:
590:
587:
585:
582:
580:
577:
576:
574:
570:
567:
563:
557:
554:
552:
549:
547:
544:
542:
539:
537:
534:
532:
529:
527:
524:
522:
519:
517:
514:
512:
509:
507:
504:
502:
499:
497:
494:
492:
489:
488:
486:
482:
476:
473:
471:
468:
466:
463:
461:
458:
456:
453:
451:
448:
446:
443:
441:
438:
436:
433:
431:
428:
426:
423:
421:
418:
416:
413:
411:
408:
404:
401:
400:
399:
398:SystemVerilog
396:
392:
389:
387:
384:
383:
382:
379:
375:
372:
370:
367:
366:
365:
362:
361:
359:
357:
353:
347:
344:
342:
339:
337:
334:
332:
329:
325:
322:
321:
320:
317:
315:
312:
310:
307:
305:
302:
300:
297:
295:
292:
290:
287:
283:
280:
279:
278:
275:
273:
270:
268:
265:
264:
262:
258:
254:
247:
242:
240:
235:
233:
228:
227:
224:
217:
213:
212:
193:
192:
185:
182:
175:
167:
165:
162:
158:
154:
150:
146:
142:
138:
137:digital logic
134:
130:
126:
122:
112:
109:
101:
90:
87:
83:
80:
76:
73:
69:
66:
62:
59: –
58:
54:
53:Find sources:
47:
43:
37:
36:
31:This article
29:
25:
20:
19:
16:
801:expanding it
794:
779:
674:LatticeMico8
664:ARM Cortex-M
640:Intellectual
414:
215:
199:. Retrieved
190:
184:
143:(CPLDs) and
124:
120:
119:
104:
95:
85:
78:
71:
64:
52:
40:Please help
35:verification
32:
15:
704:Open-source
651:Proprietary
460:Flow to HDL
282:Logic block
840:Categories
679:MicroBlaze
630:Simulators
610:Xilinx ISE
176:References
68:newspapers
749:Microwatt
744:Libre-SOC
739:Power ISA
722:OpenCores
684:PicoBlaze
491:Accellera
484:Companies
356:Languages
98:June 2023
727:OpenRISC
642:property
620:ModelSim
598:Software
572:Hardware
565:Products
551:Synopsys
521:Infineon
496:Achronix
455:C to HDL
420:Handel-C
260:Concepts
694:Nios II
584:Stratix
546:Siemens
531:Lattice
516:Cadence
410:SystemC
364:Verilog
201:23 June
168:Example
157:Verilog
149:Quartus
82:scholar
756:RISC-V
615:Vivado
589:Virtex
475:Chisel
440:PALASM
324:Xputer
84:
77:
70:
63:
55:
526:Intel
506:Aldec
465:MyHDL
391:VITAL
195:(PDF)
89:JSTOR
75:books
797:stub
732:1200
689:Nios
669:LEON
470:ELLA
450:CUPL
445:ABEL
425:Lola
415:AHDL
381:VHDL
314:PSoC
294:EPLD
289:CPLD
277:FPGA
267:ASIC
203:2023
161:VHDL
159:and
125:AHDL
61:news
761:Zet
712:JOP
659:ARC
625:VTR
579:iCE
541:NXP
511:Arm
501:AMD
435:UPF
430:PSL
403:DPI
386:AMS
374:AMS
309:GAL
304:PAL
299:PLA
272:SoC
153:Ada
44:by
842::
828:e
821:t
814:v
803:.
369:A
245:e
238:t
231:v
205:.
123:(
111:)
105:(
100:)
96:(
86:·
79:·
72:·
65:·
38:.
Text is available under the Creative Commons Attribution-ShareAlike License. Additional terms may apply.
